CN213212164U

CN213212164U - SiC MOSFET device integrated with gate protection structure

Info

Publication number: CN213212164U
Application number: CN202022112680.XU
Authority: CN
Inventors: 倪炜江
Original assignee: Wuhu Qiyuan Microelectronics Technology Partnership LP
Current assignee: Anhui Xinta Electronic Technology Co.,Ltd.
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2021-05-14
Anticipated expiration: 2030-09-24

Abstract

The utility model relates to the technical field of semiconductors, especially, relate to a SiC MOSFET device of integrated grid protection structure, the SiC MOSFET device includes scribing groove zone and terminal area, p + main ring, bars runway and source runway on the p + main ring, the active area that comprises a plurality of primitive cell structures in parallel and the briquetting metal of source and bars on the active area from the edge to the center in proper order; the grid protection device is characterized in that two or more reverse-series-connected polysilicon pn diode structures are integrated between the grid runway and the source runway and serve as a grid protection structure of the device. The utility model discloses an integrated bars protection device on the chip, when the grid voltage of device surpassed the maximum allowable voltage, the breakdown took place for bars protection device, made bars source voltage clamper at the maximum allowable voltage, protected MOS bars medium and avoided bearing high voltage.

Description

SiC MOSFET device integrated with gate protection structure

Technical Field

The utility model belongs to the technical field of the semiconductor technology and specifically relates to a SiC MOSFET device of integrated bars protection architecture is related to.

Background

The wide bandgap semiconductor material SiC has a bandgap width of about 3 times, a critical breakdown electric field strength of 10 times, and a thermal conductivity of 3 times as compared with Si. Therefore, compared with a Si device, the SiC device has the advantages of higher voltage resistance, higher working frequency, higher temperature resistance and the like. Both theory and practice have demonstrated that SiC MOSFETs have switching frequencies above 10 and better switching efficiency than Si-based IGBTs, and therefore SiC devices will have a very large field of application and market.

The SiC material has two atoms of Si and C, so the thermal oxidation mechanism is more complicated than that of the Si material, and SiC/SiO in the SiC MOS structure₂The interface state density of (A) is more than one order of magnitude higher than that of Si MOS. Simultaneously because of SiC and SiO₂Band offset ratio of Si to SiO of intermediate conduction band₂Even lower, according to Fowler-Nordheim tunneling current formula, the tunneling current increases exponentially, and thus the gate lifetime decreases sharply. In order to obtain a very long device lifetime, the gate-source voltage of the SiC MOSFET, which is used in a much smaller range than the Si device, must be strictly limited in practical applications. This is also a popular approach for the current commercial SiC MOSFET products. However, in practical circuit applications, there are often some current and voltage disturbances, such as sudden on/off of a load, circuit failure, external electromagnetic interference, etc., which may cause voltage fluctuation at the gate, and if the gate voltage fluctuation range exceeds the allowable range of the gate voltage, this may reduce the life and reliability of the gate, and even directly cause the gate dielectric breakdown failure. In order to avoid this phenomenon, the gate protection circuit is usually disposed in the driving circuit in circuit application to protect the gate, which not only increases the cost, but also makes the driving circuit complex and fragile.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an integrated bars protection architecture's SiC MOSFET device, through integrated bars protection device on the chip, when the grid voltage of device surpassed the maximum allowable voltage, the breakdown took place for bars protection device, made bars source voltage clamp at the maximum allowable voltage, protected MOS bars medium and avoided bearing high voltage.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a SiC MOSFET device of integrated grid protection structure, the SiC MOSFET device comprises a scribing groove area and a terminal area, a p + main ring, a grid runway and a source runway on the p + main ring, an active area formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a grid on the active area from the edge to the center in sequence; two or more reverse-series-connected polysilicon pn diode structures are integrated between the gate track and the source track and serve as gate protection structures of devices.

As a further technical scheme, the gate protection structure sequentially comprises a drain electrode, an n + substrate, an n + type buffer layer, an n type drift region, a p + region, a field oxide layer, polycrystalline silicon, an interlayer dielectric, ohmic contact metal, source track metal, gate track metal and a passivation layer from bottom to top.

As a further solution, the polysilicon comprises three portions of different doping, respectively a first highly doped n + type region, an n/p +/n doped region and a second highly doped n + type region, to form two pn diodes with np + and p + n in anti-series.

As a further technical solution, the first highly doped n + type region and the second highly doped n + type region of the polysilicon are respectively connected with the gate track metal and the source track metal in ohmic contact with a low resistance, and the source track metal is also connected with the ohmic contact metal on the p + main ring.

As a further technical scheme, the active region sequentially comprises a drain electrode, an n + substrate, an n + buffer layer, an n-type drift region, an n-type JFET region, a p-well, a p + region, an n + region, a gate dielectric, a polysilicon gate, an interlayer dielectric, a source ohmic contact and a source press metal from bottom to top.

As a further aspect, the electrodes of the source runner are in electrical communication with the source of the active region, and the electrodes of the gate runner are in electrical communication with the gate of the active region.

As a further technical scheme, the gate runway and the source runway are isolated by a passivation layer.

A SiC MOSFET device integrated with a gate protection structure sequentially comprises a scribing groove region, a terminal region, a p + main ring, a gate runway and a source runway on the p + main ring, an active region formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a gate on the active region from the edge to the center; the p + main ring and the gate track are also arranged in the middle area of the SiC MOSFET device, and two or more reverse-series polycrystalline silicon pn diode structures are integrated between the gate track and the source pressing block metal and serve as gate protection structures of the device.

Adopt above-mentioned technical scheme, the utility model discloses following beneficial effect has:

the utility model discloses an integrated bars protection device on the chip, when the grid voltage of device surpassed the maximum allowable voltage, the breakdown took place for bars protection device, made bars source voltage clamper at the maximum allowable voltage, protected MOS bars medium and avoided bearing high voltage. Meanwhile, due to the avalanche resistance robustness of the pn junction, the gate protection device is not damaged after breakdown and can continuously work.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a SiC MOSFET device with an integrated gate protection structure according to an embodiment of the present invention;

FIG. 2 is a graph of intrinsic carrier concentration (ordinate) versus temperature (abscissa) in SiC and Si materials;

fig. 3 is a schematic front structural diagram of a SiC MOSFET device with an integrated gate protection structure according to an embodiment of the present invention;

fig. 4 is a schematic front structural diagram of a SiC MOSFET device with an integrated gate protection structure according to an embodiment of the present invention;

FIG. 5 is a schematic view of the structure of FIG. 3 or FIG. 4 taken along the direction A-A';

icon: 01-terminal and scribe-lane regions, 02-p + main ring, 03-gate racetrack, 04-source racetrack, 05-cell structure, 06-source bulk metal, 07-gate bulk metal, 1-drain, 2-n + substrate, 3-n + buffer layer, 4-n drift region, 5-p + region, 6-field oxide layer, 7-polysilicon, 8-interlayer dielectric, 9-ohmic contact metal, 10-source bulk metal, 11-gate bulk metal, 12-passivation layer, 701-first highly doped n + region 701, 702-n/p +/n doped region, JFET-second highly doped n + region, 21-n type region, 22-p well, 23-p + region, 24-n + region, 25-gate dielectric, 26-polysilicon gate, 27-interlayer dielectric, 28-source ohmic contact and 29-source briquetting metal.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.

The utility model provides a gate protection architecture can be applied to on the multiple SiC transistor chip, like planar MOSFET, ditch groove type MOSFET, integrated Schottky diode's MOSFET, integrated current sensor's MOSFET, SiC IGBT, SiC JFET etc. principle and method are unanimous. The method of the present invention can also be used for transistor devices of other wide bandgap materials, such as GaN, Ga₂O₃And the like in various semiconductor material devices.

Example one

As shown in fig. 1, fig. 3 and fig. 5, the present embodiment provides a SiC MOSFET device with an integrated gate protection structure, which includes, in order from an edge to a center, a scribe lane region and a termination region 01, a p + main ring 02, a gate track 03 and a source track 04 on the p + main ring 02, an active region formed by connecting a plurality of cell structures 05 in parallel, and a source bulk metal 06 and a gate bulk metal 07 on the active region; two or more reverse series-connected polysilicon pn diode structures are integrated between the gate track 03 and the source track 04 to serve as gate protection structures of devices.

A pair of reverse series-connected polysilicon pn diodes D1 and D2 are connected between the grid source in parallel, and the breakdown voltage of D1 and D2 is designed according to the following scheme that when the forward voltage drop of the grid is larger than the allowed maximum forward voltage drop, D1 breaks down, so that the protection of a grid medium is realized. When the gate reverse voltage drop is larger than the maximum allowed reverse voltage drop, D2 breaks down, and the gate dielectric is protected. Due to the very good avalanche breakdown resistance of the pn diode, the voltage remains substantially constant as the current increases when the pn diode breaks down, thus creating a voltage clamping effect.

Preferably, the integrated polysilicon pn diodes D1 and D2 are each made up of multiple diodes to achieve the designed forward and reverse breakdown voltages.

Likewise, the integrated polysilicon pn diode also has junction temperature protection function. When the SiC MOSFET device passes a very large voltage drop and saturation current due to abnormal causes such as short circuit, power consumption is very large, and junction temperature rapidly rises. Along with the rising of junction temperature, the intrinsic carrier concentration of the semiconductor material rises exponentially and sharply, see the formula:

wherein E_GT is the junction temperature, and is the forbidden bandwidth of the semiconductor material. The device fails when the intrinsic carrier concentration approaches the device doping concentration. The higher the forbidden band width, the lower the intrinsic carrier concentration, and therefore the better the high temperature resistance, the higher the allowed junction temperature. Fig. 2 is a graph of intrinsic carrier concentration versus junction temperature for SiC and Si materials. The intrinsic carrier concentration of SiC is about 9 orders of magnitude lower than that of Si at room temperature. The carrier concentration of SiC is much lower than that of Si materials, so SiC devices can withstand much higher junction temperatures than Si devices. Therefore, when the junction temperature rises to a certain temperature, the intrinsic carrier concentration in the integrated polysilicon diode rises sharply to become a conductor firstly, the grid source is short-circuited, the grid voltage drops to be close to zero volt, and the device is turned off, so that the protection of the device is realized.

In this embodiment, as a further technical solution, the gate protection structure sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + type buffer layer 3, an n type drift region 4, a p + region 5, a field oxide layer 6, polysilicon 7, an interlayer dielectric 8, an ohmic contact metal 9, a source track metal 10, a gate track metal 11, and a passivation layer 12.

In this embodiment, as a further solution, the polysilicon 7 includes three portions with different dopings, namely a first highly doped n + type region 701, an n/p +/n doped region 702, and a second highly doped n + type region 703, to form two pn diodes with np + and p + n connected in anti-series. The first highly doped n + type region 701 and the second highly doped n + type region 703 form a low resistance connection of ohmic contact with the gate track metal 11 and the source track metal 10, respectively, and the source track metal 10 is also connected with the ohmic contact metal 9. Thus, the final source also forms an electrical connection with the p + main ring 02. The gate runner metal 11 and the source runner metal 10 are also the two electrodes of the integrated gate protection structure. The n/p +/n doped region 702 is a multi-region differently doped polysilicon, such as an n/p +/n doped structure, which, together with the n + doping at both ends, forms an n +/n/p +/n/n + device structure. Namely the series connection of two diodes of n +/n/p + and p +/n/n +.

In this embodiment, as a further technical solution, the active region sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + buffer layer 3, an n-type drift region 4, an n-type JFET region 21, a p well 22, a p + region 23, an n + region 24, a gate dielectric 25, a polysilicon gate 26, an interlayer dielectric 27, a source ohmic contact 28, and a source briquetting metal 29.

In this embodiment, as a further technical solution, the electrode of the source track 04 is electrically communicated with the source of the active region, and the electrode of the gate track 03 is electrically communicated with the gate of the active region.

In this embodiment, as a further technical solution, the gate track 03 and the source track 04 are isolated by a passivation layer.

Example two

As shown in fig. 1, 4 and 5, the present embodiment provides a SiC MOSFET device with an integrated gate protection structure, which includes, in order from the edge to the center, a scribe line region and a termination region 01, a p + main ring 02, a gate track 03 and a source track 04 on the p + main ring 02, an active region formed by connecting a plurality of cell structures 05 in parallel, and a source bulk metal 06 and a gate bulk metal 07 on the active region; the p + main ring 02 and the gate track 03 also exist in the middle area of the SiC MOSFET device at the same time, so that the non-uniformity of gate voltage among the cells in the SiC MOSFET device is further reduced; two or more reverse series-connected polysilicon pn diode structures are integrated between the gate track 03 and the source briquetting metal 06 as gate protection structures of devices. At this time, a gate protection structure is integrated between the gate track 03 and the source compact metal 06, and the structure is the same as that of the gate protection structure in the first embodiment.

The drain electrode 1 consists of a drain electrode ohmic contact and drain electrode briquetting metal, wherein the briquetting metal is TiNiAg and the like, and the thickness is more than 1 micron. The n + type buffer layer 3 has a doping concentration less than that of the n + substrate, and is typically 1E18cm^-3And the thickness is between 0.5 and 5 microns. The doping concentration and thickness of the n-type drift region 4 are determined according to the designed breakdown voltage of the device, for example, for a 1200V device, the concentration can be 5E15-2E16cm^-3And a thickness of between 7-15 microns. The width of n-type JFET region 21 depends on the device breakdown voltage, the maximum electric field of the gate dielectric at off, and the on-resistance. The doping concentration is greater than that of the n-type drift region 4, which is beneficial to reducing the on-resistance. p-well 22 bulk doping concentration greater than 1E18cm^-3The surface channel region is 1E15-2E17cm^-3Depending on the threshold voltage. Bulk doping of p + region 23 greater than 1E18cm^-3Surface concentration greater than 1E19cm-³And low-resistance ohmic contact is formed. Doping of n + region 24 is greater than 1E19cm^-3. The gate dielectric 25 is typically a thermally oxidized grown SiO₂The thickness is between 20nm and 100nm according to the design of threshold voltage. The polysilicon gate 26 is heavily doped low resistivity polysilicon and the interlayer dielectric 27(ILD) is SiO₂Or SiN, typically greater than 0.5 microns thick. The source ohmic contact 28 is formed by RTA rapid annealing after Ni deposition and the source block metal 29 may be TiAl, or TiNiAg, or TiAu, etc., with a thickness greater than 1 micron.

The ohmic contact in the integrated gate protection structure is completed together with the ohmic contact in the active region. The p + region 5 is coincident with the p + region 23 of the active region and is completed at the same time, as is the interlayer dielectric 8 and interlayer dielectric 27. The gate track metal is identical to the source track metal and the source metal compact, and the process is completed simultaneously. The polysilicon 7 and the polysilicon gate 26 are deposited simultaneously, and after deposition, different regions are doped differently. Wherein the polysilicon gate 26 is heavily doped low resistance polysilicon. The doping of the polysilicon 7 is divided into several regions, forming two pn diodes in anti-series connection of D1 and D2, wherein the reverse breakdown voltage of the two polysilicon diodes is designed to be the maximum allowable voltage of the MOSFET gate. The first highly doped n + type region 701 and the second highly doped n + type region 703 in the polysilicon 7 are both heavily n + doped and form a low resistance connection of ohmic contacts with the gate runner metal and the source runner metal, respectively. The gate runner metal and the source runner metal are also the two electrodes of the integrated gate protection structure. The n/p +/n doped region 702 is a multi-region differently doped polysilicon, such as an n/p +/n doped structure, which, together with the n + doping at both ends, forms an n +/n/p +/n/n + device structure. Namely the series connection of two diodes of n +/n/p + and p +/n/n +. The doping concentration and width of the n-region polysilicon are determined according to the designed breakdown voltage.

The n-type doping and the p-type doping mentioned in the embodiments of the present invention are relative, and may also be referred to as the first doping and the second doping, i.e., the interchanging of the n-type and the p-type is also applicable to the device.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A SiC MOSFET device integrated with a gate protection structure sequentially comprises a scribing groove region, a terminal region, a p + main ring, a gate runway and a source runway on the p + main ring, an active region formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a gate on the active region from the edge to the center; the grid protection device is characterized in that two or more reverse-series-connected polysilicon pn diode structures are integrated between the grid runway and the source runway and serve as a grid protection structure of the device.

2. The SiC MOSFET device of claim 1, wherein the gate protection structure comprises, in order from bottom to top, a drain electrode, an n + substrate, an n + buffer layer, an n-drift region, a p + region, a field oxide layer, polysilicon, an interlayer dielectric, an ohmic contact metal, a source runner metal, a gate runner metal, and a passivation layer.

3. The integrated gate protection structure SiC MOSFET device of claim 2, wherein the polysilicon comprises three portions of different doping, a first highly doped n + type region, an n/p +/n doped region, and a second highly doped n + type region, respectively, to form two pn diodes with np + in anti-series with p + n.

4. The integrated gate protection structure SiC MOSFET device of claim 3, wherein the first and second highly doped n + type regions of polysilicon form a low resistance connection of ohmic contacts with the gate runner metal and the source runner metal, respectively, and the source runner metal is also connected with the ohmic contact metal on the p + main ring.

5. The SiC MOSFET device with an integrated gate protection structure of claim 1, wherein the active region comprises a drain electrode, an n + substrate, an n + buffer layer, an n-type drift region, an n-type JFET region, a p well, a p + region, an n + region, a gate dielectric, a polysilicon gate, an interlayer dielectric, a source ohmic contact and a source blocking metal in sequence from bottom to top.

6. The integrated gate protection structure SiC MOSFET device of claim 1, wherein the electrodes of the source runner are in electrical communication with the source of the active region and the electrodes of the gate runner are in electrical communication with the gate of the active region.

7. The SiC MOSFET device of claim 1, wherein the gate runner and the source runner are separated by a passivation layer.

8. A SiC MOSFET device integrated with a gate protection structure sequentially comprises a scribing groove region, a terminal region, a p + main ring, a gate runway and a source runway on the p + main ring, an active region formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a gate on the active region from the edge to the center; the p + main ring and the gate runway are simultaneously arranged in the middle area of the SiC MOSFET device, and two or more reverse series-connected polycrystalline silicon pn diode structures are integrated between the gate runway and source voltage block metal and serve as gate protection structures of the device.