CN213186054U - Differential amplifier based on negative impedance compensation - Google Patents
Differential amplifier based on negative impedance compensation Download PDFInfo
- Publication number
- CN213186054U CN213186054U CN202021599297.5U CN202021599297U CN213186054U CN 213186054 U CN213186054 U CN 213186054U CN 202021599297 U CN202021599297 U CN 202021599297U CN 213186054 U CN213186054 U CN 213186054U
- Authority
- CN
- China
- Prior art keywords
- transistor
- terminal
- differential
- voltage
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides a differential amplifier based on negative impedance compensation increases through connecting negative impedance compensating circuit at differential amplifier circuit's output differential amplifier's output impedance, thereby increases differential amplifier's gain, just additional pole can not be introduced to differential amplifier's structure to can not produce negative effects to the high frequency response of amplifier, can realize higher bandwidth. In addition, the substrate voltage of the tail current tube is adjusted through the substrate adjusting circuit so as to adjust the threshold voltage of the tail current tube, so that the current generated by the tail current tube can be adaptively adjusted to be a constant current under the condition that parameters such as power supply voltage or process temperature change, the differential amplifier is ensured to have high gain and good stability, and the differential amplifier is suitable for high-speed low-voltage application occasions.
Description
Technical Field
The utility model belongs to the technical field of differential amplifier, specifically relate to a differential amplifier based on negative impedance compensation.
Background
Differential amplifiers play an important role in many analog and mixed signal systems. Implementing high gain amplifiers with large gain-bandwidth products during supply voltage reduction requires innovative circuit design and integrated circuit process technology advances.
Cascode differential amplifiers using transistor "stacking" have been widely used in the past to achieve high dc gain, but their output swing is limited. As feature sizes decrease into the deep sub-micron region, the supply voltage also decreases. As the power supply voltage decreases, the number of transistors that can be stacked between the power supply voltage terminal and the ground terminal decreases significantly, which affects the gain of the differential amplifier, thereby limiting the application of the differential amplifier in low voltage processes. It then arose from a method based on gain multiplication by cascading two or more lower gain stages, which, although high dc gain can be achieved, has a significant compensation requirement that limits the high frequency performance of the cascaded amplifier in feedback applications due to the excessive phase shift introduced by the cascade. Currently, the low power consumption requirement is met by increasing the output impedance of the basic gain stage to achieve gain enhancement, which proves to be the most efficient way to achieve high gain and high gain-bandwidth products.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a differential amplifier based on negative impedance compensation to solve the prior art and need improve the gain through the cascaded mode of multistage amplifier circuit and can't satisfy the problem of low pressure high speed application occasion.
A negative impedance compensation based differential amplifier comprising: a differential amplifying circuit and a negative impedance compensating circuit connected to an output terminal of the differential amplifying circuit,
the first input end of the differential amplifying circuit is used for receiving a first input signal, the second input end of the differential amplifying circuit is used for receiving a second input signal, the difference value between the first input signal and the second input signal is a first difference value, the first output end of the differential amplifying circuit is used for outputting a first output signal, the second output end of the differential amplifying circuit is used for outputting a second output signal, the difference value between the first output signal and the second output signal is a second value, and the ratio between the second value and the first value is the gain of the differential amplifier,
the impedance compensation circuit is used for increasing the output impedance of the differential amplification circuit, thereby increasing the gain,
wherein the impedance compensation circuit comprises a first transistor, a second transistor, and a first current source for providing a bias current to the first and second transistors,
the first end of the first transistor is connected with the first output end of the differential amplification circuit, the second end of the first transistor and the first end of the first current source are connected with a first node, the second end of the first current source is grounded,
a first terminal of the second transistor is connected to the second output terminal of the differential amplification circuit, a second terminal thereof is connected to the first node,
the control end of the first transistor is connected with the first end of the second transistor, and the control end of the second transistor is connected with the first end of the first transistor.
Preferably, the first input terminal of the differential amplifier circuit is a non-inverting input terminal of the differential amplifier circuit, the second input terminal of the differential amplifier circuit is an inverting input terminal of the differential amplifier circuit, and the differential amplifier circuit is further provided with a power supply voltage terminal and a ground terminal for receiving a power supply voltage.
Preferably, the first transistor and the second transistor are both NMOS transistors.
Preferably, the differential amplifier circuit is a cascade amplifier circuit.
Preferably, the differential amplification circuit includes: a third to a tenth transistor and a second current source, the third transistor being a tail current pipe of the differential amplifying circuit,
a fourth transistor and a fifth transistor form a differential input pair transistor of the differential amplification circuit, a control end of the fourth transistor is a first input end of the differential amplification circuit, a control end of the fifth transistor is a second input end of the differential amplification circuit, the fourth transistor is connected with the power supply voltage end through a sixth transistor, the fifth transistor is connected with the power supply voltage end through a seventh transistor, the sixth transistor and the seventh transistor are symmetrical load transistors, a second node where the fourth transistor and the sixth transistor are connected is a first output end of the differential amplification circuit, and a third node where the fifth transistor and the seventh transistor are connected is a second output end of the differential amplification circuit,
a first terminal of the eighth transistor is grounded through a ninth transistor, a second terminal is connected to the power supply voltage terminal,
control ends of the eighth transistor, the sixth transistor and the seventh transistor are all connected with a fourth node, the fourth node is a node where the eighth transistor and the ninth transistor are connected,
the second current source and the tenth transistor are connected in series between the power supply voltage terminal and a ground terminal, a node at which the second current source and the tenth transistor are connected is a fifth node,
and the control end of the third transistor, the control end of the ninth transistor and the control end of the tenth transistor are all connected with the fifth node.
Preferably, the differential amplifier further comprises a substrate voltage regulating circuit, the substrate voltage regulating circuit is configured to regulate a substrate voltage of a tail current tube of the differential amplifier, the tail current tube is connected between the power supply voltage end and a ground end, a control end of the tail current tube receives a constant current control voltage, the constant current control voltage is configured to control the tail current tube to generate a constant current,
when the threshold voltage of the tail current tube needs to be increased, the substrate voltage regulating circuit controls the substrate voltage to be less than 0, so that the threshold voltage of the tail current tube is increased,
when the threshold voltage of the tail current tube needs to be reduced, the substrate voltage regulating circuit controls the substrate voltage to be larger than 0, so that the threshold voltage of the tail current tube is reduced.
Preferably, the substrate voltage adjusting circuit includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a third current source, and an error amplifier,
the eleventh transistor and the third current source are connected in series between the power supply voltage terminal and a ground terminal, a sixth node where the eleventh transistor and the third current source are connected is connected to the first input terminal of the error amplifier,
the twelfth transistor and the eleventh transistor constitute a current mirror such that currents flowing through the eleventh transistor and the twelfth transistor are the same, the twelfth transistor is connected in series with the thirteenth transistor between the power supply voltage terminal and a ground terminal, a seventh node at which the twelfth transistor and the thirteenth transistor are connected is connected to the second input terminal of the error amplifier,
the signal output by the output end of the error amplifier is used for controlling the substrate voltage of the tail current tube,
a control terminal of the thirteenth transistor receives a reference voltage such that when the power supply voltage of the power supply voltage terminal is maintained at a constant voltage, voltages of the first input terminal and the second input terminal of the error amplifier are the same, a signal of an output of the error amplifier is 0, thereby making the substrate voltage 0,
when the environment of the application environment of the differential amplifier changes to increase the threshold voltage of the eleventh transistor and the thirteenth transistor, the threshold voltage of the tail current tube needs to be reduced, the voltage of the second input terminal of the error amplifier is increased to be smaller than the voltage of the first input terminal of the error amplifier, so that the output signal of the output terminal of the error amplifier controls the substrate voltage to be greater than 0, and the threshold voltage of the tail current tube is reduced,
when the environment of the application environment of the differential amplifier changes to reduce the threshold voltage of the eleventh transistor and the thirteenth transistor, the threshold voltage of the tail current tube needs to be increased, the power of the second input terminal of the error amplifier is greater than the voltage of the first input terminal, and the substrate voltage is controlled to be less than 0 by the signal output by the output terminal of the error amplifier, so that the threshold voltage of the tail current tube is increased.
Preferably, a first terminal of the eleventh transistor and a first terminal of the third current source are connected to the sixth node, the third current source is connected to the power supply voltage terminal, a second terminal of the eleventh transistor is grounded,
a control end of the eleventh transistor and a control end of the twelfth transistor are both connected to the sixth node, a first end of the twelfth transistor and a first end of the thirteenth transistor are connected to the seventh node, a second end of the thirteenth transistor is connected to the power supply voltage terminal, and a second end of the twelfth transistor is grounded.
Preferably, the substrates of the eleventh transistor and the twelfth transistor are both connected to the output terminal of the error amplifier.
The utility model discloses beneficial effect: the output impedance of the differential amplifier is increased by connecting the negative impedance compensation circuit to the output end of the differential amplification circuit, so that the gain of the differential amplifier is increased, an extra pole is not introduced into the structure of the differential amplifier, the high-frequency response of the amplifier is not negatively influenced, and higher bandwidth can be realized. In addition, the substrate voltage of the tail current tube is adjusted through the substrate voltage adjusting circuit so as to adjust the threshold voltage of the tail current tube, so that the current generated by the tail current tube can be adaptively adjusted to be a constant current under the condition that parameters such as power supply voltage or process temperature change, the differential amplifier is ensured to have high gain and good stability, and the differential amplifier is suitable for high-speed low-voltage application occasions.
Drawings
Fig. 1 is a schematic structural diagram of a differential amplifier based on negative impedance compensation according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a differential amplifier based on negative impedance compensation according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a differential amplifier based on negative impedance compensation according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments generated by the ordinary skilled in the art without creative work all belong to the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only intended to indicate technical belongings or features of the present invention.
The utility model provides a differential amplifier based on negative impedance compensation, figure 1 is the foundation the utility model discloses differential amplifier's based on negative impedance compensation structural schematic diagram of first embodiment, figure 2 is the foundation the utility model discloses differential amplifier's based on negative impedance compensation structural schematic diagram of second embodiment, figure 3 is the foundation the utility model discloses differential amplifier's based on negative impedance compensation structural schematic diagram of third embodiment. The present invention will be described in detail with reference to fig. 1 to 3.
As shown in fig. 1, in the first embodiment, the differential amplifier based on negative impedance compensation mainly includes a differential amplification circuit and a negative impedance compensation circuit connected to an output terminal of the differential amplification circuit. The differential amplifier comprises a differential amplifier circuit, a first input end and a second input end, wherein the first input end of the differential amplifier circuit is used for receiving a first input signal, the second input end of the differential amplifier circuit is used for receiving a second input signal, the difference value between the first input signal and the second input signal is a first difference value, the first output end of the differential amplifier circuit is used for outputting a first output signal, the second output end of the differential amplifier circuit is used for outputting a second output signal, the difference value between the first output signal and the second output signal is a second value, and the ratio of the second value to the first value is the gain of the differential amplifier. For example, the first input terminal of the differential amplifier circuit is a non-inverting input terminal, and the second input terminal of the differential amplifier circuit is an inverting input terminal, so that the first input terminal and the second input terminal of the differential amplifier circuit respectively receive the first input signal Vip and the second input signal Vin in the differential input pair, so as to convert the differential input pair into a differential output pair through the differential amplifier circuit. The differential mode voltage of the differential output pair is greater than that of the differential input pair, that is, the differential amplifying circuit is used for amplifying and outputting the differential mode signal between the input signals. The first output signal Vop in the differential output pair is output through the first output terminal of the differential amplification circuit, and the first output signal Von in the differential output pair is output through the second output terminal of the differential amplification circuit. In the first embodiment, the differential amplifier is a fully differential amplifier, and the differential amplifier circuit is further provided with a power supply voltage terminal for receiving a power supply voltage Vdd and a ground terminal.
The impedance compensation circuit is used for increasing the output impedance of the differential amplification circuit so as to increase the gain, wherein the gain is the ratio of the first difference value to the second difference value. Wherein the first difference is a difference between the first output signal Vop and the second output signal Von, and the first difference is a difference between the first input signal Vip and the second input signal Vin. The impedance compensation circuit comprises a first transistor M1, a second transistor M2 and a first current source A1, wherein the first current source A1 is used for providing a bias current I1 for the first transistor M1 and the second transistor M2. The first terminal of the first transistor M1 is connected to the first output terminal of the differential amplifier circuit, the second terminal thereof is connected to the first terminal of the first current source a1 at the first node, and the second terminal of the first current source a1 is grounded. A first end of the second transistor M2 is connected to the second output end of the differential amplification circuit, and a second end is connected to the first node. The control terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, and the control terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The first end of each transistor refers to one of a drain and a source, and the second end of each transistor refers to the other of the drain and the source. Further, the differential amplification circuit may be a cascade (Cascode) amplification circuit formed by stacking a plurality of transistors, the differential amplifier includes a plurality of stages of cascade-connected differential amplification circuits, and the differential amplification circuit connected to the negative impedance compensation circuit is a first stage differential amplification circuit in the plurality of stages of cascade-connected differential amplification circuits.
A specific implementation manner of the differential amplifier circuit is shown in a schematic structural diagram of the differential amplifier in fig. 2. In the second embodiment, the negative impedance compensation circuit is the same as the first embodiment, and the description thereof will not be repeated. The differential amplifying circuit comprises third to tenth transistors and a second current source, and a third transistor M3 is a tail current tube of the differential amplifying circuit.
Fourth transistor M4And a fifth transistor M5A differential input pair of transistors constituting the differential amplifier to receive two input signals Vip, Vin respectively, the fourth transistor M4Through a sixth transistor M6Connected to the supply voltage Vdd terminal, the fifth transistor M5Through a seventh transistor M7The sixth transistor M is connected with the power supply voltage Vdd end6And a seventh transistor M7Is a symmetrical load tube. A second node at which the fourth transistor M4 and the sixth transistor M6 are connected is a first output terminal of the differential amplifier circuit, and a third node at which the fifth transistor M5 and the seventh transistor M7 are connected is a second output terminal of the differential amplifier circuit. The eighth transistor M8Through a ninth transistor M9A ground, a second terminal connected to the supply voltage Vdd terminal, and an eighth transistor M8The sixth transistor M6And the seventh transistor M7The control ends of the first and second transistors are all connected with a fourth node, and the fourth node is the eighth transistor M8And the ninth transistor M9A connected node. The second current source A2 and the tenth transistor M10The second current source A2 and the tenth transistor M are connected in series between the power voltage Vdd terminal and the ground terminal10The connected node is the fifth node. The ninth transistor M9And a tenth transistor M10A current mirror is configured to flow through the ninth transistor M9And a tenth transistor M10Is the bias current I2 outputted by the second current source a2, so as to form a constant current control voltage at the control end of the tail current tube M3 at the fifth node. The control end of the constant current tube and the ninth transistor M9And said tenth transistor M10The control ends of the first and second nodes are all connected with the fifth node.
When the output end of the differential amplifier circuit shown in fig. 2 is not connected to the negative impedance compensation circuit, the calculation formulas of the output impedance rout and the gain Av of the differential amplifier are respectively as follows:
when the output end of the differential amplifier circuit shown in fig. 2 is connected to the negative impedance compensation circuit, the calculation formulas of the output impedance rout 'and the gain Av' of the differential amplifier are respectively as follows:
in the above formula, ro5 is the output impedance of the fifth transistor M5, ro7 is the output impedance of the first transistor M7, gm5 is the transconductance of the fifth transistor M5, and gm2 is the transconductance of the second transistor M2. As can be seen from the comparison of the above formulas, the denominator of the output impedance and the gain of the differential amplifier based on the negative impedance compensation provided by the present invention reduces the gm2 ro2 ro7 term compared to the denominator of the output impedance and the gain of the differential amplifier without increasing the impedance compensation circuit. Therefore, the utility model discloses a negative impedance compensating circuit is connected at differential amplifier circuit's output, can effectually improve differential amplifier's gain, just the utility model provides a differential amplifier's structure can not introduce extra limit to can not produce negative effects to amplifier's high frequency response, can realize higher bandwidth.
Furthermore, as shown in fig. 3, in the third embodiment, the differential amplifier based on load impedance compensation further includes a substrate voltage adjusting circuit, the substrate voltage adjusting circuit is used for adjusting the substrate voltage Vbgn of the tail current tube M3 of the differential amplifier, the tail current tube M3 is connected between the Vdd terminal of the power supply voltage and the ground terminal, the control terminal of the tail current tube M3 receives a constant current control voltage, and the constant current control voltage is used for controlling the tail current tube to generate a constant current. When the threshold voltage of the tail current tube M3 needs to be increased, the substrate voltage regulating circuit controls the substrate voltage Vbgn to be less than 0, so that the threshold voltage of the tail current tube M3 is increased, and when the threshold voltage of the tail current tube needs to be decreased, the substrate voltage regulating circuit controls the substrate voltage to be greater than 0, so that the threshold voltage of the tail current tube M3 is decreased.
Specifically, as shown in fig. 3, the substrate voltage adjusting circuit includes: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a third current source A3, and an error amplifier AF. The tail current tube M3 is connected between a power supply voltage Vdd terminal and a ground terminal, and the tail current tube M3 generates a constant current under a constant current control voltage at a control terminal, so as to provide a constant bias current for a differential signal input pair tube (a fourth transistor M4 and a fifth transistor M5) connected with the tail current tube M3 and a load tube (a sixth transistor M6 and a seventh transistor M7) connected with the differential signal input pair tube.
The eleventh transistor M11 and the third current source A3 are connected in series between a power supply voltage terminal and a ground terminal, a sixth point at which the eleventh transistor M11 and the third current source A3 are connected is connected to the first input terminal of the error amplifier AF, and the eleventh transistor M11 and the twelfth transistor M12 form a current mirror, so that the currents flowing through the eleventh transistor M11 and the twelfth transistor M12 are the same, i.e., the current I3 output by the third current source A3 is the same. The twelfth transistor M12 and the thirteenth transistor M13 are connected in series between the power supply voltage Vdd terminal and the ground terminal. A seventh node at which the twelfth transistor M12 and the thirteenth transistor M13 are connected is connected to the second input terminal of the error amplifier AF, and a signal output by the output terminal of the error amplifier AF is used for controlling the substrate voltage Vbgn of the substrate of the tail current tube M3. The control terminal of the thirteenth transistor M13 receives a reference voltage Vcm, so that when the ambient temperature of the application environment of the differential amplifier is not changed or the change of the ambient temperature does not change the threshold voltages of the eleventh transistor and the thirteenth transistor, which indicates that the threshold voltage of the tail current tube does not change in the period, the threshold voltage of the tail current tube does not need to be adjusted, at this time, the voltages of the first input terminal and the second input terminal of the error amplifier AF are the same, the output signal of the error amplifier AF is 0, and thus the substrate voltage Vbgn is 0. When the environmental temperature of the application environment of the differential amplifier changes, so that the threshold voltages of the eleventh transistor and the thirteenth transistor increase, which indicates that the threshold voltage of the tail current tube also increases correspondingly during the period, the threshold voltage of the tail current tube needs to be decreased, at this time, the voltage of the second input terminal of the error amplifier AF increases to be greater than the voltage of the first input terminal of the error amplifier AF, so that the output signal of the output terminal of the error amplifier AF controls the substrate voltage Vbgn to be greater than 0, and the threshold voltage of the tail current tube M3 decreases. When the ambient temperature of the application environment of the differential amplifier changes, so that the threshold voltages of the eleventh transistor and the thirteenth transistor decrease, which indicates that the threshold voltage of the tail current tube also decreases correspondingly during the period, the threshold voltage of the tail current tube needs to be increased, at this time, the voltage of the second input terminal of the error amplifier AF is greater than the voltage of the first input terminal of the error amplifier AF, and the substrate voltage Vbgn is controlled to be less than 0 by the signal output by the output terminal of the error amplifier AF, so that the threshold voltage of the constant current tube increases.
When the power supply voltage Vdd decreases, the constant current tube MSThe drain-source voltage margin of the operational amplifier is compressed, so that the current of the operational amplifier is reduced, and the gain and the bandwidth of the operational amplifier are influenced. Therefore, when the power supply voltage is low, the change of the ambient temperature has a large influence on the threshold voltage of the transistor, we set the reference voltage to establish the balanced state of the error amplifier (the sizes of the positive and negative phase input ends are equal), and the balanced state of the error amplifier is changed by the change of the ambient temperature, so the signal fed back by the output end of the error amplifier reflects the influence of the ambient temperature on the size of the threshold voltage of the tail current tube M3, so that we can adjust the substrate voltage Vbgn according to the feedback signal output by the error amplifier, and finally make the error amplifier in the balanced state, so as to adjust the threshold voltage of the tail current tube M3 to be adjusted to be small during the increase due to the change of the ambient temperature, and to be large during the decrease due to the change of the ambient temperature, and finally make the tail current tube M3 to basically keep the output current constant during the change of the power supply voltage and the change of the ambient temperature .
Since the relationship between the threshold voltage Vths of the tail current tube M3 and the substrate voltage Vbgn of the constant current tube is a negative correlation relationship, that is, the larger the substrate voltage Vbgn is, the smaller the threshold voltage Vths is, and the smaller the substrate voltage Vbgn is, the larger the threshold voltage Vths is. Therefore, in the present invention, we can control the substrate voltage Vbgn by changing the magnitude of the voltage difference between the two input terminals of the error amplifier AF according to the magnitude of the threshold voltages of the eleventh transistor and the thirteenth transistor, so that the output terminal of the error amplifier AF outputs a corresponding signal, thereby realizing that the threshold voltage of the tail current tube M3 is adjusted to change correspondingly during the change of the ambient temperature by adjusting the substrate voltage Vbgn to follow the change of the ambient temperature, and the current generated by the tail current tube M3 is adaptively adjusted to be kept constant. The output signal via the error amplifier AF is in this embodiment applied directly to the substrate of the tail current tube M3, i.e. the output of the error amplifier is connected directly to the substrate end of the tail current tube M3.
As shown in fig. 3, in the embodiment of the present invention, the first input terminal of the error amplifier AF is a non-inverting input terminal, and the second input terminal of the error amplifier AF is an inverting input terminal. A first terminal of the eleventh transistor M11 and a first terminal of the third current source A3 are connected to the sixth node, the third current source A3 is connected to the Vdd terminal, and a second terminal of the eleventh transistor M11 is connected to ground. A control terminal of the eleventh transistor M11 and a control terminal of the twelfth transistor M12 are both connected to the sixth node. A first terminal of the twelfth transistor M12 and a first terminal of the thirteenth transistor M13 are connected to the seventh node, a second terminal of the thirteenth transistor M13 is connected to the Vdd terminal, and a second terminal of the twelfth transistor M12 is grounded. Furthermore, the present invention provides a substrate voltage adjusting circuit, which can be further used to adjust the substrate voltage of its own transistor, and therefore, in the embodiment of the present invention, the substrates of the eleventh transistor M11 and the twelfth transistor M12 are both connected to the output terminal of the error amplifier AF, so that the substrate voltages of the eleventh transistor M11 and the twelfth transistor M12 are both changed following the change of the threshold voltages of the eleventh transistor and the thirteenth transistor. In the embodiment of the present invention, the tail current tube M3, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all NMOS tubes.
We can set the size of the reference voltage Vcm to a fixed size, so that the sizes of the two input terminals of the error amplifier AF are equal during the threshold voltages of the eleventh transistor and the thirteenth transistor are not changed, and the output of the error amplifier AF only changes with the change of the threshold voltages of the eleventh transistor and the thirteenth transistor during the threshold voltages of the eleventh transistor and the thirteenth transistor. We can therefore determine the magnitude of the reference voltage Vcm by the following calculation formula:
wherein Vth13 is a threshold voltage of the thirteenth transistor, Vth11 is a threshold voltage of the eleventh transistor, I3 is a current output by the third current source, and β 1 is a step-through factor of the eleventh transistor.
When the threshold voltages of the eleventh transistor and the thirteenth transistor increase, i.e., Vth13 and Vth11 increase, the voltage of the non-inverting input terminal of the error amplifier is greater than the voltage of the inverting input terminal, the signal of the output of the error amplifier is greater than 0, i.e., the substrate voltage Vbgn is greater than 0, so that the threshold voltage Vths of the tail current tube M3 decreases.
When the threshold voltages of the eleventh transistor and the thirteenth transistor are reduced, that is, Vth13 and Vth11 are reduced, the voltage of the non-inverting input terminal of the error amplifier is greater than the voltage of the inverting input terminal, the signal of the output of the error amplifier is less than 0, that is, the substrate voltage Vbgn is less than 0, so that the threshold voltage Vths of the tail current tube M3 is increased.
The utility model discloses a connect negative impedance compensating circuit at differential amplifier circuit's output and increase differential amplifier's output impedance, thereby increase differential amplifier's gain, in addition, substrate voltage through substrate voltage regulating circuit adjustment tail current pipe, in order to adjust through adjusting substrate voltage adjusts the threshold voltage of tail current pipe, thereby make the tail current pipe is in under the variation situation of supply voltage or technology temperature isoparametric, adjustment that can self-adaptation the electric current of the production of tail current pipe is a constant current, has ensured differential amplifier still has better stability when having high-gain, so that differential amplifier adapts to the high-speed low pressure application.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A negative impedance compensation based differential amplifier, comprising: a differential amplifying circuit and a negative impedance compensating circuit connected to an output terminal of the differential amplifying circuit,
the first input end of the differential amplifying circuit is used for receiving a first input signal, the second input end of the differential amplifying circuit is used for receiving a second input signal, the difference value between the first input signal and the second input signal is a first difference value, the first output end of the differential amplifying circuit is used for outputting a first output signal, the second output end of the differential amplifying circuit is used for outputting a second output signal, the difference value between the first output signal and the second output signal is a second value, and the ratio between the second value and the first value is the gain of the differential amplifier,
the impedance compensation circuit is used for increasing the output impedance of the differential amplification circuit, thereby increasing the gain,
wherein the impedance compensation circuit comprises a first transistor, a second transistor, and a first current source for providing a bias current to the first and second transistors,
the first end of the first transistor is connected with the first output end of the differential amplification circuit, the second end of the first transistor and the first end of the first current source are connected with a first node, the second end of the first current source is grounded,
a first terminal of the second transistor is connected to a second output terminal of the differential amplification circuit, a second terminal is connected to the first node,
the control end of the first transistor is connected with the first end of the second transistor, and the control end of the second transistor is connected with the first end of the first transistor.
2. The differential amplifier according to claim 1, wherein the first input terminal of the differential amplifier circuit is a non-inverting input terminal of the differential amplifier circuit, the second input terminal of the differential amplifier circuit is an inverting input terminal of the differential amplifier circuit, and the differential amplifier circuit is further provided with a power supply voltage terminal receiving a power supply voltage and a ground terminal.
3. The differential amplifier of claim 2, wherein the first and second transistors are both NMOS transistors.
4. The differential amplifier of claim 1, wherein the differential amplification circuit is a tandem amplification circuit.
5. The differential amplifier according to claim 2, wherein the differential amplifying circuit comprises: a third to a tenth transistor and a second current source, the third transistor being a tail current pipe of the differential amplifying circuit,
a fourth transistor and a fifth transistor form a differential input pair transistor of the differential amplification circuit, a control end of the fourth transistor is a first input end of the differential amplification circuit, a control end of the fifth transistor is a second input end of the differential amplification circuit, the fourth transistor is connected with the power supply voltage end through a sixth transistor, the fifth transistor is connected with the power supply voltage end through a seventh transistor, the sixth transistor and the seventh transistor are symmetrical load transistors, a second node where the fourth transistor and the sixth transistor are connected is a first output end of the differential amplification circuit, and a third node where the fifth transistor and the seventh transistor are connected is a second output end of the differential amplification circuit,
a first terminal of the eighth transistor is grounded through the ninth transistor, a second terminal is connected to the power supply voltage terminal,
control ends of the eighth transistor, the sixth transistor and the seventh transistor are all connected with a fourth node, the fourth node is a node where the eighth transistor and the ninth transistor are connected,
the second current source and the tenth transistor are connected in series between the power supply voltage terminal and a ground terminal, a node at which the second current source and the tenth transistor are connected is a fifth node,
and the control end of the third transistor, the control end of the ninth transistor and the control end of the tenth transistor are all connected with the fifth node.
6. The differential amplifier of claim 2, further comprising a substrate voltage regulating circuit for regulating a substrate voltage of a tail current tube of the differential amplifier, the tail current tube being connected between the power supply voltage terminal and a ground terminal, a control terminal of the tail current tube receiving a constant current control voltage for controlling the tail current tube to generate a constant current,
when the threshold voltage of the tail current tube needs to be increased, the substrate voltage regulating circuit controls the substrate voltage to be less than 0, so that the threshold voltage of the tail current tube is increased,
when the threshold voltage of the tail current tube needs to be reduced, the substrate voltage regulating circuit controls the substrate voltage to be larger than 0, so that the threshold voltage of the tail current tube is reduced.
7. The differential amplifier of claim 6, wherein the substrate voltage regulation circuit comprises: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a third current source, and an error amplifier,
the eleventh transistor and the third current source are connected in series between the power supply voltage terminal and a ground terminal, a sixth node where the eleventh transistor and the third current source are connected is connected to the first input terminal of the error amplifier,
the twelfth transistor and the eleventh transistor constitute a current mirror such that currents flowing through the eleventh transistor and the twelfth transistor are the same, the twelfth transistor is connected in series with the thirteenth transistor between the power supply voltage terminal and the ground terminal, a seventh node at which the twelfth transistor and the thirteenth transistor are connected is connected to the second input terminal of the error amplifier,
the signal output by the output end of the error amplifier is used for controlling the substrate voltage of the tail current tube,
a control terminal of the thirteenth transistor receives a reference voltage such that when the power supply voltage of the power supply voltage terminal is maintained at a constant voltage, voltages of the first input terminal and the second input terminal of the error amplifier are the same, a signal of an output of the error amplifier is 0, thereby making the substrate voltage 0,
when the environment of the application environment of the differential amplifier changes to increase the threshold voltage of the eleventh transistor and the thirteenth transistor, the threshold voltage of the tail current tube needs to be reduced, the voltage of the second input terminal of the error amplifier is increased to be smaller than the voltage of the first input terminal of the error amplifier, so that the output signal of the output terminal of the error amplifier controls the substrate voltage to be greater than 0, and the threshold voltage of the tail current tube is reduced,
when the environment of the application environment of the differential amplifier changes to reduce the threshold voltage of the eleventh transistor and the thirteenth transistor, the threshold voltage of the tail current tube needs to be increased, the power of the second input terminal of the error amplifier is greater than the voltage of the first input terminal, and the substrate voltage is controlled to be less than 0 by the signal output by the output terminal of the error amplifier, so that the threshold voltage of the tail current tube is increased.
8. The differential amplifier of claim 7, wherein the first input of the error amplifier is a non-inverting input of the error amplifier, the second input of the error amplifier is an inverting input of the error amplifier,
the output of the error amplifier is directly connected to the substrate to the constant current tube, so that the substrate voltage is the signal at the output of the error amplifier.
9. The differential amplifier of claim 8, wherein a first terminal of the eleventh transistor and a first terminal of the third current source are connected at the sixth node, the third current source is connected to the supply voltage terminal, a second terminal of the eleventh transistor is connected to ground,
a control end of the eleventh transistor and a control end of the twelfth transistor are both connected to the sixth node, a first end of the twelfth transistor and a first end of the thirteenth transistor are connected to the seventh node, a second end of the thirteenth transistor is connected to the power supply voltage terminal, and a second end of the twelfth transistor is grounded.
10. The differential amplifier of claim 9, wherein the substrates of the eleventh and twelfth transistors are connected to the output of the error amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021599297.5U CN213186054U (en) | 2020-08-04 | 2020-08-04 | Differential amplifier based on negative impedance compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021599297.5U CN213186054U (en) | 2020-08-04 | 2020-08-04 | Differential amplifier based on negative impedance compensation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213186054U true CN213186054U (en) | 2021-05-11 |
Family
ID=75798673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021599297.5U Active CN213186054U (en) | 2020-08-04 | 2020-08-04 | Differential amplifier based on negative impedance compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213186054U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452333A (en) * | 2021-09-02 | 2021-09-28 | 深圳市芯波微电子有限公司 | Differential amplifier and laser drive circuit |
-
2020
- 2020-08-04 CN CN202021599297.5U patent/CN213186054U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452333A (en) * | 2021-09-02 | 2021-09-28 | 深圳市芯波微电子有限公司 | Differential amplifier and laser drive circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101277095B (en) | Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier | |
| CN111464139B (en) | Common mode feedback circuit suitable for wide-swing full-differential operational amplifier | |
| CN110311636B (en) | High bandwidth Gao Baifu linear amplifier for envelope tracking power supply modulator | |
| CN109951161B (en) | Complementary digital variable gain amplifier | |
| US5578964A (en) | CMOS differential operational amplifier | |
| CN105141265A (en) | Gain increased operational transconductance amplifier | |
| JPH033406A (en) | Amplifier circuit | |
| CN213186054U (en) | Differential amplifier based on negative impedance compensation | |
| KR100662517B1 (en) | Operational trans-conductance amplifier using current sink | |
| CN204928758U (en) | Operation transconductance amplifier that gain promoted | |
| CN216016845U (en) | Buffer circuit and electronic equipment | |
| JP2002100936A (en) | Electronic circuit device having cascode transistor in output stage | |
| CN113489465B (en) | Amplifier circuit | |
| CN216721300U (en) | Stabilizing circuit of frequency compensation circuit with self-adaptive load change | |
| CN111697936B (en) | Low-power consumption complementary digital variable gain amplifier | |
| US5917376A (en) | Circuit and technique for compensating high gain amplifier without compensation capacitors | |
| CN213182459U (en) | Self-adaptive constant current source circuit, operational amplifier and comparator | |
| CN113612449A (en) | Operational amplifier circuit | |
| TWI799129B (en) | Voltage regulation integrated circuit | |
| CN219107415U (en) | Comparator | |
| US20150002222A1 (en) | Combined input stage for transconductance amplifier having gain linearity over increased input voltage range | |
| TWI750035B (en) | Low dropout regulator | |
| KR100801563B1 (en) | Variable gain amplifier | |
| US20220190788A1 (en) | Parallel input and dynamic cascaded operational transconductance amplifier achieving high precision with phase shifting | |
| TWI806543B (en) | Amplifier and method for controlling common mode voltage of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |