CN213043595U - Circuit for reducing load current change influence - Google Patents
Circuit for reducing load current change influence Download PDFInfo
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- CN213043595U CN213043595U CN202022410662.XU CN202022410662U CN213043595U CN 213043595 U CN213043595 U CN 213043595U CN 202022410662 U CN202022410662 U CN 202022410662U CN 213043595 U CN213043595 U CN 213043595U
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Abstract
The utility model relates to a circuit for reducing load current change influence, including the Sense wiring end, first transistor, second transistor and VO end; the Sense terminal is used for connecting a load; the base electrode of the first transistor is connected with the VO end, the collector electrode of the first transistor is connected with the Sense terminal and the base electrode of the second transistor, the emitter electrode of the first transistor is connected with the collector electrode of the second transistor, and the emitter electrode of the second transistor is connected with the VO end. The utility model discloses a set up first transistor and second transistor, can make when the magnitude of voltage that is greater than the VO end at the SENSE wiring end surpasss the transistor voltage, form low resistance path between SENSE wiring end and the VO end, can offset the change of SENSE voltage. The voltage jump caused by the current jump is reduced, thereby reducing the influence of the load current change.
Description
Technical Field
The utility model belongs to the technical field of integrated electronic circuit, concretely relates to circuit for reducing load current change influence.
Background
The current source is used to supply current to the load, and thus the current source has a wide range of applications. In the related art, many chips need output signals to be modulated and then fed back to the chips, and when the load power of the output signals changes, jitter is generated to affect a feedback circuit, so that the performance of the whole chip is affected.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention is directed to overcome the deficiencies in the prior art, and provides a circuit for reducing the influence of load current change to solve the problem that the current load current change affects the feedback circuit and thus affects the performance of the whole chip.
In order to realize the above purpose, the utility model adopts the following technical scheme: a circuit for reducing the effects of load current variations, comprising: a Sense terminal, a first transistor, a second transistor and a VO terminal;
the Sense terminal is used for connecting a load;
the base electrode of the first transistor is connected with the VO end, the collector electrode of the first transistor is connected with the Sense terminal and the base electrode of the second transistor, the emitter electrode of the first transistor is connected with the collector electrode of the second transistor, and the emitter electrode of the second transistor is connected with the VO end.
Further, the method also comprises the following steps:
an inductor connected to the Sense terminal.
Further, the first transistor and the second transistor both adopt:
and a triode.
Further, the first transistor is a PNP triode, and the second transistor is an NPN triode.
Further, the first transistor and the second transistor adopt:
a field effect transistor or a MOS transistor.
The utility model adopts the above technical scheme, the beneficial effect that can reach includes:
the circuit for reducing load current change influence provided by the embodiment of the application can enable a low-resistance path to be formed between the SENSE terminal and the VO end when the voltage value of the SENSE terminal greater than the VO end exceeds the voltage of the transistor by arranging the first transistor and the second transistor, and can offset the change of the SENSE voltage. The voltage jump caused by the current jump is reduced, thereby reducing the influence of the load current change.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a circuit for reducing the influence of load current variations.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
A specific circuit for reducing the effect of load current variations provided in the embodiments of the present application will be described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a circuit for reducing the influence of load current variation, including: a Sense terminal, a first transistor Q1, a second transistor Q2, and a VO terminal;
the Sense terminal is used for connecting a load;
the base of the first transistor Q1 is connected to the VO terminal, the collector of the first transistor Q1 is connected to the Sense terminal and the base of the second transistor Q2, the emitter of the first transistor Q1 is connected to the collector of the second transistor Q2, and the emitter of the second transistor Q2 is connected to the VO terminal.
Preferably, the circuit for reducing the influence of load current variation provided by the embodiment of the present application further includes:
an inductor (not shown) connected to the Sense terminal.
The working principle of the circuit for reducing the influence of the change of the load current is that when the current of a SENSE terminal jumps from large to small, the SENSE can be raised due to the effect of the inductance connected with the SENSE, after the circuit for reducing the influence of the change of the load current is added, when the difference value of the SENSE which is larger than the VO exceeds Vbe, the first transistor Q1 is firstly conducted, the VO voltage is raised instantly after the conduction so that the second transistor Q2 is conducted, and a low-resistance path is formed between the SENSE terminal and the VO terminal at the moment, so that the change of the voltage of the SENSE terminal can be counteracted. The voltage sudden change caused by the current sudden change is reduced, so that the influence of load current change is reduced, and the method and the device can be applied to high-precision circuits.
Preferably, the first transistor Q1 and the second transistor Q2 both adopt: and a triode.
Preferably, the first transistor Q1 is a PNP transistor, and the second transistor is an NPN transistor.
Preferably, the first transistor Q1 and the second transistor Q2 employ:
a field effect transistor or a MOS transistor.
It is to be understood that the first transistor and the second transistor may also adopt other elements, and the application is not limited herein.
To sum up, the circuit for reducing the influence of the load current variation provided by the utility model comprises a Sense terminal, a first transistor, a second transistor and a VO terminal; the Sense terminal is used for connecting a load; the base electrode of the first transistor is connected with the VO end, the collector electrode of the first transistor is connected with the Sense terminal and the base electrode of the second transistor, the emitter electrode of the first transistor is connected with the collector electrode of the second transistor, and the emitter electrode of the second transistor is connected with the VO end. The utility model discloses a set up first transistor and second transistor, can make when the magnitude of voltage that is greater than the VO end at the SENSE wiring end surpasss the transistor voltage, form low resistance path between SENSE wiring end and the VO end, can offset the change of SENSE voltage. The voltage jump caused by the current jump is reduced, thereby reducing the influence of the load current change.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A circuit for reducing the effects of load current variations, comprising: a Sense terminal, a first transistor, a second transistor and a VO terminal;
the Sense terminal is used for connecting a load;
the base electrode of the first transistor is connected with the VO end, the collector electrode of the first transistor is connected with the Sense terminal and the base electrode of the second transistor, the emitter electrode of the first transistor is connected with the collector electrode of the second transistor, and the emitter electrode of the second transistor is connected with the VO end.
2. The circuit for reducing the effects of load current variations according to claim 1, further comprising:
an inductor connected to the Sense terminal.
3. The circuit for reducing the effect of load current variation according to claim 1, wherein the first transistor and the second transistor each employ:
and a triode.
4. The circuit for reducing the effect of load current variation according to claim 3,
the first transistor adopts a PNP triode, and the second transistor adopts an NPN triode.
5. The circuit of claim 1, wherein the first transistor and the second transistor are configured to:
a field effect transistor or a MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022410662.XU CN213043595U (en) | 2020-10-27 | 2020-10-27 | Circuit for reducing load current change influence |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022410662.XU CN213043595U (en) | 2020-10-27 | 2020-10-27 | Circuit for reducing load current change influence |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213043595U true CN213043595U (en) | 2021-04-23 |
Family
ID=75536494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022410662.XU Active CN213043595U (en) | 2020-10-27 | 2020-10-27 | Circuit for reducing load current change influence |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213043595U (en) |
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2020
- 2020-10-27 CN CN202022410662.XU patent/CN213043595U/en active Active
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