CN212935880U

CN212935880U - Adder circuit and electronic device

Info

Publication number: CN212935880U
Application number: CN202021181776.5U
Authority: CN
Inventors: 赵嘉晨; 赵雁军
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-06-23
Filing date: 2020-06-23
Publication date: 2021-04-09
Anticipated expiration: 2030-06-23

Abstract

The application discloses an adder circuit and an electronic device. Wherein, this adder circuit includes: the circuit comprises a plurality of relays and a circuit board, wherein the relays are connected and at least used for forming a logic gate circuit of an adder; the circuit board is used for bearing the relays, and the relays can be repeatedly plugged and pulled out on the circuit board. The technical problem that a beginner cannot understand the working principle of the adder due to the fact that various gate circuits of the adder are formed by using diodes and triodes as experimental equipment at present is solved.

Description

Adder circuit and electronic device

Technical Field

The present application relates to the field of adders, and in particular, to an adder circuit and an electronic device.

Background

The inside of the adder mainly comprises various gate circuits, and the existing experimental devices of various gate circuits generally adopt the forms of simple bulbs, series connection and parallel connection of switches to show the results of various gate circuits, but a beginner is about what the internal real structure is or has a fog. In addition, some experimental devices form a gate circuit by using diodes and triodes, the transistors have many characteristics which are not easy to understand, and the transistors form the gate circuit by using the transistors which are not easy to understand.

Aiming at the problem that the working principle of the adder is difficult to understand by beginners due to the fact that various gate circuits of the adder are formed by adopting diodes and triodes as experimental equipment at present, an effective solution is not provided at present.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides an adder circuit and electronic equipment, so that the technical problem that a beginner cannot understand the working principle of an adder due to the fact that various gate circuits of the adder are formed by using diodes and triodes as experimental equipment at present is solved.

According to an aspect of an embodiment of the present application, there is provided an adder circuit including: the circuit comprises a plurality of relays and a circuit board, wherein the relays are connected and at least used for forming a logic gate circuit of an adder; the circuit board is used for bearing the relays, and the relays can be repeatedly plugged and pulled out on the circuit board.

Optionally, the logic gate circuit of the adder comprises: the circuit comprises two half adders and an OR gate circuit, wherein the half adders consist of the XOR gate circuit and the AND gate circuit; the exclusive-or gate circuit is composed of a nand gate circuit, an and gate circuit, and an or gate circuit.

Alternatively, the and circuit, the nand gate circuit, and the or gate circuit are each composed of two relays.

Optionally, the circuit board is a bread board.

Optionally, the relay is an unencapsulated relay.

Optionally, the adder circuit further comprises a relay circuit for connecting the logic gate circuit of the adder.

Optionally, the relay circuit consists of two relays.

Optionally, the adder circuit further comprises an indicator light for indicating an operating state of the adder.

According to another aspect of the embodiments of the present application, there is provided another adder circuit, including: a plurality of logic gate circuits, the plurality of logic gate circuits comprising: and the relays form a plurality of logic gate circuits according to different combination modes.

According to another aspect of the embodiments of the present application, there is also provided an electronic device including the above adder circuit.

In an embodiment of the present application, there is provided an adder circuit including: the circuit comprises a plurality of relays and a circuit board, wherein the relays are connected and at least used for forming a logic gate circuit of an adder; the circuit board for bear a plurality of relays, and a plurality of relays can repeatedly plug on the circuit board, constitute the various gate circuits of adder through the relay that adopts not encapsulation, thereby realized can very audio-visual understanding the on off state of relay, understand the state of each gate circuit, finally understand the technological effect of the principle of adder, and then solved because at present adopt diode, triode constitute the various gate circuits that the adder led to the fact as experimental device and lead to beginner to be difficult to understand the theory of operation technical problem of adder.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a block diagram of an adder circuit according to an embodiment of the present application;

FIG. 2 is a circuit diagram of a half-adder according to an embodiment of the present application;

FIG. 3 is a circuit diagram of an XOR gate circuit according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a NAND gate circuit, an AND gate circuit, an OR gate circuit, and a repeater circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a one-bit full adder according to an embodiment of the present application;

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a block diagram of an adder circuit according to an embodiment of the present application, and as shown in fig. 1, the adder circuit includes:

a plurality of relays 10, and a circuit board 12, wherein,

a plurality of relays 10 are connected, at least for forming a logic gate circuit of the adder;

a relay is an electric control device that generates a predetermined step change in a controlled amount in an electric output circuit when a change in an input amount (excitation amount) meets a predetermined requirement.

According to an alternative embodiment of the present application, the relay 10 is an unencapsulated relay.

It should be noted that the relay 10 provided in the embodiment of the present application uses an unpackaged relay, which enables a beginner to know the switching state of the relay very intuitively.

The circuit board 12 is used for carrying a plurality of relays 10, and the relays 10 can be repeatedly plugged and unplugged on the circuit board 12.

In an alternative embodiment of the present application, the circuit board 12 is a bread board. The bread board is specially designed and manufactured for the solderless experiment of the electronic circuit because of a plurality of small jacks on the board. Because various electronic components can be inserted or pulled out at will according to needs, the welding is saved, the assembly time of the circuit is saved, and the components can be reused, so the device is very suitable for the assembly, debugging and training of the electronic circuit.

Through the adder circuit, various gate circuits of the adder are formed by the aid of the unpackaged relays, so that the switching states of the relays can be known very intuitively, the states of the gate circuits can be known, and the technical effect of the principle of the adder can be finally known.

According to an alternative embodiment of the present application, the logic gate circuit of the full adder comprises: the circuit comprises two half adders and an OR gate circuit, wherein the half adders consist of the XOR gate circuit and the AND gate circuit; the exclusive-or gate circuit is composed of a nand gate circuit, an and gate circuit, and an or gate circuit.

The full adder is composed of two half adders and an OR gate circuit, and FIG. 2 is a circuit diagram of one half adder according to an embodiment of the present application.

The half adder is composed of an exclusive-or gate circuit and an and gate circuit, and fig. 3 is a circuit diagram of an exclusive-or gate circuit according to an embodiment of the present application.

The exclusive-or gate circuit is composed of a nand gate circuit, an and gate circuit, and an or gate circuit. Fig. 4 is a circuit diagram of a nand gate circuit, an and gate circuit, an or gate circuit, and a repeater circuit according to an embodiment of the present application.

According to an alternative embodiment of the application, the and circuit, the nand gate circuit, and the or gate circuit are each composed of two relays.

The AND gate circuit, the NAND gate circuit and the OR gate circuit provided in the embodiment of the present application are all composed of two relays mentioned above.

According to an alternative embodiment of the present application, the adder circuit further comprises a relay circuit for connecting the logic gate circuit of the adder.

Optionally, the relay circuit also consists of two relays as mentioned above.

FIG. 5 is a schematic diagram of a one-bit full adder according to an embodiment of the present application.

In another alternative embodiment of the present application, the adder circuit further includes an indicator light for indicating an operation state of the adder.

The indicator light adopts an LED lamp and is used for indicating the working state of the adder circuit, and during specific implementation, the LED lamp can be set to be in a lighting state to represent a number '1', and the LED and the like can be set to be in a extinguishing state to represent a number '0'.

An embodiment of the present application further provides another adder circuit, including: a plurality of logic gate circuits, the plurality of logic gate circuits comprising: and the relays form a plurality of logic gate circuits according to different combination modes.

It should be noted that the relay provided in the embodiment of the present application adopts an unpackaged relay, so that a beginner can very intuitively know the switching state of the relay, the state of each gate circuit, and finally the technical effect of the principle of the adder.

The embodiment of the application also provides an electronic device, which comprises the adder circuit. It should be noted that the adder circuit mentioned above may be integrated in an electronic device.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. An adder circuit, comprising: the circuit comprises a plurality of relays and a circuit board, wherein the relays are connected and at least used for forming a logic gate circuit of an adder;

the circuit board is used for bearing the relays, and the relays can be repeatedly plugged and unplugged on the circuit board.

2. The adder circuit of claim 1, wherein the logic gate circuit of the adder comprises: two half-adders and an or gate, wherein,

the half adder consists of an exclusive-OR gate circuit and an AND gate circuit;

the exclusive OR gate circuit consists of a NAND gate circuit, an AND gate circuit and an OR gate circuit.

3. The adder circuit of claim 2, wherein the and circuit, the nand gate circuit, and the or gate circuit are each comprised of two of the relays.

4. The adder circuit of claim 1, wherein the circuit board is a bread board.

5. The adder circuit of claim 1, wherein the relay is an unencapsulated relay.

6. The adder circuit of claim 1, further comprising a relay circuit for connecting a logic gate circuit of the adder.

7. The adder circuit according to claim 6, wherein the middle relay circuit is composed of two of the relays.

8. The adder circuit of claim 1, further comprising an indicator light for indicating an operational status of the adder.

9. An adder circuit, comprising: a plurality of logic gate circuits are arranged in the circuit,

the plurality of logic gate circuits includes: the plurality of relays form the plurality of logic gate circuits according to different combination modes.

10. An electronic device, comprising: an adder circuit as claimed in any one of claims 1 to 9.