CN207074435U - Adaptive JTAG chain on-off circuits - Google Patents
Adaptive JTAG chain on-off circuits Download PDFInfo
- Publication number
- CN207074435U CN207074435U CN201720949771.4U CN201720949771U CN207074435U CN 207074435 U CN207074435 U CN 207074435U CN 201720949771 U CN201720949771 U CN 201720949771U CN 207074435 U CN207074435 U CN 207074435U
- Authority
- CN
- China
- Prior art keywords
- jtag
- slot
- backboard
- emulator
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The utility model discloses a kind of adaptive JTAG chain on-off circuits, set n backboard slot to form link, and each slot is used for inserting subcard；A JTAG emulator interface is set to be used for inserting emulator, emulator is used for that the chip on subcard in link is emulated, debugged or programmed；The electronic equipment for connecting complicated more subcards is connected into succinct, efficient JTAG link using adaptive JTAG chains on-off circuit, makes system emulation, debugging more convenient by the utility model for the electronic equipment of more subcards；Its simple circuit, cost are cheap, easy to connect, considerably increase the flexibility of circuit design, meet the application of multiple fields.
Description
Technical field
A kind of adaptive JTAG chain on-off circuits are the utility model is related to, it is such as logical applied to more board electronic device fields
Believe equipment, electromedical equipment etc.；Especially after equipment installation, error detection, journey are carried out to the circuit in equipment, chip
Sequence is applied when updating, to remove the trouble of disassemblerassembler from.
Background technology
In electromedical equipment, system needs the cooperation of multiple boards in equipment to work, and now board is all integrated
On same backboard, if device fails or program need to update, it is necessary to subcard be dismantled one by one, detection or renewal respectively
Program, the workload of demolition, installation equipment are surprising；Therefore failure of chip is detected on the premise of subcard is not dismantled, program more
Newly solve the problems, such as into urgently connecing.
Utility model content
The utility model is to solve the deficiency present in above-mentioned prior art, there is provided a kind of adaptive JTAG chains switch
Circuit, in the case where being switched using only JTAG, the jtag circuit of all subcards in equipment is connected in series in a JTAG link,
So as to efficiently solve above mentioned problem.
The utility model adopts the following technical scheme that to solve technical problem：
The adaptive JTAG chains on-off circuit of the utility model is structurally characterized in that：
Set backboard slot 1 to backboard slot n to amount to n slot to be used for forming link, the n slot is used for intron
Card；One JTAG emulator interface is set, and the JTAG emulator interfaces are used for inserting emulator, and the emulator is for right
Chip in the link on subcard is emulated, debugged or programmed；
The data output end TDI of the JTAG emulator interfaces is connected with the data input pin TDI1 of backboard slot 1, will
The data output end TDO1 of backboard slot 1 is connected with the data input pin of adjacent next backboard slot, and connection in regular turn will be until will
Backboard slot n-1 data output end is connected with backboard slot n data input pin TDIn, by backboard slot n data output
End TDOn is connected with the input TDO of the JTAG emulator interfaces；
Set JTAG to switch 1 to JTAG switch n and amount to n JTAG on-off circuit, in the chip select terminal of each JTAG on-off circuits
OE accesses two divider resistances；When the chip select terminal OE does not have outer access voltage signal, divider resistance provides for chip select terminal OE
High level, the JTAG switches are made to be switched in conducting, data signal by the JTAG；JTAG is opened when chip select terminal OE is low level
Close in closing, block data-signal to pass through；
The Enable Pin PRES1-PRESn of each slot is switched to n chip select terminal with JTAG switches 1-JTAG correspondingly
OE is connected；The data output end TDO1-TDOn of each slot is switched to n data terminal with JTAG switches 1-JTAG correspondingly
A is connected；The data input pin TDI1-TDIn of each slot is switched to n data terminal B with JTAG switches 1-JTAG correspondingly
It is connected.
The design feature of the adaptive JTAG chains on-off circuit of the utility model is lain also in：Slot for forming link can expand
Exhibition.
Compared with the prior art, the utility model has the beneficial effect that：
1st, the utility model is in equipment all boards same by concatenating JTAG switches between TDI and TDO networks
In individual jtag circuit, exempt the trouble of demolition, installation equipment in debugging process.
2nd, the utility model is between TDI and TDO networks by concatenating JTAG switches, make slot can infinite expanding and subcard can
Arbitrarily plug, has no effect on JTAG link integrality.
Brief description of the drawings
Fig. 1 is the adaptive JTAG chains on-off circuit schematic diagram of the utility model.
Embodiment
Referring to Fig. 1, the structure type of adaptive JTAG chain on-off circuits is in the present embodiment：
Set backboard slot 1 to backboard slot n to amount to n slot to be used for forming link, n slot is used for inserting subcard；
One JTAG emulator interface is set, and JTAG emulator interfaces are used for inserting emulator, using emulator on subcard in link
Chip emulated, debugged or programmed；The micro-control unit MCU that emulator is used to substitute in goal systems emulates its operation,
The operation of emulator is identical with the target processor of reality, but its function increased, and can pass through desktop computer or other
Debugging interface observes the program and data in micro-control unit MCU, and controls micro-control unit MCU operation.
The data output end TDI of JTAG emulator interfaces is connected with the data input pin TDI1 of backboard slot 1, by backboard
The data output end TDO1 of slot 1 is connected with the data input pin of adjacent next backboard slot, and connection is until by backboard in regular turn
Slot n-1 data output end is connected with backboard slot n data input pin TDIn, by backboard slot n data output end
TDOn is connected with the input TDO of JTAG emulator interfaces.
Set JTAG to switch 1 to JTAG switch n and amount to n JTAG on-off circuit, in the chip select terminal of each JTAG on-off circuits
OE accesses divider resistance R1 and divider resistance R2, wherein, divider resistance R1 connects power supply, divider resistance R2 ground connection, two partial pressure electricity
It is connected at the series connection of resistance with the chip select terminal OE of JTAG on-off circuits, when being not inserted into son in the associated socket being connected with chip select terminal OE
During card, the voltage on slot is in vacant state, then the voltage on chip select terminal OE is high level；It is connected when with chip select terminal OE
Associated socket on insert subcard when, the voltage on slot is low level, then the voltage on chip select terminal OE is also low level.
When chip select terminal OE is high level, JTAG switches are switched in conducting, data signal by JTAG；JTAG when chip select terminal OE is low level
Switch blocks passing through for data-signal in closing.
The Enable Pin PRES1-PRESn of each slot is switched to n chip select terminal with JTAG switches 1-JTAG correspondingly
OE is connected；The data output end TDO1-TDOn of each slot is switched to n data terminal with JTAG switches 1-JTAG correspondingly
A is connected；The data input pin TDI1-TDIn of each slot is switched to n data terminal B with JTAG switches 1-JTAG correspondingly
It is connected.
It is expansible to be used to be formed the slot of link in the utility model, suitable for carrying out system to the electronic equipment of more subcards
Emulation and debugging.
As shown in figure 1, when inserting subcard on backboard slot 1, its Enable Pin PRES1 output low level signals, with its phase
The chip select terminal OE of JTAG switches 1 even be low level, the closing of JTAG switches 1, data signal by JTAG emulator interfaces data
Output end TDI is sent, and after the subcard on backboard slot 1, is output to subsequently by the data output end TDO1 of backboard slot 1
Backboard slot 2 data input pin TDI2；If do not have subcard on backboard slot 1, its Enable Pin PRES1 is hanging, and JTAG is opened
The chip select terminal OE for closing 1 is high level, and JTAG switches 1 turn on, the numeral sent by the data output end TDI of JTAG emulator interfaces
After signal is via JTAG switches 1, the data input pin TDI2 to backboard slot 2 is exported.
When on backboard slot n inserted with subcard, JTAG switches n is closed, the numeral letter of its data output end TDOn outputs
Number return to the data input pin TDO of JTAG emulator interfaces；When there is no subcard on backboard slot n, JTAG switch n conductings,
After the data signal that the data output end that upper level is inserted with the slot of subcard exports switchs n by JTAG, JTAG emulation is returned to
The data input pin TDO of device interface, completes the unimpeded of link.
One emulator Debugging interface is set, when needing to debug the subcard on some neck on link,
The neck of pre- debugging is chosen in emulator Debugging interface, now emulator is adjusted just for the subcard in the neck chosen
Examination, other necks for being inserted with subcard are only responsible for transparent transmission data signal, without debugging efforts.
Slot can infinite stages extension, and whether there is subcard insertion and do not interfere with the integrality of JTAG link, so far JATG circuits
Reach adaptation function.
Claims (2)
1. a kind of adaptive JTAG chain on-off circuits, it is characterized in that：
Set backboard slot 1 to backboard slot n to amount to n slot to be used for forming link, the n slot is used for inserting subcard；
One JTAG emulator interface is set, and the JTAG emulator interfaces are used for inserting emulator, and the emulator is for institute
The chip in link on subcard is stated to be emulated, debugged or programmed；
The data output end TDI of the JTAG emulator interfaces is connected with the data input pin TDI1 of backboard slot 1, by backboard
The data output end TDO1 of slot 1 is connected with the data input pin of adjacent next backboard slot, and connection is until by backboard in regular turn
Slot n-1 data output end is connected with backboard slot n data input pin TDIn, by backboard slot n data output end
TDOn is connected with the input TDO of the JTAG emulator interfaces；
Set JTAG to switch 1 to JTAG switch n and amount to n JTAG on-off circuit, connect in the chip select terminal OE of each JTAG on-off circuits
Enter divider resistance；When the chip select terminal OE does not have outer access voltage signal, divider resistance provides high level for chip select terminal OE, makes
The JTAG switches are switched in conducting, data signal by the JTAG；JTAG switches are in close when chip select terminal OE is low level,
Block passing through for data-signal；
The Enable Pin PRES1-PRESn of each slot is switched to n chip select terminal OE phases with JTAG switches 1-JTAG correspondingly
Even；The data output end TDO1-TDOn of each slot is switched to n data terminal A phases with JTAG switches 1-JTAG correspondingly
Even；The data input pin TDI1-TDIn of each slot is switched to n data terminal B phases with JTAG switches 1-JTAG correspondingly
Even.
2. adaptive JTAG chain on-off circuits according to claim 1, it is characterized in that can expand for the slot for forming link
Exhibition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720949771.4U CN207074435U (en) | 2017-08-01 | 2017-08-01 | Adaptive JTAG chain on-off circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720949771.4U CN207074435U (en) | 2017-08-01 | 2017-08-01 | Adaptive JTAG chain on-off circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207074435U true CN207074435U (en) | 2018-03-06 |
Family
ID=61523307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720949771.4U Active CN207074435U (en) | 2017-08-01 | 2017-08-01 | Adaptive JTAG chain on-off circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207074435U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021056401A1 (en) * | 2019-09-25 | 2021-04-01 | 苏州浪潮智能科技有限公司 | Jtag-based burning device |
-
2017
- 2017-08-01 CN CN201720949771.4U patent/CN207074435U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021056401A1 (en) * | 2019-09-25 | 2021-04-01 | 苏州浪潮智能科技有限公司 | Jtag-based burning device |
| US11874323B2 (en) | 2019-09-25 | 2024-01-16 | Inspur Suzhou Intelligent Technology Co., Ltd. | JTAG-based burning device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102998614B (en) | System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method | |
| CN104090855B (en) | The USB mode of USB interface and the compatibility method and device of MHL patterns | |
| CN103186441A (en) | Switching circuit | |
| CN103281226B (en) | A kind of MVB device address configuration system and method based on TCN | |
| CN105095037A (en) | Wire card, backboard of wire card and wire card test method | |
| CN206133546U (en) | Storage device's break -make testing arrangement and system | |
| CN207074435U (en) | Adaptive JTAG chain on-off circuits | |
| CN106462512B (en) | It is forward and reverse between a kind of contact USB device to be inserted into the scheme being mutually distinguishable | |
| CN105338150A (en) | Multi-card detection device and method for mobile terminal | |
| CN104535919A (en) | Chip debugging method and debugging circuit under normal operating mode | |
| CN111104279A (en) | SAS connector conduction detection system and method thereof | |
| CN202102275U (en) | IO port expansion circuit | |
| CN209148019U (en) | A kind of capacitance type sensor simulator | |
| CN203012704U (en) | System capable of achieving joint test action group (JTAG) debugging of signal digital signal processor (DSP) board or multiple DSP boards | |
| CN206962955U (en) | USB multiplexing control circuit | |
| CN102156425A (en) | Device for monitoring health status of welding spot of digital integrated circuit in real time | |
| CN205404705U (en) | Automatic testing arrangement of automatically controlled board of white appliances | |
| CN108674699A (en) | A kind of satellite equivalent system of the bipolar gating of time-sharing multiplex | |
| CN209043946U (en) | A kind of any attachment device of JTAG chain | |
| CN205545720U (en) | Signal connection and transmission device | |
| CN108431788A (en) | A kind of method of veneer, electronic equipment and gating | |
| CN209015145U (en) | A kind of information output apparatus | |
| CN201903876U (en) | Circuit board supporting automatic external test equipment | |
| US20040123193A1 (en) | Method and apparatus for enhanced parallel port JTAG interface | |
| CN202093391U (en) | Multifunctional digital signal input card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: SHENZHEN ANKE HIGH-TECH Co.,Ltd. Assignor: HEFEI FEITE COMMUNICATION TECHNOLOGY Co.,Ltd. Contract record no.: X2022980004488 Denomination of utility model: Adaptive JTAG chain switching circuit Granted publication date: 20180306 License type: Common License Record date: 20220420 |
|
| EE01 | Entry into force of recordation of patent licensing contract |