CN212850277U - Circuit for optimizing power supply current adjustment degree - Google Patents
Circuit for optimizing power supply current adjustment degree Download PDFInfo
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- CN212850277U CN212850277U CN202021482278.4U CN202021482278U CN212850277U CN 212850277 U CN212850277 U CN 212850277U CN 202021482278 U CN202021482278 U CN 202021482278U CN 212850277 U CN212850277 U CN 212850277U
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Abstract
The utility model provides a circuit for optimizing the power current adjustment degree, which comprises an input circuit, an output circuit, a voltage stabilizing circuit and a photoelectric sensing circuit; the voltage stabilizing circuit comprises a voltage stabilizer U2, a sampling resistor R5 and a resistor R2, and the output circuit comprises a coupler T1, a capacitor C1, a capacitor C2 and an inductor L1; the utility model adjusts the position of the inductor L1, one end of the inductor L1 is connected with the second end of the capacitor C1 and the second end of the sampling resistor R5, and the other end is connected with the second end of the capacitor C2 and the output ground Go; because of the voltage of the negative pressure that inductance L1 produced and sampling resistor R5 equals the voltage of stabiliser U2's REF end, because the voltage of stabiliser U2's REF end maintains unchangeably, sampling resistor R5's voltage must rise so, and resistance R2's voltage also follows the lifting, then output circuit's output voltage also raises to the produced line loss of output circuit when compensating current increases, the utility model discloses have good load adjustment degree.
Description
Technical Field
The utility model belongs to the technical field of commonality technique and specifically relates to a circuit of optimizing supply current adjustment degree.
Background
In the circuit of the prior art as shown in fig. 1, if the output current of the power supply is large and the load is far away from the output end, the voltage from the output voltage to the load end will lose a little due to the line loss, and if the load requires a good load regulation degree, some compensation is needed to ensure that the load regulation degree obtains a good result.
It is common practice to achieve better current regulation by adding a SENSE resistor to the feedback circuit, with the SENSE terminal and the output power bus connected together to the load terminal, which is a good solution, but has some disadvantages, such as the need to add two SNESE resistors and two output terminals to the circuit, and the need to add two SENSE compensation lines in use, which adds some complexity and cost, and also catastrophic consequences if the SENSE function is not used in use, but the SENSE terminal is inadvertently used as the output power bus.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides an optimize circuit of supply current adjustment degree.
The utility model discloses a following technical scheme realizes:
the utility model provides an optimize circuit of supply current adjustment degree, including input circuit, output circuit, voltage stabilizing circuit and photoelectric sensing circuit, input circuit with the output circuit coupling, photoelectric sensing circuit connects voltage stabilizing circuit connect with input circuit.
The voltage stabilizing circuit comprises a voltage stabilizer U2, a sampling resistor R5 and a resistor R2, wherein the output end of the resistor R2 is connected with the photoelectric sensing circuit, the first end of the sampling resistor R5 and the REF end of the voltage stabilizer U2, and the anode of the voltage stabilizer U2 is connected with an output ground Go.
The output circuit comprises a coupler T1, a diode D1, a capacitor C1, a capacitor C2 and an inductor L1, wherein the anode of the diode D1 is connected with the coupler T1, the cathode of the diode D1 is connected with the first end of the capacitor C1 and the first end of the capacitor C2, one end of the inductor L1 is connected with the second end of the capacitor C1 and the second end of the sampling resistor R5, and the other end of the inductor L1 is connected with the second end of the capacitor C2 and an output ground Go.
Further, the photoelectric sensing circuit comprises a resistor R4 and a capacitor C4, wherein the output end of the resistor R4 is connected in series with the input end of the capacitor C4.
Further, the photoelectric sensing circuit comprises a resistor R3 and a photoelectric pair tube U1, the emitting end of the photoelectric pair tube U1 is connected in parallel with the resistor R3, and the cathode of the voltage stabilizer U2 is connected with the input end of the resistor R4, the output end of the resistor R3 and the K pole of the emitting end of the photoelectric pair tube U1.
Further, the photoelectric sensing circuit comprises a resistor R1, one end of the resistor R1 is connected with the resistor R2, and the other end of the resistor R1 is connected with the A pole of the emitting end of the photoelectric pair tube U1 and the input end of the resistor R3.
Further, the input circuit comprises a pulse width modulator, a field effect transistor Q1, a capacitor C1 and an auxiliary power supply, wherein the pulse width modulator is connected in series with the auxiliary power supply, the field effect transistor Q1 is connected between the coupler T1 and the pulse width modulator, and the capacitor C1 is connected between an input voltage terminal VIN and an input ground GI.
The utility model has the advantages that: the circuit for optimizing the power supply current adjustment degree comprises an input circuit, an output circuit, a voltage stabilizing circuit and a photoelectric sensing circuit, wherein the input circuit is coupled with the output circuit, and the photoelectric sensing circuit is connected with the voltage stabilizing circuit and the input circuit; the voltage stabilizing circuit comprises a voltage stabilizer U2, a sampling resistor R5 and a resistor R2, and the output circuit comprises a coupler T1, a diode D1, a capacitor C1, a capacitor C2 and an inductor L1; the utility model discloses adjust the position of inductance L1, inductance L1 one end with electric capacity C1's second end, sampling resistor R5's second end is connected, inductance L1's the other end with electric capacity C2's second end and output ground Go are connected; because the negative voltage generated by the inductor L1 and the voltage of the sampling resistor R5 are equal to the voltage at the REF terminal of the regulator U2, and the voltage at the REF terminal of the regulator U2 needs to be kept constant all the time, the voltage of the sampling resistor R5 inevitably rises, the current flowing through the sampling resistor R5 inevitably increases, and since the current at the REF terminal of the regulator U2 is extremely small, most of the current flows from the resistor R2 through the sampling resistor R5, the voltage of the resistor R2 also rises, so that the output voltage also rises, and the line loss generated by the output circuit when the current increases is compensated, that is: output current is big more, inductance L1's voltage drop is big more, and the line loss of compensation is big more to optimize supply current adjustment degree, guarantee the utility model discloses good load adjustment degree has.
Drawings
FIG. 1 is a circuit diagram of the prior art;
fig. 2 is a circuit diagram of the present invention for optimizing the power current adjustment.
Detailed Description
For a more clear and complete description of the technical solution of the present invention, the following description is made with reference to the accompanying drawings.
Please refer to fig. 2, the utility model provides a circuit for optimizing power supply current adjustment degree, including input circuit 1, output circuit 2, voltage stabilizing circuit 3 and photoelectric sensing circuit 4, input circuit 1 with output circuit 2 coupling, photoelectric sensing circuit 4 connect voltage stabilizing circuit 3 connect with input circuit 1.
The voltage stabilizing circuit 3 comprises a voltage stabilizer U2, a sampling resistor R5 and a resistor R2, the output end of the resistor R2 is connected with the photoelectric sensing circuit 4, the first end of the sampling resistor R5 and the REF end of the voltage stabilizer U2, and the anode of the voltage stabilizer U2 is connected with an output ground Go.
In this embodiment, VIN is an input voltage terminal, GI is an input ground, Vout is an output voltage terminal, and Go is an output ground.
The output circuit 2 comprises a coupler T1, a diode D1, a capacitor C1, a capacitor C2 and an inductor L1, wherein the anode of the diode D1 is connected to the coupler T1, the cathode of the diode D1 is connected to the first end of the capacitor C1 and the first end of the capacitor C2, one end of the inductor L1 is connected to the second end of the capacitor C1 and the second end of the sampling resistor R5, and the other end of the inductor L1 is connected to the second end of the capacitor C2 and the output ground Go.
Because the negative voltage generated by the inductor L1 and the voltage of the sampling resistor R5 are equal to the voltage at the REF terminal of the regulator U2, and the voltage at the REF terminal of the regulator U2 needs to be kept constant all the time, the voltage of the sampling resistor R5 inevitably rises, the current flowing through the sampling resistor R5 inevitably increases, and since the current at the REF terminal of the regulator U2 is extremely small, most of the current flows from the resistor R2 through the sampling resistor R5, the voltage of the resistor R2 also rises, so that the output voltage also rises, and the line loss generated by the output circuit 2 when the current increases is compensated, that is: output current is big more, inductance L1's voltage drop is big more, and the line loss of compensation is big more to optimize supply current adjustment degree, guarantee the utility model discloses good load adjustment degree has.
Further, the photo-sensing circuit 4 comprises a resistor R4 and a capacitor C4, wherein an output end of the resistor R4 is connected in series with an input end of the capacitor C4.
Further, the photoelectric sensing circuit 4 includes a resistor R3 and a photoelectric pair tube U1, the emitting end of the photoelectric pair tube U1 is connected in parallel with the resistor R3, and the cathode of the voltage regulator U2 is connected to the input end of the resistor R4, the output end of the resistor R3 and the K pole of the emitting end of the photoelectric pair tube U1.
In the present embodiment, the resistor R4 is connected in series with the capacitor C4. The emitting end of the photoelectric pair tube U1 is connected in parallel with the resistor R3.
Further, the photoelectric sensing circuit 4 includes a resistor R1, one end of the resistor R1 is connected to the resistor R2, and the other end is connected to the a pole of the emitting end of the photoelectric pair U1 and the input end of the resistor R3. Further, the input circuit 1 includes a pulse width modulator, a fet Q1, a capacitor C1, and an auxiliary power supply, the pulse width modulator is connected in series with the auxiliary power supply, the fet Q1 is connected between the coupler T1 and the pulse width modulator, and the capacitor C1 is connected between the input voltage terminal VIN and the input ground GI.
In this embodiment, the emitting end of the photoelectric pair U1 is connected in parallel with the resistor R3, and the receiving end of the photoelectric pair U1 is connected to the pulse width modulator.
When the output circuit 2 has an output current, the negative voltage generated by the inductor L1 and the voltage of the sampling resistor R5 are equal to the voltage of the reference terminal REF of the regulator U2, that is, VR5+ VL1 is 2.5V, because VL1 is a negative voltage, and the REF terminal voltage of the regulator U2 needs to be maintained at 2.5V all the time, the voltage of the sampling resistor R5 must be increased, the current flowing through the sampling resistor R5 must be increased, because the current of the REF referenced by the regulator U2 is extremely small, most of the current flows through the sampling resistor R5 from the resistor R2, and therefore the voltage of the sampling resistor R2 is also increased, so that the output voltage is also increased, and thus the line loss generated by the output circuit 2 when the compensation current is increased, the larger the output current is, the larger the voltage drop of the inductor L1 is, the larger the compensated line loss is, and the good load adjustment degree is ensured.
The voltage Vo at the output terminal is determined by the following equation:
Vo＝(Vref-Io*R_L1)*(1+R2/R5)+Io*R_L1
after simplification, the following is obtained:
Vo＝Vref*(1+R2/R5)-Io*R_L1*R2/R5
since the current direction of the inductor L1 is from the output ground to the left, the current of the inductor L1 is negative, so that the compensation voltage Vo of the above formula is changed back to positive, and the voltage Vo at the output end is increased more than before, which meets the analysis result. The utility model discloses an advantage has been realized the compensation of current adjustment degree under the prerequisite that does not increase any components and parts and output terminal, but lacks certain flexibility, and compensation voltage is subject to inductance L1's parasitic resistance, will change the inductance that compensation coefficient need change different parasitic resistance, nevertheless can obtain reasonable compensation voltage through reasonable design, is a better compensation means on the whole. The inductor L1 of the present invention can be replaced by a current sampling resistor, so that the compensation of the current adjustment can be realized to increase some flexibility.
Of course, the present invention can also have other various embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative work, and all of them belong to the protection scope of the present invention.
Claims (5)
1. A circuit for optimizing the adjustment degree of power supply current is characterized by comprising an input circuit, an output circuit, a voltage stabilizing circuit and a photoelectric sensing circuit, wherein the input circuit is coupled with the output circuit;
the voltage stabilizing circuit comprises a voltage stabilizer U2, a sampling resistor R5 and a resistor R2, wherein the output end of the resistor R2 is connected with the photoelectric sensing circuit, the first end of the sampling resistor R5 and the REF end of the voltage stabilizer U2, and the anode of the voltage stabilizer U2 is connected with an output ground Go;
the output circuit comprises a coupler T1, a diode D1, a capacitor C1, a capacitor C2 and an inductor L1, wherein the anode of the diode D1 is connected with the coupler T1, the cathode of the diode D1 is connected with the first end of the capacitor C1 and the first end of the capacitor C2, one end of the inductor L1 is connected with the second end of the capacitor C1 and the second end of the sampling resistor R5, and the other end of the inductor L1 is connected with the second end of the capacitor C2 and an output ground Go.
2. The circuit for optimizing power supply current adjustment according to claim 1, wherein the photo-sensing circuit comprises a resistor R4 and a capacitor C4, and an output terminal of the resistor R4 is connected in series with an input terminal of the capacitor C4.
3. The circuit for optimizing the power supply current adjustment degree according to claim 2, wherein the photoelectric sensing circuit comprises a resistor R3 and a photoelectric pair tube U1, the emitting end of the photoelectric pair tube U1 is connected in parallel with the resistor R3, and the cathode of the voltage regulator U2 is connected with the input end of the resistor R4, the output end of the resistor R3 and the K pole of the emitting end of the photoelectric pair tube U1.
4. The circuit for optimizing power supply current adjustment according to claim 3, wherein the photo-sensing circuit comprises a resistor R1, one end of the resistor R1 is connected to the resistor R2, and the other end of the resistor R1 is connected to the A pole of the emitting end of the photo-pair U1 and the input end of the resistor R3.
5. The circuit for optimizing power supply current adjustment according to claim 4, wherein the input circuit comprises a pulse width modulator, a field effect transistor Q1, a capacitor C1 and an auxiliary power supply, the pulse width modulator is connected in series with the auxiliary power supply, the field effect transistor Q1 is connected between the coupler T1 and the pulse width modulator, and the capacitor C1 is connected between an input voltage terminal VIN and an input ground GI.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021304134X | 2020-07-03 | ||
| CN202021304134 | 2020-07-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212850277U true CN212850277U (en) | 2021-03-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021482278.4U Active CN212850277U (en) | 2020-07-03 | 2020-07-23 | Circuit for optimizing power supply current adjustment degree |
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| Country | Link |
|---|---|
| CN (1) | CN212850277U (en) |
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2020
- 2020-07-23 CN CN202021482278.4U patent/CN212850277U/en active Active
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