CN212809024U

CN212809024U - Low dropout regulator

Info

Publication number: CN212809024U
Application number: CN202021477030.9U
Authority: CN
Inventors: 陈俊龙
Original assignee: Xiamen Imsemi Technology Co ltd
Current assignee: Xiamen Imsemi Technology Co ltd
Priority date: 2020-07-23
Filing date: 2020-07-23
Publication date: 2021-03-26
Anticipated expiration: 2030-07-23

Abstract

The utility model discloses a low dropout linear regulator, which comprises a Vref output end of a reference circuit, a Vref1 input end of a quick starting circuit and a Vref3 input end of a foldback current limiting circuit, wherein the Vref output end of the reference circuit is respectively coupled with the Vref1 input end of the quick starting circuit and the Vref3 input end of the foldback current; the quick starting circuit is used for removing noise of the reference voltage and outputting a control signal, the Vref2 output end of the quick starting circuit is coupled with the Vref4 input end of the LDO main circuit, and the Ctrl output end of the control signal is coupled with the Ctrl input end of the foldback current limiting circuit; the foldback current limiting circuit samples output current and output voltage, and performs fixed current limiting and output current foldback when the output current exceeds a limit value; the LDO main circuit generates a stable output voltage, and its Vout output terminal supplies power to the next-stage load. The utility model discloses a set up quick start circuit, guarantee the normal start of circuit to current-limiting protection has improved the reliability of circuit.

Description

Low dropout regulator

Technical Field

The utility model belongs to the technical field of the integrated circuit technique and specifically relates to a low dropout regulator that reliability is high.

Background

Among them, Low Dropout regulators (LDO) are widely used in various high performance power systems and various electronic products because they can provide stable output voltage and have the advantages of Low noise, high power rejection ratio, and Low cost.

The output voltage of the low dropout regulator may be unstable due to abnormal operation of the load circuit. Especially, when the load circuit is overloaded or even short-circuited, the power management chip and the back-end load module are easily damaged by an excessive output current, so that a current-limiting protection circuit is usually required to be introduced, and the current-limiting protection circuit mainly adopts a fixed current-limiting mode or a foldback current-limiting mode. In the fixed current limiting mode, the system is limited within the maximum range of the rated current limiting value, the output voltage is reduced, once current limiting occurs, the low-dropout linear regulator still maintains high current and high power consumption, and a chip generates heat for a long time, so that the chip is possibly failed or even burnt out; the foldback current limiting mode is to enter a current limiting mode after the overload of the load is found, reduce the output voltage and the output current until the output current reaches a smaller limit value, so the foldback current limiting mode is mainly adopted at present. However, as shown in fig. 1, when the low dropout regulator starts to start, the foldback current limiting circuit may be triggered due to low voltage and low current, so that the circuit enters a "Latch-Up" state, and thus the chip may not operate normally, resulting in poor reliability. In addition, the circuit is mainly implemented by an RC filter to realize low noise performance, and if the circuit is disposed in a chip, a large chip area is required to be occupied.

SUMMERY OF THE UTILITY MODEL

The applicant provides a low dropout regulator with a reasonable structure aiming at the problem of poor reliability in the existing low dropout regulator, and a control signal is generated to control a foldback circuit through a low pass filter circuit which is started quickly, so that the circuit is prevented from entering a 'latch-up' state, the normal starting of the circuit is ensured, and the reliability is improved.

The utility model discloses the technical scheme who adopts as follows:

a low dropout linear regulator comprising:

the reference circuit is used for generating a reference voltage and a reference current, and the Vref output ends of the reference circuit are respectively coupled with the Vref1 input end of the quick start circuit and the Vref3 input end of the foldback current limiting circuit;

the fast starting circuit is used for removing noise of the reference voltage and outputting a control signal, the Vref2 output end of the fast starting circuit is coupled with the Vref4 input end of the LDO main circuit, the Ctrl output end of the control signal is coupled with the Ctrl input end of the foldback current limiting circuit, and when the Ctrl output end outputs a low level, the foldback current limiting circuit does not work;

the foldback current limiting circuit samples output current and output voltage, and performs fixed current limiting and output current foldback when the output current exceeds a limit value, wherein a VG input end of the foldback current limiting circuit is coupled with a VG output end of the LDO main body circuit, and a Vout input end of the foldback current limiting circuit is coupled with a Vout output end of the LDO main body circuit;

an LDO main body circuit that generates a stable output voltage, whose Vout output supplies a subordinate load.

Preferably, the fast start circuit includes a low pass filter circuit composed of a transistor M0 and a capacitor C0, and a switching circuit including a comparator Comp, a switch SW, a transistor M1, and a current source I0.

Further, the negative terminal of the comparator Comp of the fast start circuit is coupled to the input terminal Vref1, the source of the transistor M0, and the source of the transistor M1, respectively, the positive terminal of the comparator Comp is coupled to the drain of the transistor M0, the output terminal Vref2, and one terminal of the capacitor C0, the other terminal of the capacitor C0 is grounded, and the output terminal of the comparator Comp is coupled to the Ctrl output terminal and the control terminal of the switch SW; one end of the switch SW is coupled to the gate of the transistor M0, the drain and the gate of the transistor M1, respectively, and the other end of the switch SW is coupled to the current source I0 and then grounded.

Preferably, the foldback current limiting circuit includes a current limiting circuit and a foldback circuit, the current limiting circuit includes a first sampling transistor M312 and a maximum current determining circuit, and is configured to set a maximum output current value, sample an output current of the LDO main circuit 400 through a VG input terminal, and limit the output current at the maximum output current value when the output current exceeds the maximum output current; the foldback circuit 302 includes a second sampling transistor M322 and a threshold circuit, and samples the output voltage of the LDO main circuit through the Vout input terminal after the output current is limited, and folds back the output current when the output voltage of the Vout output terminal drops below a set threshold voltage.

Further, the positive terminal of the comparator Comp2 of the current limiting circuit is coupled to the input terminal of Vref3, the positive terminal is coupled to the drain of the transistor M313 and one terminal of the resistor R311, the output terminal of the comparator Comp2 is coupled to the gate of the transistor M311, the other terminal of the resistor R311 is coupled to one terminal of the current source I311 and then grounded, the transistor M313 and the transistor M314 form a pair of active current mirrors, the source of the transistor M313 is coupled to the drain of the transistor M312, the source of the transistor M312 is coupled to the source of the transistor M311, and the drain of the transistor M311 is coupled to the gate of the transistor M312 and the VG input terminal, respectively.

Further, a drain of the transistor M321, a gate of the transistor M322 of the foldback circuit are coupled to the VG input terminal, a source of the transistor M321 is coupled to a source of the transistor M322 and one end of the resistor R321, another end of the resistor R321 is coupled to a gate of the transistor M321, a drain and a gate of the transistor M324, a drain of the transistor M322 is coupled to a source of the transistor M323, a gate of the transistor M323, a source of the transistor M314, and a source of the transistor M324 are coupled to the Vout input terminal, a drain of the transistor M323 is coupled to a drain of the transistor M325, a gate of the transistor M325 is coupled to a drain of the transistor M326 and a gate of the transistor M324, a source of the transistor M325 is grounded through the resistor R322, a gate of the transistor M326 is coupled to the Ctrl input terminal, and.

Preferably, the LDO main circuit includes an error amplifier EA, a power tube M401, a voltage dividing resistor R401 and a voltage dividing resistor R402, a negative terminal of the error amplifier EA is coupled to the input terminal of Vref4, a positive terminal of the error amplifier EA is coupled between the voltage dividing resistor R401 and the voltage dividing resistor R402, the other terminal of the voltage dividing resistor R401 is coupled to the drain of the power tube M401 and the output terminal of Vout, and the other terminal of the voltage dividing resistor R402 is grounded; the output terminal of the error amplifier EA is coupled to the output terminal VG and the gate of the power transistor M401, and the source of the power transistor M401 is coupled to the dc voltage source.

The utility model has the advantages as follows:

the utility model discloses a set up the quick start circuit, when guaranteeing quick start, output control signal guarantees that the circuit of turning back is out of work when the initial power-on to avoid the voltage of Vout output end in the process of rising, the circuit enters "latch" state; the normal start of the circuit is ensured, the current-limiting protection is carried out, and the reliability of the circuit is improved.

The utility model discloses a set up low pass filter circuit among the quick start circuit, compare the voltage of Vref1 input with Vref2 output, treat that electric capacity C0 charges to when the voltage with Vref1 input is equal, comparator Comp exports the high level, the disconnection of control switch SW, switching transistor M0's operating condition, low pass filter circuit's cutoff frequency has effectively been reduced, effectively reduce the output voltage noise of Vref2 output, and then reduce the output voltage noise of Vout output; the chip area is ensured, and external elements are reduced.

Drawings

FIG. 1 is a prior art "latched" state waveform.

Fig. 2 is a block diagram of the present invention.

Fig. 3 is a circuit diagram of the fast start circuit of the present invention.

Fig. 4 is a circuit diagram of the foldback current limiting circuit of the present invention.

Fig. 5 is a circuit diagram of the LDO main circuit of the present invention.

In the figure: 100. a reference circuit; 200. a fast start circuit; 300. a foldback current limiting circuit; 400. LDO main part circuit.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

As shown in fig. 2 to fig. 5, the present invention provides a low dropout regulator, which includes a reference circuit 100, a fast start circuit 200, a foldback current limiting circuit 300 and a LDO main circuit 400, wherein, as shown in fig. 2, the reference circuit 100 is used to generate a reference voltage and a reference current, and the Vref output terminals of the reference circuit 100 are respectively coupled to the Vref1 input terminal of the fast start circuit 200 and the Vref3 input terminal of the foldback current limiting circuit 300; the fast start circuit 200 performs noise removal on the reference voltage and outputs a control signal, wherein the Vref2 output terminal is coupled to the Vref4 input terminal of the LDO main circuit 400, and the control signal Ctrl output terminal is coupled to the Ctrl input terminal of the foldback current-limiting circuit 300; the foldback current-limiting circuit 300 samples the output current and the output voltage, and performs fixed current limiting and output current foldback when the output current exceeds a limit value, wherein a VG input end of the foldback current-limiting circuit is coupled with a VG output end of the LDO main body circuit 400, and a Vout input end of the foldback current-limiting circuit is coupled with a Vout output end of the LDO main body circuit 400; the LDO body circuit 400 generates a stable output voltage with its Vout output supplying the next stage load.

The fast start circuit 200 includes a low pass filter circuit composed of a transistor M0 and a capacitor C0, and a switching circuit including a comparator Comp, a switch SW, a transistor M1, and a current source I0. As shown in fig. 3, the negative terminal of the comparator Comp is coupled to the input terminal Vref1, the source of the transistor M0 and the source of the transistor M1, the positive terminal of the comparator Comp is coupled to the drain of the transistor M0, the output terminal Vref2 and one terminal of the capacitor C0, the other terminal of the capacitor C0 is grounded, and the output terminal of the comparator Comp is coupled to the Ctrl output terminal and the control terminal of the switch SW; one end of the switch SW is coupled to the gate of the transistor M0, the drain and the gate of the transistor M1, respectively, and the other end of the switch SW is coupled to the current source I0 and then grounded. When the power supply starts to work, because the voltage at the input end of the Vref1 is greater than the voltage at the output end of the Vref2, the comparator Comp outputs a low level, that is, the Ctrl output end is a low level, the control switch SW is closed, the transistor M0 works in a low impedance state, and the capacitor C0 charges quickly; when the capacitor C0 is charged to be equal to the voltage at the input terminal of Vref1, the comparator Comp outputs a high level, i.e., the Ctrl output terminal becomes a high level, the control switch SW is turned off, the transistor M0 is switched to a high impedance state, so that the cut-off frequency of the low-pass filter circuit is reduced, the noise of the output voltage at the output terminal of Vref2 is effectively reduced, and the noise of the output voltage at the output terminal of Vout is further reduced.

The foldback current limiting circuit 300 comprises a current limiting circuit 301 and a foldback circuit 302, wherein the current limiting circuit 301 comprises a first sampling transistor M312 and a maximum current judging circuit, and is used for setting a maximum output current value, sampling the output current of the LDO main body circuit 400 through a VG input end, and limiting the output current at the maximum output current value when the output current exceeds the maximum output current; the foldback circuit 302 includes a second sampling transistor M322 and a threshold circuit, and when the output current is limited, the output voltage of the LDO main circuit 400 is sampled by the Vout input terminal, and when the output voltage of the Vout output terminal drops below the set threshold voltage, the foldback circuit 302 folds back the output current to maintain the output current at a smaller value. As shown in fig. 4, the positive terminal of the comparator Comp2 of the current limiting circuit 301 is coupled to the input terminal Vref3, the positive terminal is coupled to the drain of the transistor M313 and one end of the resistor R311, the output terminal of the comparator Comp2 is coupled to the gate of the transistor M311, the other end of the resistor R311 is coupled to one end of the current source I311 and then grounded, the transistor M313 and the transistor M314 form a pair of active current mirrors, the source of the transistor M313 is coupled to the drain of the transistor M312, the source of the transistor M312 is coupled to the source of the transistor M311, and the drain of the transistor M311 is coupled to the gate of the transistor M312 and the VG input terminal, respectively; the drain of the transistor M321, the gate of the transistor M322, and the VG input terminal of the foldback circuit 302 are coupled, the source of the transistor M321 is coupled to the source of the transistor M322 and one end of the resistor R321, the other end of the resistor R321 is coupled to the gate of the transistor M321, the drain of the transistor M324 and the gate, the drain of the transistor M322 is coupled to the source of the transistor M323, the gate of the transistor M323, the source of the transistor M314, and the source of the transistor M324 are coupled to the Vout input terminal, the drain of the transistor M323 is coupled to the drain of the transistor M325, the gate of the transistor M325 is coupled to the drain of the transistor M326 and the gate of the transistor M324, the source of the transistor M325 is grounded through the resistor R322, the gate of the transistor M326 is coupled to the Ctrl. The transistors M311, M322, M323, and M326 are control transistors.

As shown in fig. 5, the LDO main body circuit 400 includes an error amplifier EA, a power tube M401, a voltage dividing resistor R401, and a voltage dividing resistor R402. The negative end of the error amplifier EA is coupled with the input end of Vref4, the positive end of the error amplifier EA is coupled between a voltage dividing resistor R401 and a voltage dividing resistor R402, the other end of the voltage dividing resistor R401 is coupled with the drain of the power tube M401 and the Vout output end, and the other end of the voltage dividing resistor R402 is grounded; the output terminal of the error amplifier EA is coupled to the output terminal VG and the gate of the power transistor M401, and the source of the power transistor M401 is coupled to the dc voltage source. The LDO main body circuit 400 is in a negative feedback state, and the output voltage of the Vout output terminal is determined by the voltage value at the input terminal of Vref4, the voltage dividing resistor R401, and the voltage dividing resistor R402.

The working principle of the utility model is as follows:

1. when the power is initially powered on, a stable reference voltage is generated at the Vref output end of the reference circuit 100, and meanwhile, the power is supplied to the quick start circuit 200 and the foldback current-limiting circuit 300, at this time, the voltage at the Vref1 input end of the quick start circuit 200 is greater than the voltage at the Vref2 output end, the transistor M0 is in a low impedance state, the Ctrl output end is at a low level, the capacitor C0 of the low-pass filter circuit is charged, the voltage at the Vref4 input end of the LDO main circuit 400 is not stable yet, the transistor M326 is in a conduction state, the foldback circuit 302 is ensured not to work, and the circuit is prevented from; when the voltages at the Vref2 and Vref1 inputs are equal, the Ctrl output goes high and the foldback circuit 302 can operate normally.

2. When the voltage at the Vref4 input end of the LDO main circuit 400 is stable, the circuit works normally, when the output current of the LDO main circuit 400 is lower than the maximum output current value, the first sampling transistor M312 and the second sampling transistor M322 respectively mirror the power end M401 of the LDO main circuit 400, sample the output current, at this time, the voltage at the resistor R311 is smaller than the voltage at the Vref3 input end, the comparator Comp2 outputs a high level, the gate voltages of the transistor M311 and the transistor M321 are high levels, the transistor M311 and the transistor M321 are in a cut-off state, and the current limiting circuit 301 and the foldback circuit 302 do not work; the foldback current limiting circuit 300 does not affect the LDO main circuit 400, and the Vout output terminal of the LDO main circuit 400 provides a stable output voltage for the next stage load circuit.

3. When the output current of the LDO main circuit 400 exceeds the maximum output current value, the voltage at the resistor R311 is greater than the voltage at the input terminal Vref3 at this time, the comparator Comp2 outputs a low level, the gate voltage of the transistor M311 is pulled down, the transistor M311 is turned on, the voltage at the VG input terminal is pulled up, the gate potential of the power transistor M401 of the LDO main circuit 400 is pulled up, the output current is locked at the set maximum output current value within a variation range of the load resistor, and the output voltage at the Vout output terminal is linearly decreased.

4. When the voltage of the output end of the Vout is reduced to a set threshold value, the voltage of the input end of the Vout is reduced, so that the transistor M325 and the transistor M324 are conducted, the voltage of the grid end of the transistor M321 is reduced, the transistor M321 is conducted, the foldback circuit 302 is triggered to work, the voltage of the VG end is further pulled up, and then the current of the output end is continuously returned to a low current state, so that the current-limiting protection is realized.

The above description is illustrative of the present invention and is not intended to limit the present invention, and the present invention may be modified in any manner without departing from the spirit of the present invention.

Claims

1. A low dropout linear regulator, comprising: the method comprises the following steps:

2. The low dropout regulator of claim 1, wherein: the fast start circuit comprises a low pass filter circuit consisting of a transistor M0 and a capacitor C0, and a switching circuit comprising a comparator Comp, a switch SW, a transistor M1, and a current source I0.

3. The low dropout regulator of claim 2, wherein: the negative terminal of the comparator Comp of the fast start circuit is respectively coupled to the input terminal of Vref1, the source of the transistor M0 and the source of the transistor M1, the positive terminal of the comparator Comp is respectively coupled to the drain of the transistor M0, the output terminal of Vref2 and one terminal of the capacitor C0, the other terminal of the capacitor C0 is grounded, and the output terminal of the comparator Comp is coupled to the Ctrl output terminal and the control terminal of the switch SW; one end of the switch SW is coupled to the gate of the transistor M0, the drain and the gate of the transistor M1, respectively, and the other end of the switch SW is coupled to the current source I0 and then grounded.

4. The low dropout regulator of claim 1, wherein: the foldback current limiting circuit comprises a current limiting circuit and a foldback circuit, wherein the current limiting circuit comprises a first sampling transistor M312 and a maximum current judging circuit and is used for setting a maximum output current value, sampling the output current of the LDO main body circuit through a VG input end, and limiting the output current at the maximum output current value when the output current exceeds the maximum output current; the foldback circuit comprises a second sampling transistor M322 and a threshold circuit, when the output current is limited, the output voltage of the LDO main circuit is sampled through the Vout input end, and when the output voltage of the Vout output end is reduced to be lower than the set threshold voltage, the foldback circuit folds back the output current.

5. The low dropout regulator of claim 4, wherein: the positive terminal of the comparator Comp2 of the current limiting circuit is coupled to the input terminal Vref3, the positive terminal is coupled to the drain of the transistor M313 and one end of the resistor R311, the output terminal of the comparator Comp2 is coupled to the gate of the transistor M311, the other end of the resistor R311 is coupled to one end of the current source I311 and then grounded, the transistor M313 and the transistor M314 form a pair of active current mirrors, the source of the transistor M313 is coupled to the drain of the transistor M312, the source of the transistor M312 is coupled to the source of the transistor M311, and the drain of the transistor M311 is coupled to the gate of the transistor M312 and the VG input terminal, respectively.

6. The low dropout regulator of claim 4, wherein: the drain of the transistor M321, the gate of the transistor M322, and the VG input terminal of the foldback circuit are coupled, the source of the transistor M321 is coupled to the source of the transistor M322 and one end of the resistor R321, the other end of the resistor R321 is coupled to the gate of the transistor M321, the drain of the transistor M324 and the gate, the drain of the transistor M322 is coupled to the source of the transistor M323, the gate of the transistor M323, the source of the transistor M314, and the source of the transistor M324 are coupled to the Vout input terminal, the drain of the transistor M323 is coupled to the drain of the transistor M325, the gate of the transistor M325 is coupled to the drain of the transistor M326 and the gate of the transistor M324, the source of the transistor M325 is grounded through the resistor R322, the gate of the transistor M326 is coupled to the Ctrl.

7. The low dropout regulator of claim 1, wherein: the LDO main circuit comprises an error amplifier EA, a power tube M401, a voltage dividing resistor R401 and a voltage dividing resistor R402, wherein the negative end of the error amplifier EA is coupled with the input end of Vref4, the positive end of the error amplifier EA is coupled between the voltage dividing resistor R401 and the voltage dividing resistor R402, the other end of the voltage dividing resistor R401 is coupled with the drain of the power tube M401 and the Vout output end, and the other end of the voltage dividing resistor R402 is grounded; the output terminal of the error amplifier EA is coupled to the output terminal VG and the gate of the power transistor M401, and the source of the power transistor M401 is coupled to the dc voltage source.