CN212750861U - Packaging part structure for semiconductor packaging substrate - Google Patents
Packaging part structure for semiconductor packaging substrate Download PDFInfo
- Publication number
- CN212750861U CN212750861U CN202021926215.3U CN202021926215U CN212750861U CN 212750861 U CN212750861 U CN 212750861U CN 202021926215 U CN202021926215 U CN 202021926215U CN 212750861 U CN212750861 U CN 212750861U
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- China
- Prior art keywords
- packaging
- encapsulation
- top cover
- fixedly connected
- semiconductor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 238000005538 encapsulation Methods 0.000 claims abstract description 23
- 210000004907 gland Anatomy 0.000 claims description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229920003023 plastic Polymers 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 241000218202 Coptis Species 0.000 claims description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000000084 colloidal system Substances 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 238000012423 maintenance Methods 0.000 abstract description 10
- 238000005452 bending Methods 0.000 abstract description 4
- 241001391944 Commicarpus scandens Species 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 6
- 238000001125 extrusion Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- -1 gold tin copper aluminum Chemical compound 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Landscapes
- Packaging Frangible Articles (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The utility model relates to a semiconductor package technical field just discloses a semiconductor package is packaging part structure for base plate, including the encapsulation base, encapsulation base top fixedly connected with encapsulation top cap, encapsulation base top fixed mounting has the wafer tray that is located the encapsulation top cap, wafer tray top fixed mounting has the semiconductor wafer that is located the encapsulation top cap, the equal fixed mounting in semiconductor wafer top left and right sides has the gasket that is connected and is located the encapsulation top cap with the semiconductor wafer electricity, the equal fixedly connected with of encapsulation base top left and right sides is located the interior pin of encapsulation top cap, fixedly connected with wire between interior pin and the gasket. The packaging part structure for the semiconductor packaging substrate solves the problems that pins of the packaging part structure for the existing semiconductor packaging substrate are easy to break and damage at bending positions, so that the whole chip cannot be used, a new chip needs to be replaced, and the maintenance cost is increased.
Description
Technical Field
The utility model relates to a semiconductor package technical field specifically is a semiconductor package is packaging part structure for base plate.
Background
The packaging substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip so as to realize multi-pin, reduce the volume of a packaged product, improve the electric performance and the heat dissipation, and achieve the purpose of ultrahigh density or multi-chip modularization, the semiconductor packaging refers to the process of processing a wafer passing through the test according to the product model and the function requirement to obtain an independent chip, and the packaging process is as follows: the wafer from the previous process of the wafer is cut into small chips after scribing process, then the cut chips are pasted on the corresponding small island of the substrate (lead frame) frame by glue, and then the bonding pads of the chips are connected to the corresponding pins of the substrate by utilizing superfine metal (gold tin copper aluminum) wires or conductive resin to form the required circuit; the individual chips are then encapsulated and protected by a plastic housing.
The pins of the conventional packaging part structure for the semiconductor packaging substrate are easy to break and damage at the bent part, so that the whole chip cannot be used, a new chip needs to be replaced, and the maintenance cost is increased.
SUMMERY OF THE UTILITY MODEL
Technical problem to be solved
The utility model provides a not enough to prior art, the utility model provides a packaging part structure for semiconductor package base plate possesses the advantage that reduces the maintenance cost, and the pin of having solved the packaging part structure for present semiconductor package base plate is easy in the fracture damage of the department of bending, leads to whole chip unable to use, needs the chip of renewal, has increased the problem of maintenance cost.
(II) technical scheme
For the purpose of realizing above-mentioned reduction maintenance cost, the utility model provides a following technical scheme: a packaging part structure for a semiconductor packaging substrate comprises a packaging base, wherein a packaging top cover is fixedly connected to the top of the packaging base, a wafer tray positioned in the packaging top cover is fixedly installed at the top of the packaging base, a semiconductor wafer positioned in the packaging top cover is fixedly installed at the top of the wafer tray, gaskets which are electrically connected with the semiconductor wafer and positioned in the packaging top cover are fixedly installed on the left side and the right side of the top of the semiconductor wafer, inner pins positioned in the packaging top cover are fixedly connected to the left side and the right side of the top of the packaging base, conducting wires are fixedly connected between the inner pins and the gaskets, outer pins penetrating through the packaging top cover and extending into the packaging top cover are inserted into the left side and the right side of the packaging top cover, a gland is movably connected to the top of the packaging top cover, clamping grooves are formed in the tops of the outer pins, and, the utility model discloses a semiconductor wafer packaging device, including encapsulation top cap, gland bottom fixedly connected with peg graft to the slot, the slot that quantity is two is all seted up to encapsulation top cap top left and right sides, the slot is kept away from one side bottom of semiconductor wafer and is seted up the spacing groove that is located the encapsulation top cap, gland bottom fixedly connected with pegs graft to the inserted bar in the slot, the fixture block of one side fixedly connected with and spacing groove looks joint that semiconductor wafer was kept away from to the inserted bar.
Preferably, the package base and the package top cover are made of resin which is integrally formed, and the semiconductor wafer is fixedly connected with the wafer tray through silver colloid.
Preferably, the wire is the gold thread, the equal fixedly connected with gold cladding material of inner pin and outer pin outer wall, set up the mounting groove with outer pin looks adaptation in the encapsulation top cap.
Preferably, the height of the mounting groove is equal to the sum of the heights of the inner pin and the outer pin, and the inner pin penetrates through the package top cover and extends into the mounting groove.
Preferably, when the gland is contacted with the encapsulation top cover, the distance between the bottom wall of the clamping groove and the encapsulation base is equal to the distance between the limiting compression rod and the encapsulation base.
Preferably, the inserted bar and the clamping block are made of plastics, the length of the slot is larger than the distance between the clamping block and the separated surface of the inserted bar, and ejection holes communicated with adjacent limiting grooves are formed in the left side and the right side of the gland.
(III) advantageous effects
Compared with the prior art, the utility model provides a semiconductor package is packaging part structure for base plate possesses following beneficial effect:
this packaging part structure for semiconductor package substrate, through setting up interior pin, outer pin, gland and spacing depression bar, make outer pin be connected with interior pin under the extrusion of gland and spacing depression bar, after fracture damage appears in outer pin, only need insert the thimble from ejecting hole and promote the fixture block and keep away from the spacing groove, alright with take out the gland from the top, make spacing depression bar not carry on spacingly to outer pin, then alright change with the outer pin that takes out the correspondence, thereby reached the purpose that reduces the maintenance cost, thereby effectual pin of having solved the packaging part structure that present semiconductor package substrate used is bending the fracture damage easily, lead to whole chip unable to use, need more renewed chip, the problem of maintenance cost has been increased.
Drawings
FIG. 1 is a schematic structural view of the present invention;
fig. 2 is a partially enlarged schematic view of a portion a shown in fig. 1 according to the present invention.
In the figure: the packaging structure comprises a packaging base 1, a packaging top cover 2, a wafer tray 3, a semiconductor wafer 4, a gasket 5, an inner pin 6, a lead 7, an outer pin 8, a gland 9, a clamping groove 10, a limiting compression bar 11, a slot 12, a limiting groove 13, an inserted bar 14 and a clamping block 15.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-2, a package structure for a semiconductor package substrate comprises a package base 1, a package top cover 2 fixedly connected to the top of the package base 1, the package base 1 and the package top cover 2 are made of an integrally formed resin, a chip tray 3 disposed in the package top cover 2 is fixedly mounted on the top of the package base 1, a semiconductor chip 4 disposed in the package top cover 2 is fixedly mounted on the top of the chip tray 3, the semiconductor chip 4 is fixedly connected to the chip tray 3 through a silver adhesive, pads 5 electrically connected to the semiconductor chip 4 and disposed in the package top cover 2 are fixedly mounted on the left and right sides of the top of the semiconductor chip 4, inner leads 6 disposed in the package top cover 2 are fixedly connected to the left and right sides of the top of the package base 1, conductive wires 7 are fixedly connected between the inner leads 6 and the pads 5, the conductive wires 7 are gold wires, outer leads 8 penetrating through the package top cover 2 and extending into the package top cover 2 are inserted into the left, the outer walls of the inner pin 6 and the outer pin 8 are fixedly connected with gold coatings, a mounting groove matched with the outer pin 8 is formed in the packaging top cover 2, the height of the mounting groove is equal to the sum of the heights of the inner pin 6 and the outer pin 8, the inner pin 6 penetrates through the packaging top cover 2 and extends into the mounting groove, the top of the packaging top cover 2 is movably connected with a gland 9, the top of the outer pin 8 is provided with a clamping groove 10, the bottom of the gland 9 is fixedly connected with a limiting pressure rod 11 which penetrates through the packaging top cover 2 and is inserted into the clamping groove 10, the distance between the bottom wall of the clamping groove 10 and the packaging base 1 when the gland 9 is contacted with the packaging top cover 2 is equal to the distance between the limiting pressure rod 11 and the packaging base 1, the left side and the right side of the top of the packaging top cover 2 are respectively provided with two slots 12, the bottom of one side of each slot 12, which, one side of the inserted rod 14, which is far away from the semiconductor chip 4, is fixedly connected with a clamping block 15 clamped with the limiting groove 13, the inserted rod 14 and the clamping block 15 are made of plastics, the length of the slot 12 is greater than the distance between the clamping block 15 and the separated surface of the inserted rod 14, and the left side and the right side of the gland 9 are provided with ejection holes communicated with the adjacent limiting grooves 13.
When using, through setting up inner pin 6, outer pin 8, gland 9 and spacing depression bar 11 for outer pin 8 is connected with inner pin 6 under gland 9 and spacing depression bar 11's extrusion, after outer pin 8 fracture damage appears, only need insert thimble from ejecting hole and promote fixture block 15 and keep away from spacing groove 13, alright take out gland 9 with the top, make spacing depression bar 11 not spacing to outer pin 8, then alright change with taking out corresponding outer pin 8, thereby reached the purpose that reduces the maintenance cost.
In summary, the package structure for the semiconductor package substrate is provided with the inner pin 6, the outer pin 8, the gland 9 and the limiting pressure rod 11, so that the outer pin 8 is connected with the inner pin 6 under the extrusion of the gland 9 and the limiting pressure rod 11, when the outer pin 8 is broken and damaged, the gland 9 can be taken out from the upper part only by inserting the thimble from the ejection hole to push the fixture block 15 to be away from the limiting groove 13, so that the limiting pressure rod 11 is not limiting for the outer pin 8, and then the corresponding outer pin 8 can be taken out for replacement, thereby achieving the purpose of reducing the maintenance cost, and effectively solving the problems that the pins of the package structure for the conventional semiconductor package substrate are easily broken and damaged at the bending part, the whole chip cannot be used, a new chip needs to be replaced, and the maintenance cost is increased.
It is to be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A package structure for a semiconductor package substrate includes a package base (1), characterized in that: the packaging structure is characterized in that a packaging top cover (2) is fixedly connected to the top of the packaging base (1), a wafer tray (3) positioned in the packaging top cover (2) is fixedly installed at the top of the packaging base (1), a semiconductor wafer (4) positioned in the packaging top cover (2) is fixedly installed at the top of the wafer tray (3), gaskets (5) which are electrically connected with the semiconductor wafer (4) and positioned in the packaging top cover (2) are fixedly installed at the left side and the right side of the top of the semiconductor wafer (4), inner pins (6) positioned in the packaging top cover (2) are fixedly connected to the left side and the right side of the top of the packaging base (1), wires (7) are fixedly connected between the inner pins (6) and the gaskets (5), outer pins (8) which penetrate through the packaging top cover (2) and extend into the packaging top cover (2) are inserted into the left side and the right side, encapsulation top cap (2) top swing joint has gland (9), draw-in groove (10) have been seted up at outer pin (8) top, gland (9) bottom fixedly connected with runs through encapsulation top cap (2) and inserts spacing depression bar (11) that connect to in draw-in groove (10), quantity is slot (12) of two all seted up to encapsulation top cap (2) top left and right sides, spacing groove (13) that are located encapsulation top cap (2) are seted up to one side bottom that semiconductor wafer (4) were kept away from in slot (12), gland (9) bottom fixedly connected with inserts inserted bar (14) that connect to in slot (12), fixture block (15) of one side fixedly connected with and spacing groove (13) looks joint that semiconductor wafer (4) were kept away from in inserted bar (14).
2. The package structure for a semiconductor package substrate according to claim 1, wherein: the packaging base (1) and the packaging top cover (2) are both integrally formed resin, and the semiconductor wafer (4) is fixedly connected with the wafer tray (3) through silver colloid.
3. The package structure for a semiconductor package substrate according to claim 1, wherein: the lead (7) is a gold thread, the outer walls of the inner pin (6) and the outer pin (8) are fixedly connected with gold coatings, and a mounting groove matched with the outer pin (8) is formed in the packaging top cover (2).
4. The package structure for a semiconductor package substrate according to claim 3, wherein: the height of the mounting groove is equal to the sum of the heights of the inner pin (6) and the outer pin (8), and the inner pin (6) penetrates through the packaging top cover (2) and extends into the mounting groove.
5. The package structure for a semiconductor package substrate according to claim 1, wherein: when the gland (9) is contacted with the encapsulation top cover (2), the distance between the bottom wall of the clamping groove (10) and the encapsulation base (1) is equal to the distance between the limiting compression bar (11) and the encapsulation base (1).
6. The package structure for a semiconductor package substrate according to claim 1, wherein: the plug rod (14) and the clamping block (15) are made of plastics, the length of the slot (12) is larger than the distance between the clamping block (15) and the plug rod (14) and the separation surface, and ejection holes communicated with the adjacent limiting grooves (13) are formed in the left side and the right side of the gland (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021926215.3U CN212750861U (en) | 2020-09-07 | 2020-09-07 | Packaging part structure for semiconductor packaging substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021926215.3U CN212750861U (en) | 2020-09-07 | 2020-09-07 | Packaging part structure for semiconductor packaging substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212750861U true CN212750861U (en) | 2021-03-19 |
Family
ID=75002503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021926215.3U Expired - Fee Related CN212750861U (en) | 2020-09-07 | 2020-09-07 | Packaging part structure for semiconductor packaging substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212750861U (en) |
-
2020
- 2020-09-07 CN CN202021926215.3U patent/CN212750861U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210319 |