CN117352477A - Lead frame and packaging method and structure of semiconductor element thereof - Google Patents
Lead frame and packaging method and structure of semiconductor element thereof Download PDFInfo
- Publication number
- CN117352477A CN117352477A CN202210739106.8A CN202210739106A CN117352477A CN 117352477 A CN117352477 A CN 117352477A CN 202210739106 A CN202210739106 A CN 202210739106A CN 117352477 A CN117352477 A CN 117352477A
- Authority
- CN
- China
- Prior art keywords
- chip
- cover plate
- unit
- semiconductor
- seat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000005452 bending Methods 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims description 36
- 239000010410 layer Substances 0.000 claims description 16
- 239000011265 semifinished product Substances 0.000 claims description 12
- 230000000712 assembly Effects 0.000 claims description 6
- 238000000429 assembly Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 2
- 239000012945 sealing adhesive Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A lead frame is suitable for packaging a semiconductor chip with at least one connecting pad, and comprises a chip setting unit, a cover plate unit and a connecting unit for connecting the chip setting unit and the cover plate unit. The chip setting unit comprises a chip seat for setting the semiconductor chip, and the cover plate unit comprises a cover plate and at least one guide port corresponding to the at least one connecting pad. When the lead frame is used for packaging the semiconductor element, the semiconductor chip is arranged on the chip seat or the at least one guide part, and the guide port and the semiconductor chip are driven to be electrically connected through bending the connecting unit, so that the wire bonding process in the traditional semiconductor element packaging is not required, the wire bonding collapse is avoided, and the yield of products is further improved. In addition, the invention also provides a packaging method and a packaging structure of the semiconductor element.
Description
Technical Field
The present invention relates to a leadframe and a method and a structure for packaging a semiconductor device, and more particularly, to a leadframe with no leads in a square plane and a method and a structure for packaging a semiconductor device.
Background
The present disclosure relates to a Quad Flat No-Lead (QFN) package, and more particularly to a conventional chip package structure, wherein a semiconductor device is disposed on a leadframe formed in a sheet shape, and then the semiconductor device can be electrically connected to the outside through a plurality of Wire pairs by Wire bonding (Wire bonding), and then a package body is formed by packaging the leadframe and the semiconductor device with a packaging adhesive, such that the bottom surface of the leadframe is exposed, and the Wire extends out of the package body, thereby eliminating a plurality of pins for external electrical connection, which are required to be formed by the conventional leadframe by extending from the side edge. Compared with the traditional chip packaging structure, the QFN packaging structure has lighter volume and low production cost.
However, in the process of packaging with the packaging adhesive, the wires are easy to collapse due to insufficient mechanical strength, so that the whole chip packaging structure loses electrical property, the yield of the whole process is reduced, and the heat dissipation effect on the high-power device is poor.
Disclosure of Invention
The invention aims to provide a lead frame which can avoid the occurrence of the collapse of a lead in the packaging process of a semiconductor element and enhance the efficiency of the packaging structure in heat dissipation.
The invention relates to a lead frame, which is suitable for packaging semiconductor chips, and the semiconductor chips are provided with at least one connecting pad for connecting to external electricity, the lead frame comprises a plurality of frame bars staggered in a crisscross way and a plurality of lead frame components defined by any two adjacent frame bars staggered in a crisscross way, and each lead frame component comprises: the chip setting unit, the apron unit and the connection unit.
The chip setting unit comprises a chip seat which is in a flat plate shape and is used for setting the semiconductor chip.
The cover plate unit and the chip setting unit are positioned on the same horizontal plane and comprise a cover plate and at least one guide port for electrically connecting with the at least one connecting pad.
The connecting unit is provided with a first connecting piece for connecting the cover plate and the chip seat, and at least one second connecting piece for connecting the at least one guide port and at least one of the cover plate and the chip seat
Preferably, the lead frame of the present invention, wherein the semiconductor chip has a plurality of connection pads for external connection, and the cover unit has a plurality of guide ports spaced apart from each other and electrically connected to the connection pads, respectively.
Another object of the present invention is to provide a method for packaging a semiconductor device, which does not require a wire bonding process to avoid wire collapse.
The packaging method of the semiconductor element comprises a lead frame providing step, a chip arranging step, a sealing step and a cutting step.
The leadframe providing step provides the leadframe as described above.
The chip setting step is to set a semiconductor chip with at least one connection pad on the top surface of the chip seat of at least one lead frame component, and make the connection pad of the semiconductor chip face to one side far away from the chip seat.
The sealing step is to bend the connection unit of the at least one lead frame assembly to drive one of the cover plate unit and the chip setting unit to move, so that at least one guide port of the cover plate unit is connected with at least one connection pad of the semiconductor chip in an aligned manner, and a sealing space is formed between the cover plate unit and the chip seat.
The sealing step is to form a sealing layer coating the semiconductor chip in the sealing space to obtain at least a semi-finished product.
The cutting step is to cut off the at least one second connecting piece of the connecting unit of the at least semi-finished product in a laser mode so that the at least one guide port, the cover plate and the chip seat are electrically isolated from each other.
Preferably, in the packaging method of a semiconductor device of the present invention, the dicing step further cuts the first connection piece of each connection unit by a laser, so as to electrically isolate the chip carrier and the cover plate from each other.
Another object of the present invention is to provide a method for packaging a semiconductor device, which does not require a wire bonding process to avoid wire collapse.
The packaging method of the semiconductor element comprises a lead frame providing step, a chip arranging step, a sealing step and a cutting step.
The leadframe providing step provides a leadframe as described above.
The chip setting step is to set a semiconductor chip with at least one connection pad in the cover plate unit of at least one lead frame component and to electrically connect the at least one connection pad of the semiconductor chip and the corresponding at least one guide port.
The sealing step is to bend the connection unit of each lead frame assembly to drive one of the cover plate unit and the chip setting unit to move, so that the semiconductor chip is connected with the chip seat, and a sealing space is formed between the cover plate unit and the chip seat.
The sealing step is to form a sealing layer coating the semiconductor chip in the sealing space to obtain at least a semi-finished product.
The cutting step is to cut off the at least one second connecting piece of the connecting unit of the at least semi-finished product in a laser mode so that the at least one guide port, the cover plate and the chip seat are electrically isolated from each other.
Preferably, in the packaging method of a semiconductor device of the present invention, the dicing step further cuts the first connection piece of each connection unit by a laser, so as to electrically isolate the chip carrier and the cover plate from each other.
Another object of the present invention is to provide a package structure of a semiconductor device.
The invention relates to a packaging structure of a semiconductor element, which comprises a chip seat unit, a semiconductor chip, a cover plate unit and a sealing adhesive layer.
The chip holder unit includes a chip holder.
The semiconductor chip is arranged on the top surface of the chip seat and is provided with at least one connecting pad which is far away from the chip seat and is used for external electric connection.
The cover plate unit is arranged at intervals with the chip seat, clamps the semiconductor chip between the cover plate unit and the chip seat, and is provided with a cover plate and at least one guide port, wherein the cover plate and the at least one guide port are electrically isolated from each other, and the at least one guide port is electrically connected with the corresponding at least one connecting pad.
The sealing glue layer is filled between the cover plate unit and the chip seat and coats the semiconductor chip.
Preferably, the semiconductor chip of the package structure of the present invention has a plurality of connection pads, the package structure includes a plurality of conductive ports electrically independent from each other, and the conductive ports are respectively connected to the connection pads.
Preferably, the package structure of the semiconductor element of the present invention further includes a first connecting member connecting the cover plate and the chip carrier.
Preferably, in the package structure of a semiconductor element of the present invention, the cover plate and the chip carrier are independent from each other and are not connected.
The beneficial effects of the invention are that: the at least one guide port of the cover plate unit and the at least one connection pad of the semiconductor chip are electrically connected with each other by bending the connection unit, and the guide port can be used for external electrical connection, so that the wire bonding process is not needed, the wire bonding collapse in the traditional packaging process can be avoided, the yield of products is further improved, and in addition, the heat dissipation efficiency of the packaging structure can be improved by the cover plate unit.
Drawings
Fig. 1 is a schematic diagram illustrating an embodiment of a lead frame according to the present invention;
fig. 2 is a schematic diagram illustrating a leadframe assembly, and a semiconductor die according to the embodiments;
FIG. 3 is a schematic cross-sectional view illustrating one embodiment of a package structure of a semiconductor device of the present invention;
FIG. 4 is a flow chart illustrating an embodiment of a method of packaging a semiconductor device according to the present invention;
FIG. 5 is a flow diagram that assists FIG. 4 in illustrating the encapsulation method of the described embodiment; and
Fig. 6 is a flow chart illustrating the encapsulation method of the embodiment described with reference to fig. 5.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples.
Referring to fig. 1 and 2, an embodiment of a lead frame 200 of the present invention is suitable for packaging a semiconductor chip 1, where the semiconductor chip 1 may be a diode, a power device, etc., in this embodiment, the semiconductor chip 1 is exemplified by a field effect transistor (Field Effect Transistor) having a drain (D) and a source (S) on opposite sides, the field effect transistor 1 has a drain (D), a semiconductor active layer 11 on the drain (D), and a source (S) and a gate (G) on a side of the semiconductor active layer 11 away from the drain (D), and the source (S) and the gate (G) each have a connection pad 12 for external electrical connection, and the lead frame 200 is suitable for packaging the field effect transistor 1 (fig. 2 is exemplified by one of the die pads 311 of the lead frame 200, since the detailed structure of the field effect transistor 1 is well known in the art and is not emphasized in the prior art.
In detail, the leadframe 200 is made of a conductive material such as copper alloy or iron-nickel alloy, and includes a plurality of crisscross frame bars 2, and a plurality of leadframe assemblies 3 defined by two adjacent longitudinal frame bars 2 and two adjacent transverse frame bars 2, each leadframe assembly 3 includes a die-mounting unit 31, a cover unit 32, a connection unit 33, and a plurality of support bars 34.
The chip setting unit 31 includes a chip holder 311 which is formed in a flat plate shape and is provided with the semiconductor chip 1.
The cover unit 32 and the chip mounting unit 31 are located on the same horizontal plane, and include a cover 321 and two guide ports 322 (respectively indicated as 322S and 322G in fig. 2) for respectively and electrically connecting with the connection pads 12 of the source (S) and the gate (G).
The connection unit 33 has a first connector 331 for connecting the cover 321 and the chip holder 311, and a plurality of second connectors 332 for connecting the guide ports 322S, 322G and at least one of the cover 321 and the chip holder 311, respectively.
It should be noted that the number, positions and shapes of the guide ports 322 of the cover unit 32 correspond to the number and positions of the connection pads 12 electrically connected to the semiconductor chip 1, and the guide ports 322S, 322G shown in fig. 2 are examples of matching the source drain (S) and the gate (G) of the field effect transistor, and are not limited to the shape, the number and the positions in practical implementation. In addition, in the present embodiment, the connection unit 33 has three second connection members 332, wherein two second connection members 332 are used for respectively connecting the cover 321 and the chip holder 311 with the guide port 322G corresponding to the gate (G) (see fig. 2), and the other second connection member 332 is used for connecting the cover 321 with the guide port 322S corresponding to the source (S), but in practical implementation, the guide port 322 is only required to connect at least one of the cover 321 and the chip holder 311 through at least one second connection member 332.
The supporting bars 34 extend from the sides of the chip placement unit 31 and the cover unit 32 to the adjacent frame bars 2 and are connected to the frame bars 2, so that the lead frame assembly 3 has sufficient mechanical supporting force before the packaging process.
Referring to fig. 3, the lead frame 200 may be used to package the semiconductor chip 1, so as to obtain the package structure 400 of the semiconductor device shown in fig. 3. The package structure 400 includes a die pad unit 31, a semiconductor chip 1, a cover plate unit 32, and a sealing layer 4.
The chip carrier unit 31 comprises a chip carrier 311.
The semiconductor chip 1 is disposed on the top surface of the chip holder 311, and has the connection pad 12 far away from the chip holder 311 for external electrical connection. In this embodiment, the semiconductor chip 1 is exemplified by field effect transistors having a drain (D) and a source (S) respectively located at opposite sides, the field effect transistor 1 has a drain (D) electrically connected to the die pad 311, the semiconductor active layer 11 located on the drain (D), and a source (S) and a gate (G) located on a side of the semiconductor active layer 11 away from the drain (D), and the source (S) and the gate (G) are respectively formed with the connection pad 12 electrically connectable to the outside.
The cover unit 32 is disposed at a distance from the die pad 311, and sandwiches the semiconductor chip 1 between the cover unit 32 and the die pad 311, the cover unit 32 has the cover 321, the guide port 322S, and the guide port 332G, wherein the cover 321, the guide port 322G, and the guide port 322S are electrically isolated from each other, and the guide port 322S is electrically connected to the connection pad 12 corresponding to the source (S), and the guide port 322G is electrically connected to the connection pad 12 corresponding to the gate (G).
The sealing layer 4 is filled between the cover unit 32 and the die pad 311, and encapsulates the semiconductor chip 1 to protect the semiconductor chip 1.
It should be noted that, in some embodiments, the chip holder 311 may have various shapes according to requirements, in some embodiments, the chip setting unit 31 may further include a plurality of pin protruding portions (not shown) extending from one side of the chip holder 311 toward the adjacent frame strip 2, and formed at intervals from the frame strip 2 and arranged at intervals from each other, and the pin protruding portions may provide more elastic external electrical connection pins of the chip holder 311.
The aforementioned package structure 400 of the semiconductor device shown in fig. 3 may be manufactured by different packaging methods. Two different packaging methods are described below.
Referring to fig. 2 and fig. 4 to 6, the first packaging method or the second packaging method. The first packaging method includes a leadframe providing step S1, a chip arranging step S2, a capping step S3, a sealing step S4, and a dicing step S5.
The leadframe providing step S1 provides the leadframe 200 (see fig. 1) as described above.
In the chip setting step S2, the semiconductor chips 1 having the connection pads 12 of the source (S) and the gate (G) are correspondingly disposed on the top surface of the die pad 311 of the leadframe assembly 3, and the connection pads 12 of the source (S) and the gate (G) of the semiconductor chips 1 face to a side far from the die pad 311. Fig. 5 and 6 show only one group of leadframe assemblies 3, and fig. 4 to 6 are only illustrative of the manufacturing process, and the relative positions of the leadframe assemblies 3 and the source (S) and the gate (G) of the semiconductor chip 1 are shown, which are different from the actual positions of the source (S) and the gate (G) of the semiconductor chip 1 and the leadframe assemblies 3 in fig. 2.
The capping step S3 is to bend the first connecting piece 331 and the second connecting piece 332 of the connecting unit 33 of the lead frame assembly 3, which are connected to the die pad 311, so as to drive one of the cover unit 32 and the die-setting unit 31 to move, so that the guide port 322 of the cover unit 32 is aligned with the connection pad 12 of the semiconductor chip 1, and a molding space 40 is formed between the cover unit 32 and the die pad 311.
In detail, the capping step S3 is to form solder joints on the connection pads 12 or the lead ports 322 of the semiconductor chip 1; then to, for example: the supporting bar 34 corresponding to the cover unit 32 is removed by laser or stamping, and then the first connecting piece 331 and the second connecting piece 332 connected to the die pad 311 are bent, so as to move the cover unit 32 to cover the semiconductor chip 1, so that the guide ports 322S and 322G of the cover unit 32 are aligned with the connection pads 12 of the source (S) and the gate (G) of the semiconductor chip 1, and a packaged semi-product is obtained.
The sealing step S4 forms a sealing layer 4 covering the semiconductor chip 1 in the sealing space 40, thereby obtaining a semi-finished product 300.
In detail, in the sealing step S4, the semi-finished product of the package obtained in the sealing step S3 is placed into a mold (not shown), and then a molding compound is injected into the sealing space 40 in a molding mode, so that the sealing compound is hardened to form the sealing layer 4, thereby obtaining the semi-finished product 300.
Next, the dicing step S5 is performed, where the dicing step S5 is performed to cut the first connecting piece 331 and the second connecting piece 332 of the connecting unit 33 of the semi-finished product 300 by laser, so that the guide ports 322S and 322G are electrically isolated from the cover plate 321 and the chip carrier 311, and the package structure 400 shown in fig. 3 is obtained.
It should be noted that the first connector 331 and the second connector 332 may also be completely cut away as required, for example, the first connector 331 may not be cut away, and the package structure 400 may further have the first connector (not shown) connecting the cover 321 and the chip carrier 311; alternatively, the second connection element 332 connecting the guide port 322G and the chip holder 311 may be omitted, and only the second connection element 332 is disconnected from the guide port 322G, so that the drain D of the semiconductor chip 1 packaged in the chip holder 311 is used as an extended drain D capable of being electrically connected to the outside through the second connection element 332, and the electrical connection mode of the package structure 400 can be flexibly designed.
In addition, the aforementioned package structure 400 of the semiconductor device may also be manufactured by the second packaging method, which is different from the first packaging method in that the second packaging method is to package the semiconductor device by flip-chip, that is, when the chip arranging step S2 is performed, the semiconductor chip 1 with the connection pad 12 is arranged on the cover plate unit 32 of one of the lead frame assemblies 3, and the connection pad 12 of the semiconductor chip 1 and the corresponding guide port 322 are electrically connected to each other, so that the sealing step S3 is to cut the support bar 34 connected to the die pad 311 correspondingly, and then sequentially perform the sealing step S3 to the dicing step S5, so that the package structure 400 as shown in fig. 6 is also obtained.
The invention uses the structural design of the lead frame 200 to make the packaging structure 400 of the semiconductor device packaged by the lead frame 200 form the lead wire for external electric connection through the cover plate unit 32, so that the problem of wire bonding collapse in the packaging process can be avoided, and the yield of the packaging process of the semiconductor device can be improved. In addition, the cover plate 321 and the guide port 322 can also provide a protection effect for the semiconductor chip 1 and expose outside the sealing layer 4, so as to increase the heat dissipation area of the package structure 400, thereby improving the heat dissipation efficiency of the semiconductor device.
In summary, in the lead frame 200 of the present invention, the lead port 322 of the cover unit 32 is electrically connected with the connection pad 12 of the semiconductor chip 1 by bending the connection unit 33, so as to avoid the occurrence of wire collapse in the conventional packaging process, and further improve the yield of the product, and in addition, the cover unit 32 can also improve the heat dissipation efficiency of the packaging structure 400 and provide protection for the semiconductor chip 1, thereby truly achieving the purpose of the present invention.
However, the foregoing is merely illustrative of the present invention and, therefore, it is not intended to limit the scope of the invention, but it is intended to cover modifications and variations within the scope of the invention as defined by the appended claims and their equivalents.
Claims (10)
1. A leadframe for packaging a semiconductor chip, the semiconductor chip having at least one connection pad for external connection, the leadframe comprising a plurality of crisscrossed frame bars and a plurality of leadframe assemblies defined by any two adjacent crisscrossed frame bars, the leadframe comprising: each leadframe assembly includes:
the chip setting unit comprises a chip seat which is in a flat plate shape and is used for setting the semiconductor chip;
the cover plate unit is positioned on the same horizontal plane with the chip setting unit and comprises a cover plate and at least one guide port for electrically connecting with the at least one connecting pad; and
The connecting unit is provided with a first connecting piece for connecting the cover plate and the chip seat and at least one second connecting piece for connecting the at least one guide port and at least one of the cover plate and the chip seat.
2. The leadframe according to claim 1, wherein: the semiconductor chip is provided with a plurality of connecting pads for connecting to the external electricity, and the cover plate unit is provided with a plurality of guide ports which are mutually spaced and can be respectively and correspondingly and electrically connected with the connecting pads.
3. A method of packaging a semiconductor device, comprising: comprising:
a leadframe providing step of providing the leadframe according to claim 1;
a chip setting step, namely setting a semiconductor chip with at least one connecting pad on the top surface of a chip seat of at least one lead frame component, and enabling the connecting pad of the semiconductor chip to face to one side far away from the chip seat;
a cover sealing step, namely bending the connecting unit of the at least one lead frame assembly to drive one of the cover plate unit and the chip setting unit to move, so that at least one guide port of the cover plate unit is connected with at least one connecting pad of the semiconductor chip in an alignment manner, and a sealing space is formed between the cover plate unit and the chip seat;
a sealing step, namely forming a sealing layer coating the semiconductor chip in the sealing space to obtain at least a semi-finished product; and
And cutting off the at least one second connecting piece of the connecting unit of the at least semi-finished product in a laser mode to enable the at least one guide port, the cover plate and the chip seat to be electrically isolated from each other.
4. A method of packaging a semiconductor device according to claim 3, wherein: the cutting step is also to cut the first connecting piece of each connecting unit in a laser mode so as to electrically isolate the chip seat and the cover plate from each other.
5. A method of packaging a semiconductor device, comprising: comprising:
a leadframe providing step of providing the leadframe according to claim 1;
a chip setting step, in which a semiconductor chip with at least one connection pad is set in the cover plate unit of at least one lead frame component, and the at least one connection pad of the semiconductor chip and the corresponding at least one guide port are electrically connected with each other;
a capping step of bending the connection unit of each lead frame assembly to drive one of the cover plate unit and the chip setting unit to move so as to connect the semiconductor chip with the chip seat and form a sealing space between the cover plate unit and the chip seat;
a sealing step, namely forming a sealing layer coating the semiconductor chip in the sealing space to obtain at least a semi-finished product; and
And cutting off the at least one second connecting piece of the connecting unit of the at least semi-finished product in a laser mode to enable the at least one guide port, the cover plate and the chip seat to be electrically isolated from each other.
6. The method of packaging a semiconductor device according to claim 5, wherein: the cutting step is also to cut off the first connecting piece of each connecting unit in a laser mode so that the chip seat and the cover plate are electrically isolated from each other.
7. A packaging structure of a semiconductor element is characterized in that: comprising:
the chip seat unit comprises a chip seat;
the semiconductor chip is arranged on the top surface of the chip seat and is provided with at least one connecting pad which is far away from the chip seat and is used for external electric connection;
the cover plate unit is arranged at intervals with the chip seat, clamps the semiconductor chip between the cover plate unit and the chip seat, and is provided with a cover plate and at least one guide port, wherein the cover plate and the at least one guide port are electrically isolated from each other, and the at least one guide port is electrically connected with the corresponding at least one connecting pad; and
And the sealing adhesive layer is filled between the cover plate unit and the chip seat and coats the semiconductor chip.
8. The package structure of a semiconductor device according to claim 7, wherein: the semiconductor chip is provided with a plurality of connection pads, the packaging structure comprises a plurality of guide ports which are electrically independent from each other, and the guide ports are respectively and correspondingly connected with the connection pads.
9. The package structure of a semiconductor device according to claim 7, wherein: the first connecting piece is used for connecting the cover plate and the chip seat.
10. The package structure of a semiconductor device according to claim 7, wherein: the cover plate and the chip seat are independent from each other and are not connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210739106.8A CN117352477A (en) | 2022-06-28 | 2022-06-28 | Lead frame and packaging method and structure of semiconductor element thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210739106.8A CN117352477A (en) | 2022-06-28 | 2022-06-28 | Lead frame and packaging method and structure of semiconductor element thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117352477A true CN117352477A (en) | 2024-01-05 |
Family
ID=89354385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210739106.8A Pending CN117352477A (en) | 2022-06-28 | 2022-06-28 | Lead frame and packaging method and structure of semiconductor element thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117352477A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118380340A (en) * | 2024-06-21 | 2024-07-23 | 广东风华芯电科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
-
2022
- 2022-06-28 CN CN202210739106.8A patent/CN117352477A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118380340A (en) * | 2024-06-21 | 2024-07-23 | 广东风华芯电科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
| CN118380340B (en) * | 2024-06-21 | 2024-10-01 | 广东风华芯电科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8389336B2 (en) | Semiconductor device package and method of assembly thereof | |
| US6812554B2 (en) | Semiconductor device and a method of manufacturing the same | |
| CN102714201B (en) | Semiconductor packages and method | |
| US8836101B2 (en) | Multi-chip semiconductor packages and assembly thereof | |
| US9159588B2 (en) | Packaged leadless semiconductor device | |
| CN103608917B (en) | Ultra-thin power transistor and the synchronous step-down converter with customization footprints | |
| KR102402841B1 (en) | Lead frame, semiconductor device, and method for manufacturing lead frame | |
| US6573119B1 (en) | Semiconductor device and method of manufacture thereof | |
| US9040357B2 (en) | Semiconductor packaging method using connecting plate for internal connection | |
| CN117352477A (en) | Lead frame and packaging method and structure of semiconductor element thereof | |
| CN104979323A (en) | Quad flat non-leaded package and method of manufacturing the same | |
| CN101978491A (en) | Semiconductor chip package assembly method and apparatus for countering leadfinger deformation | |
| CN107305851B (en) | Method for manufacturing semiconductor device and semiconductor device | |
| JP3160994U (en) | Resin molded lead frame | |
| US10840172B2 (en) | Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package | |
| US7977776B2 (en) | Multichip discrete package | |
| JP2013143519A (en) | Connector and resin sealed type semiconductor device | |
| US20110062569A1 (en) | Semiconductor device package with down-set leads | |
| US7005728B1 (en) | Lead configuration for inline packages | |
| EP4425537A2 (en) | Hybrid multi-die qfp-qfn package | |
| EP4411814A1 (en) | Method of manufacturing semiconductor devices, corresponding ribbon, apparatus and device | |
| US20240178179A1 (en) | Method of manufacturing semiconductor devices and corresponding semiconductor device | |
| CN219267648U (en) | Semiconductor chip packaging structure | |
| KR20000011664A (en) | Semiconductor device and method for producing the same | |
| JP3763788B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |