CN212694060U - Satellite navigation receiving board card, device and system - Google Patents
Satellite navigation receiving board card, device and system Download PDFInfo
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- CN212694060U CN212694060U CN202021159432.4U CN202021159432U CN212694060U CN 212694060 U CN212694060 U CN 212694060U CN 202021159432 U CN202021159432 U CN 202021159432U CN 212694060 U CN212694060 U CN 212694060U
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Abstract
The application discloses a satellite navigation receiving board card, a device and a system, wherein the board card comprises a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals; the receiving module and the auxiliary capturing module are connected to the signal processing module in parallel. By adding the auxiliary capturing module, other frequency point capturing can be guided by rapidly capturing the main frequency point for rapid capturing during starting, so that the power consumption of the capturing part is reduced, and the capturing performance is improved.
Description
Technical Field
The application relates to the technical field of satellite navigation, in particular to a satellite navigation receiving board card, a device and a system.
Background
GNSS (Global Navigation Satellite System) refers to all Satellite Navigation systems, such as GPS in the united states, Glonass in russia, Galileo in europe, and beidou Satellite Navigation System BDS in china, for example.
Currently, a GNSS receiver board card mainly comprises a radio frequency front end processing module, an FPGA and an ARM core processor. The RF front-end processing module receives a visible satellite signal mainly through an antenna, and after the visible satellite signal is filtered and amplified by a pre-filter and an amplifier, the visible satellite signal is mixed with a sine wave local oscillator signal generated by a local oscillator to be converted into an intermediate frequency signal in a down-conversion mode, and finally the intermediate frequency signal is converted into a discrete-time data intermediate frequency signal through an analog-to-digital converter, wherein a VCO (voltage controlled oscillator), a frequency mixing module, an IF (intermediate frequency) filtering module, an ADC (analog-to-digital. The FPGA is a baseband digital signal processing module, carries out bit synchronization and frame synchronization processing on signals, thereby obtaining signal emission time and navigation messages from the received signals and finally realizing positioning, and the chip adopts an Altera A9 chip and has the capacity of processing partial frequency point signals of GPS, BDS3, GLONASS and GALILEO. The ARM core processor mainly selects an AM3352 chip of the TI, operates a TI-rtos system and mainly bears a baseband processing function with high real-time performance. And complex functions such as network communication, user interface and the like need to be completed by virtue of an EVK (Ethernet virtual K) board or a backplane.
The inventor finds that the existing GNSS receiver board card mainly has the following disadvantages: 1) the GNSS recapture function is not provided, and the capture sensitivity is poor; 2) the capability of processing all mainstream satellite system signals and frequency points is not provided; 3) it is difficult to simultaneously compatible with a plurality of high-precision positioning algorithms, and other complex functions such as network communication, user interface and the like need to be completed by additionally adding an ARM chip. 4) The CPU response speed is slow, the satellite positioning has certain time delay, and the data has packet loss under the high-frequency data requirement of a user; 5) the anti-interference capability is not provided in a complex scene; 6) electromagnetic interference can be introduced between components.
Therefore, it is particularly necessary to provide a satellite navigation receiving board card, a device and a system with a novel architecture.
SUMMERY OF THE UTILITY MODEL
Based on this, the present application aims to provide a satellite navigation receiving board card, a device and a system, so as to solve at least one of the above technical problems. The technical scheme is as follows:
on one hand, the application provides a satellite navigation receiving board card, which comprises a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals, and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals;
the input end of the receiving module and the input end of the auxiliary capturing module respectively receive external high-frequency signals, the output end of the receiving module and the output end of the auxiliary capturing module are connected to the input interface end of the signal processing module in parallel, and the output interface end of the signal processing module outputs the navigation data.
In one possible implementation manner, the auxiliary acquisition module includes an MX2708 chip for quickly acquiring at least 2 satellite dominant frequency point signals and guiding other frequency points and satellites.
In one possible implementation, the number of the receiving modules is at least one; and if each receiving module has three solution frequency point channels, the number of the receiving modules is three.
In one possible implementation manner, the signal processing module is an integrated chip, and the integrated chip includes a satellite signal capturing unit that obtains all satellite signals based on the received signals and the captured satellite main frequency point signals, and a satellite signal processing unit that processes all satellite signals captured by the satellite signal capturing unit to obtain navigation data.
In one possible implementation, the satellite signal processing unit includes a dual-core CPU with heterogeneous operating systems.
In one possible implementation, the dual-core CPU includes a first CPU for processing baseband digital signals in real time and a second CPU for performing navigation solution.
In one possible implementation, the signal processing module includes a storage interface for obtaining the relevant data;
the storage interface comprises a DDR interface, a QUAR SPI flash interface used for acquiring the related data of the second CPU and an SD CARD interface used for acquiring the related data of the first CPU.
In one possible implementation manner, the receiving module includes a radio frequency module for down-converting the high-frequency signal and an AD conversion module;
the input end of the radio frequency module receives an external high-frequency signal, and the output end of the radio frequency module is in signal connection with the input end of the AD conversion module;
the output end of the AD conversion module is in signal connection with the first input interface end of the signal processing module;
the output end of the auxiliary capture module is in signal connection with the second input interface end of the signal processing module.
On the other hand, the application provides a satellite navigation receiving device, which comprises any one of the satellite navigation receiving board cards.
In another aspect, the present application provides a satellite navigation receiving system, including the above-mentioned satellite navigation receiving board device.
The application provides a satellite navigation receives integrated circuit board, device and system has following beneficial effect at least:
the satellite navigation receiving board card comprises a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals. By adding the auxiliary capturing module, other frequency point capturing can be guided by rapidly capturing the main frequency point for rapid capturing during starting, so that the power consumption of the capturing part is reduced, and the capturing performance is improved.
In addition, this application is through using integrated chip as signal processing module, and this integrated chip has integrateed dual-core CPU and abundant logic resource, and accessible class AXI bus carries out logic device and CPU data interchange, not only can reduce the integrated circuit board size, reduces the electromagnetic interference of components and parts, has solved the data transmission bandwidth bottleneck simultaneously, and abundant logic resource can integrate anti-interference, catch the tracking anterior segment link function of 14 at least frequency points, provides an thinking for the integrated circuit board chipization.
In addition, the satellite navigation receiving board card, the satellite navigation receiving device and the satellite navigation receiving system support onboard RTK and PPP high-precision positioning algorithms, and can support inertial navigation and GNSS RTK combined positioning capacity. The method has the function of resisting in-band narrow-band interference, and can effectively inhibit narrow-band interference existing in a working environment. Meanwhile, the system has RTK working capacity in a complex application scene, and has working performance equivalent to that of an international advanced OEM product in a typical complex application scene (such as ionospheric scintillation, interference, tree shadow, building shielding and the like).
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a block diagram of a satellite navigation receiving board card according to an embodiment of the present application;
fig. 2 is a block diagram illustrating a structure of another satellite navigation receiving board according to an embodiment of the present disclosure;
fig. 3 is a block diagram illustrating a structure of another satellite navigation receiving board in an embodiment of the present application;
fig. 4 is a schematic diagram illustrating frequency point setting in a radio frequency scheme according to an embodiment of the present application;
fig. 5 shows a schematic block diagram of an auxiliary acquisition module in a satellite navigation receiving board according to an embodiment of the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "left", "right", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
Currently, a GNSS receiver board card mainly comprises a radio frequency front end processing module, an FPGA and an ARM core processor. The RF front-end processing module receives a visible satellite signal mainly through an antenna, and after the visible satellite signal is filtered and amplified by a pre-filter and an amplifier, the visible satellite signal is mixed with a sine wave local oscillator signal generated by a local oscillator to be converted into an intermediate frequency signal in a down-conversion mode, and finally the intermediate frequency signal is converted into a discrete-time data intermediate frequency signal through an analog-to-digital converter, wherein a VCO (voltage controlled oscillator), a frequency mixing module, an IF (intermediate frequency) filtering module, an ADC (analog-to-digital. The FPGA is a baseband digital signal processing module, carries out bit synchronization and frame synchronization processing on signals, thereby obtaining signal emission time and navigation messages from the received signals and finally realizing positioning, and the chip adopts an Altera A9 chip and has the capacity of processing partial frequency point signals of GPS, BDS3, GLONASS and GALILEO. The ARM core processor mainly selects an AM3352 chip of the TI, operates a TI-rtos system and mainly bears a baseband processing function with high real-time performance. And complex functions such as network communication, user interface and the like need to be completed by virtue of an EVK (Ethernet virtual K) board or a backplane.
The existing GNSS receiver board card mainly has the following disadvantages:
1) the GNSS recapture function is not provided, and the capture sensitivity is poor;
2) the capability of processing all mainstream satellite system signals and frequency points is not provided;
3) it is difficult to simultaneously compatible with a plurality of high-precision positioning algorithms, and other complex functions such as network communication, user interface and the like need to be completed by additionally adding an ARM chip.
4) The CPU response speed is slow, the satellite positioning has certain time delay, and the data has packet loss under the high-frequency data requirement of a user;
5) the anti-interference capability is not provided in a complex scene;
6) electromagnetic interference can be introduced between components.
The inventor finds that the existing GNSS receiver board card mainly has the following disadvantages: a) when the board card is restarted or the GNSS signal is unlocked and recovered, the signal capturing rate is slow, and the full frequency point capturing power consumption is large in the process. b) A9 chip FGPA logic channel is limited, can not integrate anti-interference, capture and more frequency point tracking front-end link functions. c) And the CPU resource bottleneck of the AM3352 chip is realized, and no resource is used for processing other applications after the baseband data processing and positioning algorithm is realized. d) The FPGA and the ARM carry out data transmission through a serial port, the communication between chips is achieved, and the data transmission has certain bottleneck. e) The board card has large area, many components and parts and complex circuits, and the two main chips are not packaged, so that electromagnetic interference is easily introduced between the components and parts. To address at least one of the problems of the prior art, the present application provides a satellite navigation receiver board, an apparatus and a system.
The satellite navigation receiving board, the device and the system related to the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 shows a block diagram of a satellite navigation receiving board card according to an embodiment of the present application. As shown in fig. 1, the satellite navigation receiving board 100 includes a receiving module 110 for receiving a satellite signal, an auxiliary capturing module 120 for capturing a satellite main frequency point signal, and a signal processing module 130 for obtaining navigation data based on the received signal and the captured satellite main frequency point signal.
The input end of the receiving module 110 and the input end of the auxiliary capturing module 120 respectively receive external high-frequency signals, the output end of the receiving module 110 and the output end of the auxiliary capturing module are connected to the input interface end of the signal processing module 130 in parallel, and the output interface end of the signal processing module 130 outputs the navigation data.
The satellite navigation receiving board card comprises a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals. By adding the auxiliary capturing module, other frequency point capturing can be guided by rapidly capturing the main frequency point for rapid capturing during starting, so that the power consumption of the capturing part is reduced, and the capturing performance is improved.
In one possible implementation, the auxiliary acquisition module 120 includes a chip for quickly acquiring at least 2 satellite main frequency point signals and guiding other frequency points and satellites.
As just one specific example, the auxiliary capture module 120 may be a dream core chip, such as but not limited to an MX2708 chip. The MX2708 chip can be used for rapidly capturing the two main frequency points and then guiding the capturing of other frequency points and satellites because the chip only uses 2 frequency points GPS L1 and BDS B1.
The auxiliary capture module 120 guides other frequency points to capture by rapidly capturing the main frequency point, and is used for rapidly capturing during starting, so as to reduce the power consumption of a capture part and improve the capture performance.
In a possible implementation manner, fig. 2 shows a block diagram of another satellite navigation receiving board. As shown in fig. 2, the receiving module 110 may include a radio frequency module 111 for down-converting a high frequency signal and an AD conversion module 112.
The input end of the radio frequency module 111 receives an external high-frequency signal, and the output end of the radio frequency module 111 is in signal connection with the input end of the AD conversion module 112. The video module 111 down-converts a high-frequency signal received from the outside into an intermediate-frequency analog signal, and then inputs the intermediate-frequency analog signal to the AD conversion module 112 for analog-to-digital conversion, and converts the intermediate-frequency analog signal into a corresponding intermediate-frequency digital signal.
The output end of the AD conversion module 112 is connected to the first input interface end of the signal processing module 130.
The output terminal of the auxiliary capture module 120 is connected to the second input interface terminal of the signal processing module 130. The AD conversion module 112 inputs the converted intermediate frequency digital signal to the signal processing module 130, and the signal processing module 130 combines the intermediate frequency digital signal and the satellite main frequency point signal input by the auxiliary capturing module 120 to capture the satellite signal and perform satellite signal processing.
As a specific example only, the receiving module 110 may include a radio frequency signal receiving chip, for example, but not limited to, an RX3902b chip, and the RX3902b chip is a multi-mode, multi-band, three-channel radio frequency receiving chip. Of course, the radio frequency signal receiving chip can also be other multi-channel radio frequency receiving chips.
In one possible implementation, the number of the receiving modules 110 is at least one. For example, the number of the receiving modules 110 is 1, 2, 3 or more. The number of the receiving modules 110 is related to the number of the solution frequency point channels of the satellite navigation receiving board card and the number of all satellite frequency points.
For example, fig. 4 shows a schematic diagram of frequency point setting in a radio frequency scheme according to an embodiment of the present application. Through counting all the satellite frequency points, 8 different frequency points can be counted, as shown in fig. 4, the 8 different frequency points are respectively "1176.45", 1207.140 "," 1227.6 "," 1246.4375 "," 1268.52 "," 1561.098 "," 1575.42 "and" 1602.5625 "(unit Mhz), and the frequency intervals between two adjacent frequency points are respectively 30M, 20M, 18M, 22M, 14M and 27M. At this time, the intermediate frequency output bandwidth of the RX3902b chip can be set to be 10M/20M/30M/40M respectively. Because the intermediate frequency output bandwidth is not large, 2 frequency points can be placed in each channel of the RX3902b chip at most, and considering that 8 different frequency points need to be solved at present, all frequency points can not be covered by 3 channels of one RX3902b chip. In order to ensure that all frequency points can be solved, a narrow-band mode is used, namely, only one frequency point is solved in each channel; to solve 8 different frequency points, 8 channels are needed, that is, 3 chips RX3902b are needed.
Taking the number of satellite frequency points as 14 as an example, the satellite frequency points have 8 different frequency points, and 3 RX3902b chips are needed when an RX3902b chip with three channels is used as a receiving module. Here, 3 RX3902b chips are used to have 9 channels, 8 frequency thresholds are selected according to carrier frequency, and by setting the frequency thresholds, the unwanted waves of other frequencies can be filtered, so that the unwanted waves of other frequencies can not be received, and the function of narrow-band anti-interference is realized.
It should be noted that, with the development of the technology in the field, if the number of the satellite frequency points is adjusted, the number of RX3902b chips corresponding to the adjusted satellite frequency points may be adaptively adjusted.
In an optional embodiment, in order to meet the requirements of the satellite signal receiving board on area and power consumption, a broadband radio frequency chip with an ADC can be further used. Meanwhile, an external 10-bit ADC device is used as a redundancy design to improve the anti-interference performance.
In an optional implementation manner, the satellite signal receiving board may further include a front-end radio frequency processing module (not shown), where the front-end radio frequency processing module includes a low-noise amplifier LNA, a power divider, and a band-pass filter. After the antenna receives the high-frequency signal, the high-frequency signal is sequentially processed by a low-noise amplifier LNA, a power divider and a band-pass filter in the front-end radio frequency processing module, the processed high-frequency signal is input to the receiving module 110, the receiving module 110 performs down-frequency processing on the high-frequency signal, and of course, the processing also includes performing other processing such as filtering clutter and noise, down-converting the high-frequency signal to an intermediate-frequency analog signal, performing analog-to-digital conversion on the intermediate-frequency analog signal to obtain an intermediate-frequency digital signal, and then inputting the intermediate-frequency digital signal to the signal processing module.
In one possible implementation, as shown in fig. 2 and 3, the signal processing module 130 may include an integrated chip including a PL portion and a PS portion.
The PL section is mainly a logic processing unit that may include a satellite signal acquisition unit 131 that derives all satellite signals based on the received signals and the acquired satellite primary frequency point signals. In a possible implementation manner, in the case that the number of the satellite frequency points is 15, the satellite signal capturing unit 131 has 180 (i.e. 15 × 12) physical channels. Specifically, the intermediate frequency digital signal processed by the receiving module 110 enters a PL portion in the signal processing module, and the satellite signal capturing unit 131 in the PL portion can capture one satellite per channel by analyzing the intermediate frequency digital signal, and the unit has 180(15 × 12) physical channels, so that satellite signals of 15 frequency points can be captured. For example, mainstream satellite navigation system signals such as beidou B1C, B2a, B1I, B3I, GPS L1C/A, L1C, L2P (Y), L2C, L5, GLONASS L1, L2, GALILEO E1, E5a, E5B and the like can be received and processed at the same time.
The PS part may include a satellite signal processing unit 132 that processes all satellite signals acquired by the satellite signal acquisition unit to obtain navigation data. For example only, the satellite signal processing unit 132 may be an ARM, which may include positioning pacing by running a PVT algorithm.
In one possible implementation, the satellite signal processing unit 132 may include a dual-core CPU with heterogeneous operating systems.
In one possible implementation, the dual-core CPU includes a first CPU for processing baseband digital signals in real time and a second CPU for performing navigation solution.
As a specific example only, the signal processing module 130 may be a ZYNQ series chip, such as a chip including but not limited to a model ZYNQ-7045. The ZYNQ-7045 type chip integrates two cotex A9 and abundant logic resources, and exchanges logic devices, a CPU and data through a sheet type AXI bus, so that the bottleneck of data transmission bandwidth is solved. Abundant logic resources, and can integrate the functions of anti-interference, capturing and tracking front-segment links of at least 14 frequency points. The dual-CORE CPU is designed by adopting a heterogeneous Operating System (OS), wherein the CORE0 (namely a second CPU) runs a linux system, mainly bears the functions of navigation positioning calculation and can also bear the functions of network communication, a user interface and the like. The CORE0 may be made into open cup form for the development of user applications. The CORE1 (i.e., the first CPU) may run a free rtos system, which mainly carries the function of baseband digital signal processing with higher real-time performance.
This application is through using integrated chip as signal processing module 130, this integrated chip has integrateed dual-core CPU and abundant logic resource, and accessible class AXI bus carries out logic device and CPU data interchange, not only can reduce the integrated circuit board size, reduces the electromagnetic interference of components and parts, has solved the data transmission bandwidth bottleneck simultaneously, and abundant logic resource can integrate anti-interference, catch the tracking anterior segment link function of 14 at least frequency points, provides an thinking for the integrated circuit board chipization.
In order to facilitate understanding of the present application, the following specifically explains the working principle of the satellite navigation receiving board card of the present application:
the satellite navigation receiving board card mainly comprises an analog circuit and a digital circuit, wherein the analog circuit is used for receiving GNSS signals, converting the GNSS signals into intermediate-frequency digital signals and inputting the intermediate-frequency digital signals into the digital circuit. And the digital circuit captures and tracks the converted GNSS signals, performs positioning calculation to obtain navigation data such as original observation data, ephemeris and positioning results, and outputs the navigation data to a user.
The analog circuit mainly includes a receiving module 110, and the receiving module 110 includes a radio frequency module and an AD conversion module. In order to meet the requirements of board card area and power consumption, a broadband radio frequency chip (such as RX3902b) with an ADC is adopted, and meanwhile, an external 10-bit ADC device is used as a redundancy design, so that the anti-interference performance is improved. The RX3902b chip mainly has the functions of reducing the frequency of high-frequency signals, filtering clutter and noise, and converting analog signals into digital signals through an ADC (analog-to-digital converter) inside the chip. Here, 3 RX3902b chips are used, 9 channels are provided, 8 frequency thresholds are selected according to carrier frequency, and therefore useless waves of other frequencies cannot be received, so that a narrowband anti-interference function is achieved, and meanwhile, a 10-bit ADC device is externally connected to serve as a redundancy design, so that the anti-interference performance is improved.
The digital circuit may include a signal processing module 130, and the signal processing module 130 may use a ZYNQ series chip as a main chip. The main chip may acquire the digital intermediate frequency data sent by the receiving module 110 and the frequency point signal captured by the auxiliary capturing module 120 to perform preprocessing, anti-interference, baseband algorithm, device management, and the like. The main chip comprises a PL part and a PS part, wherein the PL part is mainly a logic processing unit, and by analyzing the intermediate digital signals, under the condition that the number of satellite frequency points is 15, the unit has 180(15 × 12) physical channels, and each channel can capture one satellite, so that the satellite signals of the 15 frequency points can be captured. Two cotex A9 and abundant logic resources are integrated in the PS part, and the logic device, the CPU and data are exchanged through the sheet AXI bus, so that the bottleneck of data transmission bandwidth is solved. Abundant logic resources, and can integrate the functions of anti-interference, capturing and tracking front-section links of 15 frequency points. The dual-CORE CPU adopts heterogeneous OS design, and the CORE0 runs a linux system and bears complex functions such as positioning calculation, network communication, user interface and the like. The CORE1 runs a free rtos system and mainly carries the function of baseband digital signal processing with high real-time performance.
For example only, the auxiliary capturing module 120 may be a core chip, and is configured to rapidly capture main frequency point signals (for example, 2 main frequency points, such as GPS L1 and BDS B1) at startup, guide capturing of other frequency points and satellites, and provide the captured frequency point signals to the signal processing module 130 in the digital circuit for processing, so as to reduce power consumption of a capturing part and improve capturing performance. The auxiliary capture module 120 may include both an analog circuit for data conversion and a digital circuit for auxiliary capture of frequency point signals.
In a specific application, the auxiliary acquisition module 120 may employ a method of parallel pseudo code phase and doppler search, i.e., partial matched filtering and fast fourier transform together. The implementation method can be unified with a GNSS satellite signal capturing method, and different constellations, different frequency points and different satellites can be captured by configuring different parameters. The auxiliary capture module 120 at least has the following functions: can adapt to different pseudo code rates; can adapt to different pseudo code types; different coherent integration times can be set; different non-coherent integration times can be set; can cover a specified doppler search range.
In a specific embodiment, fig. 5 shows a schematic block diagram of an auxiliary acquisition module in a satellite navigation receiving board according to an embodiment of the present disclosure, and as shown in fig. 5, the auxiliary acquisition module 120 receives an input signal and a local carrier, sequentially performs down-conversion and down-sampling, then performs N-Tap delay line (N-Tap delay line) signal modulation using an obtained pseudo code rate, then performs coherent integration together with a local pseudo code obtained from a pseudo code memory, and then sequentially performs M-point fast fourier transform, I-point fast fourier transform, and I-point fast fourier transform2+Q2And calculating an incoherent accumulation value, and detecting and outputting a pseudo code phase and Doppler corresponding to the maximum incoherent accumulation value, thereby realizing phase estimation and Doppler estimation corresponding to auxiliary acquisition of satellite main frequency point signals.
In one possible implementation, the NVM uses an SD + norflash scheme in consideration of the small chip-supported nor flash space and no support for inter-CORE shared peripherals, the SD card is used for system and mass data access, and norflash is allocated to CORE1 for satellite list, observation and ephemeris data access. As shown in fig. 3, the signal processing module further includes a storage interface for acquiring related data;
the storage interface comprises a DDR interface, a QUAR SPI flash interface used for acquiring the related data of the second CPU and an SD CARD interface used for acquiring the related data of the first CPU. For example only, the first CPU related data includes BOOT LOADER, operating system and APP for core0 to run. At this time, the SD CARD interface is connected with SD CARD for placing BOOT LOADER, an operating system for running core0, and APP. The second CPU related data includes, but is not limited to, an operating system and APP for running the OS and APP of CORE 1. At this point, the QUAR SPI flash interface is connected with a QUAR SPI flash that places the operating system and APP, including but not limited to the OS and APP for running CORE 1.
In one possible implementation, the satellite signal receiving board 100 may further include a clock module (not shown), a debug interface (not shown), and a power interface (not shown).
On the other hand, the present application provides a satellite navigation receiving device (not shown) including any of the above satellite navigation receiving board.
In another aspect, the present application provides a satellite navigation receiver system (not shown), including the above-mentioned satellite navigation receiver board device.
The satellite navigation receiving board card, the satellite navigation receiving device and the satellite navigation receiving system of the embodiment of the application comprise a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals. By adding the auxiliary capturing module, other frequency point capturing can be guided by rapidly capturing the main frequency point for rapid capturing during starting, so that the power consumption of the capturing part is reduced, and the capturing performance is improved.
In addition, the satellite navigation receiving board card, the satellite navigation receiving device and the satellite navigation receiving system have the advantages that the integrated chip is used as the signal processing module, the dual-core CPU and rich logic resources are integrated, data exchange between logic devices and the CPU can be carried out through the piece type AXI bus, the size of the board card can be reduced, electromagnetic interference of the components is reduced, the bottleneck of data transmission bandwidth is solved, the rich logic resources can integrate the functions of resisting interference and capturing tracking front-section links of 15 frequency points, and an idea is provided for the chip of the board card.
The satellite navigation receiving board card, the satellite navigation receiving device and the satellite navigation receiving system support onboard RTK and PPP high-precision positioning algorithms, and can support inertial navigation and GNSS RTK combined positioning capacity. The method has the function of resisting in-band narrow-band interference, and can effectively inhibit narrow-band interference existing in a working environment. Meanwhile, the system has RTK working capacity in a complex application scene, and has working performance equivalent to that of an international advanced OEM product in a typical complex application scene (such as ionospheric scintillation, interference, tree shadow, building shielding and the like).
It should be noted that: the sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. And specific embodiments thereof have been described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the device and server embodiments, since they are substantially similar to the method embodiments, the description is simple, and the relevant points can be referred to the partial description of the method embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.
Claims (10)
1. A satellite navigation receiving board card is characterized by comprising a receiving module for receiving satellite signals, an auxiliary capturing module for capturing satellite main frequency point signals and a signal processing module for obtaining navigation data based on the received signals and the captured satellite main frequency point signals;
the input end of the receiving module and the input end of the auxiliary capturing module respectively receive external high-frequency signals, the output end of the receiving module and the output end of the auxiliary capturing module are connected to the input interface end of the signal processing module in parallel, and the output interface end of the signal processing module outputs the navigation data.
2. The board card of claim 1, wherein the auxiliary capture module comprises a chip for rapidly capturing at least 2 satellite dominant frequency point signals and guiding other frequency points and satellites.
3. The board card of claim 1, wherein the number of the receiving modules is at least one; and if each receiving module has three solution frequency point channels, the number of the receiving modules is three.
4. The board card of any one of claims 1 to 3, wherein the signal processing module is an integrated chip, and the integrated chip includes a satellite signal capturing unit that obtains all satellite signals based on the received signals and the captured satellite main frequency point signals, and a satellite signal processing unit that processes all satellite signals captured by the satellite signal capturing unit to obtain navigation data.
5. The board of claim 4, wherein the satellite signal processing unit comprises a dual-core CPU with heterogeneous operating systems.
6. The board card of claim 5, wherein the dual-core CPU comprises a first CPU for real-time processing of baseband digital signals and a second CPU for navigation solution.
7. The board card of claim 6, wherein the signal processing module comprises a storage interface for obtaining relevant data;
the storage interface comprises a DDR interface, a QUAR SPI flash interface used for acquiring the related data of the second CPU and an SD CARD interface used for acquiring the related data of the first CPU.
8. The board card of any one of claims 1-3, wherein the receiving module includes a radio frequency module for down-converting a high frequency signal and an AD conversion module;
the input end of the radio frequency module receives an external high-frequency signal, and the output end of the radio frequency module is in signal connection with the input end of the AD conversion module;
the output end of the AD conversion module is in signal connection with the first input interface end of the signal processing module;
the output end of the auxiliary capture module is in signal connection with the second input interface end of the signal processing module.
9. A satellite navigation receiver, characterized in that it comprises the satellite navigation receiver board of any one of claims 1-8.
10. A satellite navigation receiving system comprising the satellite navigation receiving apparatus according to claim 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111830541A (en) * | 2020-06-19 | 2020-10-27 | 浙江时空道宇科技有限公司 | Satellite navigation receiving board card, device and system |
| CN113050129A (en) * | 2021-03-17 | 2021-06-29 | 广州南方卫星导航仪器有限公司 | Satellite signal capturing method and device |
| CN113079138A (en) * | 2021-03-23 | 2021-07-06 | 哈尔滨理工大学 | Online filtering system for biological information data |
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2020
- 2020-06-19 CN CN202021159432.4U patent/CN212694060U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111830541A (en) * | 2020-06-19 | 2020-10-27 | 浙江时空道宇科技有限公司 | Satellite navigation receiving board card, device and system |
| CN113050129A (en) * | 2021-03-17 | 2021-06-29 | 广州南方卫星导航仪器有限公司 | Satellite signal capturing method and device |
| CN113050129B (en) * | 2021-03-17 | 2023-08-01 | 广州南方卫星导航仪器有限公司 | Satellite signal capturing method and device |
| CN113079138A (en) * | 2021-03-23 | 2021-07-06 | 哈尔滨理工大学 | Online filtering system for biological information data |
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