CN212675584U

CN212675584U - Wireless charging transmitting chip

Info

Publication number: CN212675584U
Application number: CN202020631261.4U
Authority: CN
Inventors: 徐圣楠; 白栎旸; 黄志忠
Original assignee: Shanghai Sizhen Microelectronics Co ltd
Current assignee: Shanghai Sizhen Microelectronics Co ltd
Priority date: 2020-04-23
Filing date: 2020-04-23
Publication date: 2021-03-09
Anticipated expiration: 2030-04-23

Abstract

The utility model discloses a wireless transmission chip that charges, wireless transmission chip that charges includes little the control unit, Static Random Access Memory (SRAM), the IO interface, and power drive or management module. The IO interface is used for connecting the micro control unit and the static random access memory with the off-chip storage unit, and the micro control unit controls the power supply driving or management module to output electric energy. Through the structure, the utility model discloses can reach and reduce the chip cost, reduce the chip volume, improve the purpose that the user used the flexibility.

Description

Wireless charging transmitting chip

Technical Field

The application relates to the field of digital power supplies, in particular to a wireless charging transmitting chip.

Background

The wireless charging transmitting chip can change direct current into alternating current, so that energy is transmitted between the transmitting device and the receiving device in a wireless mode, and the constraint of a wire harness is eliminated. The existing wireless charging transmitting chip is configured as shown in fig. 1, a storage unit 13 is provided in the existing wireless charging transmitting chip 1 for storing function codes for implementing functions such as power control, foreign object detection, and exception handling for a long time, a static random access memory 12 is further provided for temporarily storing all the codes in the storage unit 13, a micro control unit 15 of the wireless charging transmitting chip 1 acquires the codes from the static random access memory 12 and executes the codes and stores operation data in the static random access memory 12, and parameters such as frequency, duty ratio, and voltage of a power driving or management module 16 are controlled by reading the operation data stored in the static random access memory 12.

In the existing scheme, the static random access memory 12 needs to store complete function codes and operation data of a program, the capacity requirement is high, the cost of a memory device with larger capacity is higher, the memory unit 13 needs to integrate related particles on a high-voltage power supply process, the cost of a plate making mask needs to be increased, and meanwhile, the memory unit 13 needs to set an IP and also needs to pay, so that the chip cost is further increased, and the area of a wireless charging transmitting chip is increased, and the cost is increased.

Therefore, there is a need to provide a wireless charging transmitting chip to solve the above-mentioned technical problems of high cost and large area of the chip.

SUMMERY OF THE UTILITY MODEL

The application provides a wireless transmission chip that charges can reach the purpose that reduces chip cost, reduces the chip volume.

In order to solve the technical problem, the application adopts a technical scheme that: the utility model provides a wireless transmitting chip that charges, wireless transmitting chip that charges includes little the control unit, Static Random Access Memory (SRAM), IO interface and power drive or management module, the IO interface be used for with little the control unit, Static Random Access Memory (SRAM) is connected with off-chip memory cell, little the control unit control power drive or management module carry out electric energy output.

Preferably, the wireless charging transmitting chip further comprises a transmission bus, and the transmission bus is used for connecting the IO interface, the micro control unit and the static random access memory.

Preferably, the micro control unit of the wireless charging transmitting chip is connected with the IO interface through the transmission bus, and introduces and executes an instruction code from the off-chip storage unit at a preset frequency in real time, where the instruction code is a function code of the wireless charging transmitting chip for foreign object detection, power calculation, protocol communication, and abnormality monitoring.

Preferably, the static random access memory stores operation data of the instruction codes.

Preferably, the off-chip storage unit is a FLASH memory.

Preferably, the IO interface is a high-speed SPI interface that matches the off-chip storage unit.

Preferably, the high-speed SPI interface transmits data using four wires.

Preferably, the transmission bus is a high performance bus AHB.

Preferably, the preset frequency is a preset integer multiple of the clock frequency of the micro control unit.

The beneficial effect of this application is:

the utility model discloses a wireless transmission chip that charges passes through the IO interface will little the control unit is connected with the off-chip memory cell, has reduced NVM memory cell's setting in chip inside, reduces the demand of technology to integrated memory cell, and then has reduced chip area, has reduced the chip cost.

Furthermore, the microprocessor is connected with the IO interface through the transmission bus, a currently executed code is imported from the off-chip storage unit in real time at a preset frequency, the storage space of the static random access memory is reduced, the micro control unit is connected with the static random access memory through the transmission bus, and the static random access memory is only used for storing a data result of program operation, so that the chip area is further reduced, and the chip cost is reduced.

Furthermore, the off-chip storage unit can store code data when power failure occurs to the FLASH FLASH, and is high in reliability, mature in process and easy for batch production.

Furthermore, the high-speed SPI interface adopts four-wire transmission data chip program codes, and the transient response of the system is stronger.

Drawings

Fig. 1 is a schematic structural diagram of a wireless charging transmitting chip provided in the prior art;

fig. 2 is a schematic structural diagram of a wireless charging transmitting chip according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a wireless charging transmitting chip according to an embodiment of the present invention.

The utility model provides a wireless transmission chip 1 that charges, including little the control unit 15, IO interface 11, transmission bus 14, power drive or management module 16.

The micro control unit 15 is a miniaturized central processing unit, and is used for implementing functions such as power control, foreign object detection, exception handling, protocol communication and the like of the wireless charging transmitting chip, the micro control unit 15 communicates with the off-chip storage unit 13 through the IO interface 11, and executes software code instructions for implementing functions such as power control, foreign object detection, exception handling, protocol communication and the like in real time from the off-chip storage unit 13.

Furthermore, the IO interface 11 is connected with the micro control unit 15 through a transmission bus 14, the IO interface 11 is a high-speed SPI interface matched with the off-chip storage unit 13, four lines are used for transmitting data, the SPI interface is a high-speed, full-duplex, synchronous communication bus, and only four lines need to be occupied on the pins of the wireless charging transmitting chip 1, thereby saving the pins of the chip, and simultaneously saving space on the layout of the PCB, which provides convenience, the four lines of the SPI interface include a data output SPI _ SO, a data input SPI _ SI, a clock SPI _ SCLK, and a chip selection SPI _ CS, wherein the SPI _ SO outputs data from the wireless charging transmitting chip 1; the SPI _ SI inputs data to the wireless charging transmitting chip 1; the SPI _ SCLK obtains a clock signal, the micro control unit 15 is connected with the IO interface 11 through the transmission bus 14, the instruction code is imported from the off-chip storage unit 13 in real time and executed at a preset frequency, in the embodiment, the preset frequency is a preset integral multiple of the clock frequency of the code executed by the micro control unit 15, and the preset integer can be set between 3-10 times of the clock frequency of the micro control unit 15 according to the requirements of code amount and response speed. The transmission bus 14 is a high performance bus AHB, and the transmission bus 14 makes the structure of the whole wireless charging transmitting chip 1 clear, and enhances the universality of the wireless charging transmitting chip 1 and the portability of functional modules in the wireless charging transmitting chip 1.

Instruction codes are burnt into the off-chip storage unit 13, after the wireless charging transmitting chip 1 works, the micro control unit 15 reads the codes from the off-chip storage unit 13 through the IO interface 11 at a preset frequency and executes the codes, and controls the power supply driving or management module 16 to output pulse frequency, duty ratio, voltage and the like according to an execution result.

In order to ensure stability and reliability of the micro control unit 15 for reading codes and executing results, the wireless charging transmitting chip 1 may further include a static random access memory 12, in this embodiment, the static random access memory 12 is a static random access memory SRAM for temporarily storing a part of instruction codes and operation data for executing the instruction codes. The sram 12 is connected to the IO interface 11 via a transmission bus 14, and the mcu 15 is connected to the sram 13 via the transmission bus 14.

The utility model discloses a wireless transmission chip that charges passes through the IO interface will little the control unit MCU is connected with the off-chip memory cell, has reduced the setting of memory cell NVM in chip inside, reduces the demand of technology to integrated memory cell NVM, and then has reduced chip area, has reduced the chip cost.

Furthermore, the internal storage SRAM is connected with the IO interface through the transmission bus, and program codes are executed in real time from the off-chip storage unit at a preset frequency, so that the storage space of the internal storage SRAM is reduced, the chip area is further reduced, and the chip cost is reduced.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims

1. The utility model provides a wireless transmission chip that charges, its characterized in that, wireless transmission chip that charges includes little the control unit, static random access memory, IO interface, and power drive or management module, the IO interface be used for with little the control unit, static random access memory is connected with off-chip memory cell, little the control unit control power drive or management module carry out electric energy output.

2. The wireless charging transmitting chip according to claim 1, further comprising a transmission bus, wherein the transmission bus is used for connecting the IO interface with the micro control unit and the static random access memory.

3. The wireless charging transmitting chip according to claim 2, wherein the micro control unit of the wireless charging transmitting chip is connected to the IO interface through the transmission bus, and the instruction codes for foreign object detection, power calculation, protocol communication, and abnormality monitoring are imported from the off-chip storage unit at a preset frequency in real time and executed.

4. The wireless charging transmitting chip of claim 3, wherein the static random access memory stores operation data of the instruction codes.

5. The wireless charging transmitting chip of claim 1, wherein the off-chip storage unit is a FLASH memory.

6. The wireless charging and transmitting chip of claim 1, wherein the IO interface is a high-speed SPI interface matching the off-chip storage unit.

7. The wireless charging transmit chip of claim 6, wherein the high-speed SPI interface transmits data using four wires.

8. The wireless charging and transmitting chip of claim 2, wherein the transmission bus is a high performance bus AHB.

9. The wireless charging transmit chip of claim 3, wherein the predetermined frequency is a predetermined integer multiple of the clock frequency of the MCU.