CN212568982U

CN212568982U - Circuit capable of resisting pulse group

Info

Publication number: CN212568982U
Application number: CN202020900422.5U
Authority: CN
Inventors: 张汉一; 张路平
Original assignee: Shenzhen Yijia Zhilian Technology Co ltd
Current assignee: Shenzhen Yijia Zhilian Technology Co ltd
Priority date: 2020-05-26
Filing date: 2020-05-26
Publication date: 2021-02-19
Anticipated expiration: 2030-05-26

Abstract

The utility model belongs to the technical field of the industrial control mainboard, especially, a circuit of anti pulse burst, to the current USB port that has used USB HUB to come out, the problem of the general deviation of EFT test, the scheme is now proposed, and it includes fuse FU1, fuse FU 1's one end is connected with electric capacity C11, electric capacity CE2 and electric capacity CE 8's one end, electric capacity C11, electric capacity CE2 and electric capacity CE 8's the equal ground connection of the other end, fuse FU 1's one end still is connected with USB's first interface and second interface, and USB's third interface connection has the third pin of resistor row RN1, and resistor row RN 1's second pin and USB's fifth interface connection, resistor row RN 1's fourth pin and first pin are connected with USB1_ HUB _ DN and USB1_ HUB _ DP respectively, the utility model discloses anti pulse burst, stability is good, and the circuit is simple, practices thrift the cost.

Description

Circuit capable of resisting pulse group

Technical Field

The utility model relates to an industry control mainboard technical field especially relates to a but anti pulse burst's circuit.

Background

The electric fast pulse test has typical significance for testing the immunity of equipment, and the immunity of a circuit in a wider frequency range can be tested because the rising edge of the electric fast pulse test waveform is very steep and therefore contains abundant high-frequency harmonic components. In addition, since the test pulse is a pulse train lasting for a certain period of time, it has an accumulative effect on the interference of the circuit, and most circuits have an integrating circuit at the input end for the purpose of transient interference resistance, and the circuit has a good effect of suppressing a single pulse, but cannot effectively suppress a train of pulses.

The electrically fast pulse train consists of successive pulse trains with an interval of 300ms, each pulse train lasting 15ms and consisting of several nonpolar individual pulse waveforms, the rising edge of the individual pulse being 5ns, the duration being 50ns and the repetition frequency being 5K. Typical EFT burst interference is that the peak voltage of a single pulse of the EFT signal can be as high as 4kV with a rising edge of 5 ns. The device has the characteristics of burst, high voltage, wide frequency and the like. When the pulse is directly conducted into the power supply of the equipment through the power line, the pulse group in a string causes overlarge noise voltage on the power line of the circuit, so that the computer equipment is lost, and the computer is seriously even restarted directly.

In the prior art, for the USB port using USB HUB, the EFT test is generally biased, so we propose a circuit capable of resisting burst to solve the above problem.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the USB port that has used the USB HUB to come out, the shortcoming of the general deviation of EFT test, and the circuit of a kind of anti pulse crowd that proposes.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a circuit capable of resisting pulse groups comprises a fuse FU1, one end of the fuse FU1 is connected with one end of a capacitor C11, a capacitor CE2 and a capacitor CE8, the other ends of the capacitor C11, the capacitor CE2 and the capacitor CE8 are all grounded, one end of the fuse FU1 is further connected with a first interface and a second interface of the USB, the third interface of the USB is connected with a third pin of the resistor row RN1, the second pin of the resistor row RN1 is connected with a fifth interface of the USB, the fourth pin and the first pin of the resistor bank RN1 are respectively connected with USB1_ HUB _ DN and USB1_ HUB _ DP, the fourth interface and the sixth interface of the USB are respectively connected with the first pin and the fourth pin of the resistor bank RN2, the second pin and the third pin of the resistor bank RN2 are respectively connected with USB2_ HUB _ DN and USB2_ HUB _ DP, the seventh interface, the eighth interface and the tenth interface of the USB are all grounded, and the other end of the fuse FU1 is connected with a power supply.

Preferably, the POWER supply comprises an input terminal DC _ IN, the input terminal DC _ IN is connected with one end of an inductor L1, the other end of the inductor L1 is connected with one end of a capacitor CT1 and 5V _ POWER IN, and the other end of the capacitor CT1 is grounded.

Preferably, the capacitance value of the capacitor CT1 is 100 μ F.

Preferably, the capacitance value of the capacitor CE8 is 560 μ F.

Preferably, the inductance of the inductor L1 is 1.0 μ H.

Compared with the prior art, the utility model has the advantages of:

(1) in the scheme, at the input end of a 5V power supply, in addition to a conventional integrating circuit, an inductor L1 and a high-capacity capacitor CT1 are added for filtering, and a high-capacity capacitor CE8 is additionally added beside a USB port to serve as a water reservoir, so that the problem that the pulse group is over-4 KV can be solved, and the pulse resistance of the USB is obviously improved;

(2) the utility model discloses can resist pulse group, stability is good, and the circuit is simple, practices thrift the cost.

Drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the drawings of the embodiments will be briefly described below, and it is obvious that the drawings in the following description only relate to some embodiments of the present invention, and are not intended to limit the present invention.

Fig. 1 is a circuit diagram of a circuit capable of resisting pulse groups according to the present invention;

fig. 2 is a power input end circuit diagram of a circuit capable of resisting pulse groups according to the present invention.

Detailed Description

The technical solutions in the embodiments will be described clearly and completely with reference to the drawings in the embodiments, and it is obvious that the described embodiments are only a part of the embodiments, but not all embodiments.

The terms "mounted", "connected" and "fixed" in the present invention should be understood in a broad sense, for example, they may be fixedly connected, detachably connected, or integrated; the two components can be connected mechanically or electrically, directly or indirectly through an intermediate medium, or connected internally or in an interaction relationship, and specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Referring to fig. 1-2, a burst robust circuit includes fuse FU1, fuse FU1 having one end connected to one end of capacitor C11, capacitor CE2, and one end of capacitor CE8, capacitor C11, the other ends of the capacitor CE2 and the capacitor CE8 are grounded, one end of the fuse FU1 is further connected with a first interface and a second interface of a USB (universal serial bus), a third interface of the USB is connected with a third pin of a resistor row RN1, a second pin of the resistor row RN1 is connected with a fifth interface of the USB, a fourth pin and a first pin of the resistor row RN1 are connected with a USB1_ HUB _ DN and a USB1_ HUB _ DP respectively, a fourth interface and a sixth interface of the USB are connected with a first pin and a fourth pin of a resistor row RN2 respectively, a second pin and a third pin of the resistor row RN2 are connected with a USB2_ HUB _ DN and a USB2_ HUB _ DP respectively, a seventh interface, an eighth interface and a tenth interface of the USB are grounded, and the other end of the fuse FU1 is connected with a power supply.

IN this embodiment, the POWER supply includes an input terminal DC _ IN, the input terminal DC _ IN is connected to one end of an inductor L1, the other end of the inductor L1 is connected to one end of a capacitor CT1 and 5V _ POWER IN, and the other end of the capacitor CT1 is grounded.

In this embodiment, the capacitance value of the capacitor CT1 is 100 μ F.

In this embodiment, the capacitance value of the capacitor CE8 is 560 μ F.

In this embodiment, the inductance of the inductor L1 is 1.0 μ H.

For computers on the market, such as J1800/J1900 platform of X86 platform, because the number of USB ports from the platform chip is only 4 in total, and there are too many USB ports to be used in life, this results in having to be expanded through HUB, but the motherboards of the J1900 platform friends who are common on the market all use USB signals to expand multiple USB ports through HUB, but these USB ports from HUB have extremely poor effect during burst experiments, and some-0.5 KV cannot be used, which results in USB devices lost when customers use USB ports, and have to be unplugged and plugged again many times, and some manufacturers use PCIE to convert USB for this problem, although this solution can solve this problem, but the cost is expensive.

In the following, a USB scanning gun is taken as an example, and the scanning gun is lost in each experiment.

After the rectification, the scanning gun is used normally every time.

The rectification method comprises the following steps: an inductor L1(1.0uH) and a 100uF/25V capacitor CT1 are connected in series at an input end of a power supply DC to 5V USB for supplying power for providing a clean power supply for the input end, an inductor L1 and a large-capacity capacitor CT1 are added for filtering besides a conventional integrating circuit, and a large-capacity capacitor CE8 is additionally added beside a USB port for serving as a water reservoir, so that the problem that a pulse group is over + -4KV, the pulse resistance of the USB is obviously improved can be solved, and the problem that the 5V is very stable in an EFT test is found through measurement, a USB scanning gun is lost before the CE8 is not added, and the USB scanning gun is not lost after the CE8 is added and the + -4KV is added.

The present invention has been described in detail so far. Some details which are well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

The above descriptions are only preferred embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the scope of the present invention, and the technical solutions and the utility model concepts of the present invention are equivalent to, replaced or changed.

Claims

1. A circuit capable of resisting pulse groups comprises a fuse FU1, and is characterized in that one end of the fuse FU1 is connected with one ends of a capacitor C11, a capacitor CE2 and a capacitor CE8, the other ends of the capacitor C11, the capacitor CE2 and the capacitor CE8 are all grounded, one end of the fuse FU1 is further connected with a first interface and a second interface of a USB, a third interface of the USB is connected with a third pin of a resistor row RN1, a second pin of the resistor row RN1 is connected with a fifth interface of the USB, a fourth pin and a first pin of the resistor row RN1 are respectively connected with a USB1_ B _ DN and a USB1_ HUB _ DP, the fourth interface and the sixth interface of the USB are respectively connected with a first pin and a fourth pin of the resistor row RN2, the second pin and the third pin of the resistor row RN2 are respectively connected with a USB2_ HUB _ DN and a USB2_ HUB _ DP, and the eighth interface, the seventh interface and the tenth interface of the USB are all grounded, the other end of the fuse FU1 is connected to a power supply.

2. The pulse train immunity circuit of claim 1, wherein the POWER supply comprises an input terminal DC _ IN, the input terminal DC _ IN is connected to one terminal of an inductor L1, the other terminal of the inductor L1 is connected to one terminal of a capacitor CT1 and 5V _ POWER IN, and the other terminal of the capacitor CT1 is grounded.

3. The pulse burst immunity circuit of claim 2, wherein said capacitor CT1 has a capacitance of 100 μ F.

4. The pulse burst immunity circuit of claim 1, wherein said capacitor CE8 has a capacitance of 560 μ F.

5. The pulse burst immunity circuit of claim 2, wherein the inductance of said inductor L1 is 1.0 μ H.