CN113794474B

CN113794474B - Test method for evaluating DAC anti-interference performance based on IBIS model

Info

Publication number: CN113794474B
Application number: CN202110939571.1A
Authority: CN
Inventors: 刘红侠; 郭丹
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2023-06-06
Anticipated expiration: 2041-08-16
Also published as: CN113794474A

Abstract

According to the testing method for evaluating the DAC anti-interference performance based on the IBIS model, the IBIS circuit model of the digital-to-analog conversion DAC chip is obtained; based on the DAC chip IBIS circuit model, a test circuit for testing the DAC chip in two working modes is established; when the DAC chips are respectively tested by the test circuits in the two working modes, test results of adding EFT signal interference and test results of not adding EFT signal interference are obtained; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the anti-EFT capability of the DAC chip with the model of AD5761R/AD5721R, is beneficial to quickly finding out the chip meeting the protection requirement, and further reduces the design cost and the development period.

Description

Test method for evaluating DAC anti-interference performance based on IBIS model

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a testing method for evaluating DAC anti-interference performance based on an IBIS model.

Background

In the field of power chip reliability, along with the improvement of the working frequency and the integration level of an integrated circuit, the thinning of an insulating medium layer and a shielding medium layer, the shortening of the distance between connecting lines and the lowering of breakdown voltage and working voltage, the electromagnetic anti-interference capability of the power chip can be continuously reduced. The damage or failure of transistors in an integrated circuit caused by transient disturbances such as electrostatic discharge (ESD) and electric fast transient pulse burst (EFT) accounts for about 20% -50% of the total failure proportion of the integrated circuit, and the safe and stable operation of a power chip is seriously affected. With the use of next generation process technologies, the feature size is further reduced, the current density is larger, the voltage tolerance is lower, and these factors make the stability problem of the integrated circuit more serious, so the requirements on the effectiveness and stability of the protection circuit are higher and higher.

In order to obtain a high-reliability device with transient interference such as electrostatic discharge (ESD) and electric fast transient pulse train (EFT), the performance of the device in a normal working area is researched, a very mature simulation tool can be utilized for performing computer aided design, very accurate circuit models are established for devices with different geometric shapes and sizes and different processes, and the models can be used for designing and simulating a core functional circuit.

For example, xiamen high-speed chip limited company in patent literature "a high-speed DAC test system and method" (publication No. CN201710182502.4, application date 2017-03-24) proposes a test method of a high-speed DAC, which generates DP-QPSK data stream by a simulation module, inputs the DP-QPSK data stream into a pattern generator and an arbitrary waveform generator to output a low-speed digital signal and a clock signal, converts the low-speed digital signal into a high-speed digital signal, and converts the high-speed digital signal into a high-speed analog signal according to the clock signal; and then the high-speed analog signal is sent to a simulation module, DP-QPSK modulation is carried out to obtain a DP-QPSK modulated optical signal, signal decoding and recovery are carried out through an optical receiver, the recovered signal is compared with the DP-QPSK data stream, the error rate and the error vector magnitude EVM of the signal are calculated, and the performance of the high-speed DAC is tested and evaluated.

However, since the method cannot purposefully distinguish between the interference and the electrical fast transient burst capability of the DAC under anti-interference during the test, the results of testing and evaluating the high-speed DAC are disadvantageous for quickly finding out the chip satisfying the protection requirement, reducing the design cost and development cycle. Meanwhile, due to the lack of commercial EFT circuit-level models, most protection circuits and device design processes rely mainly on experience and experimental test research. For most companies, the design process of the protection circuit is an attempt and failure process: a series of candidate circuits and device structures are first designed, then fabricated and tested using a new process, and then evaluated for their protective performance. Combining and trying different dimensions and different process variations eventually finds a circuit that meets the protection requirements, which undoubtedly affects the design costs and development cycle.

One aspect of being less desirable is that existing protection circuits cannot be directly transplanted into next generation processes and need to be remanufactured and retested. Moreover, as the pads shrink with process size, the size of the guard circuit has to be further reduced, resulting in further performance degradation, and more money and time will be used for I/O port re-development design.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a test method for evaluating DAC anti-interference performance based on an IBIS model. The technical problems to be solved by the invention are realized by the following technical scheme:

the test method for evaluating DAC anti-interference performance based on the IBIS model provided by the invention comprises the following steps:

obtaining an IBIS circuit model of a digital-to-analog conversion DAC chip;

based on a DAC chip IBIS circuit model, a test circuit for testing the DAC chip in two working modes is established;

the test circuits in the two working modes are a test circuit in an internal reference voltage source working mode and a test circuit in an external voltage source working mode;

when the DAC chips are respectively tested by the test circuits in the two working modes, test results of adding EFT signal interference and test results of not adding EFT signal interference are obtained;

and comparing the test result of the EFT signal interference with the test result of the EFT signal interference not to obtain the anti-interference performance of the DAC chip.

Optionally, the test circuit of the internal reference voltage source working mode includes: the circuit comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power supply ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with the first capacitor C1 to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, a seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with a power supply ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, a tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin 12 is connected with a voltage generator with an amplitude of 3v, a period of 60ns, a duty cycle of 50% of the DAC chip IBIS circuit model is a thirteenth pulse generator, a duty cycle of the thirteenth pulse generator is a duty cycle of the DAC chip is 50%, a duty cycle of the DAC chip is 14 is a thirteenth pulse generator, and a duty cycle of the input of the DAC chip is 50% of the input clock 14 is a pulse carrier is 50, and a thirteenth pulse duty cycle of the phase of the DAC chip is 50.

Optionally, the test circuit of the internal reference voltage source working mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R3, the other end of R3 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with the first capacitor C1 to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R2, the other end of R2 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group EFT generator which are mutually connected in series and have the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator and the electric fast transient pulse group EFT generator which are mutually connected in series and have the amplitude of 2v, the period of 50ns and the duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with the clock signal pulse generator and the electric fast transient pulse group EFT generator which are mutually connected in series and have the amplitude of 1v, the period of 40ns and the duty ratio of 50%, the variation range of the amplitude of the electric fast transient pulse group EFT generator is 1kv-4kv, the initial value is 1kv, the final value is 4kv, and the step size is 1kv.

Optionally, the test circuit of the external voltage source working mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure normal power supply of a circuit in an external voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and is used for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

Optionally, the test circuit of the external voltage source working mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure normal power supply of a circuit in an external voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the thirteenth pin 12 is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50% and an electric fast transient pulse group EFT generator which are mutually connected in series, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with a clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50% and the electric fast transient pulse group EFT generator which are mutually connected in series, and the change range of the amplitude of the electric fast transient pulse group EFT generator is set to be 1kv-4kv, the initial value is 1kv, the final value is 4kv, the step size was 1kv.

According to the test method for evaluating the DAC anti-interference performance based on the IBIS model, the IBIS circuit model of the digital-to-analog conversion DAC chip is obtained; based on a DAC chip IBIS circuit model, a test circuit for testing the DAC chip in two working modes is established; when the DAC chips are respectively tested by the test circuits in the two working modes, test results of adding EFT signal interference and test results of not adding EFT signal interference are obtained; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the capability of the DAC chip with the model of AD5761R/AD5721R for resisting the electric fast transient pulse group, is favorable for quickly finding out the chip meeting the protection requirement, and further reduces the design cost and the development period.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a flow chart of a test method for evaluating DAC immunity based on an IBIS model provided by an embodiment of the invention;

FIG. 2 is a circuit model diagram of the present invention in an internal reference voltage source mode of operation based on an IBIS model of a digital-to-analog DAC chip, model AD5761R/AD 5721R;

FIG. 3 is a schematic circuit diagram of the present invention with EFT interference applied to the signal input in the internal reference voltage source mode of operation;

FIG. 4 is a circuit model diagram of the present invention in an external voltage source mode of operation based on an IBIS model of a digital-to-analog DAC chip, model AD5761R/AD 5721R;

FIG. 5 is a schematic circuit diagram of the present invention with EFT interference applied to the signal input in an external voltage source mode of operation;

FIG. 6 is a waveform diagram of the output of the serial data output pin in the internal reference voltage source mode of operation of the present invention;

FIG. 7 is a waveform diagram of the output of the serial data output pin in the external voltage source mode of operation of the present invention;

FIG. 8 is a waveform diagram of serial input data without EFT interference and with non-uniform period and amplitude in accordance with the present invention;

FIG. 9 is a waveform diagram of the serial data input when EFT interference is applied to the signal input in the internal reference voltage source mode of operation of the present invention;

FIG. 10 is a waveform diagram of the serial data output when EFT interference is applied to the signal input in the internal reference voltage source mode of operation of the present invention;

FIG. 11 is a waveform diagram of a serial data input when EFT interference is applied to the signal input in an external voltage source mode of operation according to the present invention;

FIG. 12 is a waveform diagram of the serial data output when EFT interference is applied to the signal input in the external voltage source operating mode according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Example 1

As shown in fig. 1, the test method for evaluating the anti-interference performance of the DAC based on the IBIS model provided by the invention comprises the following steps:

s1, acquiring a digital-to-analog conversion DAC chip IBIS circuit model;

s2, based on a DAC chip IBIS circuit model, a test circuit for testing the DAC chip in two working modes is established;

s3, when the DAC chips are respectively tested by the test circuits in the two working modes, test results with the added EFT signal interference and test results without the added EFT signal interference are obtained;

s4, comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip.

It will be appreciated that in the IBIS circuit model, an IBIS model of a digital-to-analog conversion DAC chip with the model of AD5761R/AD5721R is tuned into an ansys internal reference voltage source working mode, and the power supply mode of each port of the IBIS model is set as an internal power supply internal. The ports of the IBIS model are set to an external power supply mode external in an external voltage source operation mode.

According to the test method for evaluating the DAC anti-interference performance based on the IBIS model, the IBIS circuit model of the digital-to-analog conversion DAC chip is obtained; based on a DAC chip IBIS circuit model, a test circuit for testing the DAC chip in two working modes is established; when the DAC chip is tested by the test circuit in two working modes, a test result with EFT signal interference and a test result without EFT signal interference are obtained; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the capability of the DAC chip with the model of AD5761R/AD5721R for resisting the electric fast transient pulse group, is favorable for quickly finding out the chip meeting the protection requirement, and further reduces the design cost and the development period.

Example two

As an alternative embodiment of the present invention, as shown in fig. 2, the test circuit for the internal reference voltage source operation mode includes: the circuit comprises a DAC chip IBIS circuit model, a resistor R2 and a resistor R3, a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power supply ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with the first capacitor C1 to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, a seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with a power supply ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, a tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin 12 is connected with a voltage generator with an amplitude of 3v, a period of 60ns, a duty cycle of 50% of the DAC chip IBIS circuit model is a thirteenth pulse generator, a duty cycle of the thirteenth pulse generator is a duty cycle of the DAC chip is 50%, a duty cycle of the DAC chip is 14 is a thirteenth pulse generator, and a duty cycle of the input of the DAC chip is 50% of the input clock 14 is a pulse carrier is 50, and a thirteenth pulse duty cycle of the phase of the DAC chip is 50.

It will be appreciated that the test circuit for the internal reference voltage source mode of operation may be built as follows:

step 1, an IBIS model with the model of AD5761R/AD5721R digital-to-analog conversion DAC chip is called into ansys, and the power supply mode of each port of the model is set as internal power supply internal.

And 2, the pin 1 is a low-level effective alarm interface, and the pin is externally connected with a 10 omega resistor in the connection mode of the circuit.

And 3, the pin 4 is an internal reference voltage output and external voltage input interface, and in the connection mode of the circuit, the pin is externally connected with a 10nF capacitor so as to ensure that noise in the circuit is minimum in an internal reference voltage source working mode.

And 4, the pin 7 is an analog output voltage interface of the DAC, and the pin is externally connected with a resistor of 10Ω in the connection mode of the circuit.

And 5, the pin 10 is a serial data output interface, and is externally connected with a resistor of 10Ω in the connection mode of the circuit.

Step 6, the pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%.

And 7, the pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%.

Step 8, the pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

Example III

As an alternative embodiment of the present invention, as shown in fig. 3, the test circuit for the internal reference voltage source operation mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R3, the other end of R3 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with the first capacitor C1 to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R2, the other end of R2 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are mutually connected in series, wherein the amplitude is 3v, the period is 60ns, the duty ratio is 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are mutually connected in series, the amplitude is 2v, the period is 50ns, the duty ratio is 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with a clock signal pulse generator and an electric fast transient pulse group (EFT) generator which are mutually connected in series, the amplitude is 1v, the period is 40ns, the duty ratio is 50%, and setting the amplitude of the electric fast transient pulse group (EFT) generator to be 1kv-4kv, the initial value to be 1kv, the final value to be 4kv and the step length to be 1kv.

It can be understood that the test circuit of the EFT disturbance circuit added to the signal input end in the internal reference voltage source operation mode can be built according to the following steps:

step 1, adding an interference excitation signal to an input signal port based on a schematic diagram of FIG. 2, wherein the schematic diagram has no EFT interference at a signal input end in an internal reference voltage source working mode;

step 2, the pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, wherein the amplitude is 3v, the period is 60ns, and the duty ratio is 50%.

Step 3, the pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, wherein the amplitude is 2v, the period is 50ns, and the duty ratio is 50%.

Step 4, pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, wherein the amplitude is 1v, the period is 40ns, and the duty ratio is 50%.

Step 5, setting the variation range of the amplitude to be 1kv-4kv, the initial value start to be 1kv, the final value stop to be 4kv and the step length step to be 1kv for the simulation of the electric fast transient pulse group (EFT) generator.

According to the embodiment, based on an IBIS model with the model of AD5761R/AD5721R digital-to-analog conversion DAC chip, a circuit model under an internal reference voltage source working mode is built, EFT interference signals are overlapped on an input port of signals, and finally output results under the two conditions of existence/non-existence of the EFT interference signals are compared and observed, so that the capability of the DAC chip in the internal reference voltage source working mode in resisting electric fast transient pulse groups is evaluated, chips meeting protection requirements can be found quickly, and design cost and development period are reduced.

Example IV

As an alternative embodiment of the present invention, as shown in fig. 4, the test circuit for the external voltage source operation mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure normal power supply of a circuit in an external voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and is used for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

It can be appreciated that the test circuit for the external voltage source operation mode can be built as follows:

step 1, an IBIS model with the model of AD5761R/AD5721R digital-to-analog conversion DAC chip is called into ansys, and the power supply modes of all ports of the model are set to be external power supply.

And 3, the pin 4 is an internal reference voltage output and external voltage input interface, and is externally connected with a direct-current voltage source with the amplitude of 2.5v in the connection mode of the circuit so as to ensure that the circuit is normally powered in an external voltage source working mode.

Example five

As an alternative embodiment of the present invention, as shown in fig. 5, the test circuit for the external voltage source operation mode includes: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with power ground, the fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure normal power supply of a circuit in an external voltage source working mode, the seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with power ground, the tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference performance curve, the twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50% and an electric fast transient pulse group (EFT) generator which are mutually connected in series, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with a clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50% and an electric fast transient pulse group (EFT) generator which are mutually connected in series, and the variation range of the amplitude of the electric fast transient pulse group (EFT) generator is 1kv-4kv, the initial value is 1kv, the final value is 4kv, and the step size is 1kv.

It can be understood that the test circuit of the EFT interference circuit externally added to the signal input end in the external voltage source working mode can be built according to the following steps:

step 1, adding an interference excitation signal to an input signal port based on a schematic diagram of FIG. 4 without EFT interference at a signal input end in an external voltage source working mode;

According to the embodiment, based on an IBIS model with the model of AD5761R/AD5721R digital-to-analog conversion DAC chip, a circuit model under an external voltage source working mode is built, EFT interference signals are overlapped on an input port of signals, and finally output results of the DAC chip under the two conditions of existence/non-existence of the EFT interference signals are compared and observed, so that the capability of resisting electric fast transient pulse groups of the DAC chip under the external voltage source working mode is evaluated, chips meeting protection requirements can be found quickly, and design cost and development period are reduced.

The interference performance parameters tested by the testing method provided by the invention are presented by simulation tests, and the beneficial effects of the invention are illustrated by comparison analysis.

Simulation 1, effect diagram is shown in fig. 6, and fig. 6 is an output waveform of the serial data output pin in the internal reference voltage source operation mode.

Simulation 2, the effect diagram is shown in fig. 7, and fig. 7 is an output waveform of the serial data output pin in the external voltage source operation mode.

Simulation 3, effect diagram is shown in fig. 8, fig. 8 is a waveform diagram of serial input data when EFT interference is not generated and period and amplitude are not consistent.

Simulation 4, effect diagram is shown in fig. 9, fig. 9 is waveform of serial data input end when EFT interference is applied to signal input end in internal reference voltage source operation mode.

Simulation 5, effect diagram is shown in fig. 10, fig. 10 is waveform of serial data output end when EFT interference is applied to signal input end in internal reference voltage source operation mode.

Simulation 6, the effect diagram is shown in fig. 11, and fig. 11 is a waveform of the serial data input end when EFT interference is applied to the signal input end in the external voltage source operation mode.

Simulation 7, the effect diagram is shown in fig. 12, and fig. 12 is a waveform of the serial data output end when EFT interference is applied to the signal input end in the external voltage source operation mode.

According to the effect diagram, the input and output conditions of the DAC in the power supply working mode of the internal reference voltage source are compared, wherein the input and output conditions are shown in fig. 8 and 9, and the output and comparison diagrams are shown in fig. 6 and 10. It can be seen from the comparison that the input signal in the circuit is affected, but the output signal is not affected, in the case of adding the EFT interference signal to the input terminal, which indicates that the circuit has good EFT interference resistance in the internal reference voltage source power supply mode.

The DAC is compared with the input/output conditions with/without EFT interference in the external voltage source power supply operation mode, wherein the input comparison chart is shown in fig. 8 and 11, and the output comparison chart is shown in fig. 7 and 12. In the comparison chart, under the condition that the EFT interference signal is added to the input end, both the input signal and the output signal in the circuit are affected, which indicates that the circuit has poor EFT interference resistance in an external voltage source power supply mode.

Therefore, the invention builds the circuit model under two working modes of the internal reference voltage source and the external voltage source based on the IBIS model of the DAC chip with the model of AD5761R/AD5721R, then superimposes the EFT interference signal on the input port of the signal, finally realizes the performance evaluation of the DAC chip on the capability of resisting the electric fast transient pulse group by comparing and observing the output results under the two conditions of existence/nonexistence of the EFT interference signal, is beneficial to finding out the chip meeting the protection requirement rapidly, and further reduces the design cost and the development period.

It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. The test method for evaluating the DAC immunity based on the IBIS model is characterized by comprising the following steps:

obtaining an IBIS circuit model of a digital-to-analog conversion DAC chip;

2. The test method of claim 1, wherein the test circuit of the internal reference voltage source operating mode comprises: the circuit comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor (C1), wherein the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, one end of R3 is connected with the first pin (1), the other end of R3 is connected with power ground, the fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is connected with the first capacitor (C1) so as to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, the seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R2, the other end of R2 is connected with power ground, the tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin (10) is connected with a display instrument and used for displaying an anti-interference performance curve, the twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is a serial data input interface, the seventh pin (12) is connected with the DAC chip IBIS circuit model is 60, the duty cycle is a pulse carrier (14 ns), the duty cycle is 50, the input clock is 50ns of the DAC chip is 50%, the pulse carrier is 50% of the pulse carrier is 50, and the pulse carrier is 50, the pulse carrier 14 is 50, and the pulse carrier is 50% of the pulse carrier is 50, and the pulse carrier is 50, A clock signal pulse generator with a duty cycle of 50%.

3. The test method of claim 1, wherein the test circuit of the internal reference voltage source operating mode comprises: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin (1) is connected with one end of R3, the other end of R3 is connected with power ground, the fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is connected with the first capacitor (C1) to ensure that noise in a circuit is minimum in an internal reference voltage source working mode, the seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R2, the other end of R2 is connected with power ground, the tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin (10) is connected with a display instrument and is used for displaying an anti-interference performance curve, the twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) are 3v, the period of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) are 60ns, the duty ratio of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are 50%, the thirteenth pin (13) of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the amplitude of the thirteenth pin (13) is externally connected with the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) are 2v, the duty ratio of the voltage digital signal pulse generator is 50%, a fourteenth pin (14) of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin (14) is externally connected with a clock signal pulse generator and an electric fast transient pulse group (EFT) generator which are mutually connected in series, wherein the amplitude is 1kv, the period is 40ns, the duty ratio is 50%, the amplitude variation range of the electric fast transient pulse group (EFT) generator is set to be 1kv-4kv, the initial value is 1kv, the final value is 4kv, and the step length is 1kv.

4. The test method of claim 1, wherein the test circuit of the external voltage source operation mode comprises: the digital pulse synchronous signal generating circuit comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, one end of the R4 is connected with the first pin (1), the other end of the R4 is connected with power ground, a fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is externally connected with the direct-current voltage source so as to ensure normal power supply of the circuit in an external voltage source working mode, a seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, one end of the seventh pin (7) is connected with the R1, the other end of the R1 is connected with power ground, a tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, a tenth pin (10) is connected with a display instrument and used for displaying anti-interference performance curves, a twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin (12) is connected with a serial data input interface, a thirteenth pin (12) is connected with a duty cycle of 3 ns, a duty cycle of 60ns, a thirteen (13) is a duty cycle of a digital signal generator, a duty cycle of a pulse generator is 50% of an external pulse synchronous signal is 50ns (14 ns), and a duty cycle of the DAC chip is 50% of the DAC chip is 50, and a duty cycle is 50% of a pulse synchronous signal is generated by the DAC chip, and a pulse generator is 50, and a duty cycle is 50 A clock signal pulse generator with a duty cycle of 50%.

5. The test method of claim 1, wherein the test circuit of the external voltage source operation mode comprises: the first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin (1) is connected with one end of R4, the other end of R4 is connected with power ground, the fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is externally connected with the direct-current voltage source to ensure normal power supply of the circuit in an external voltage source working mode, the seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R1, the other end of R1 is connected with power ground, the tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin (10) is connected with a display instrument and is used for displaying an anti-interference performance curve, the twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, the thirteenth pin (13) of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin (13) is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50% and an electric fast transient pulse group (EFT) generator which are mutually connected in series, the fourteenth pin (14) of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin (14) is externally connected with a voltage digital signal pulse generator with the amplitude of 1v, A clock signal pulse generator with a period of 40ns and a duty cycle of 50% and an electric fast transient pulse group (EFT) generator, and setting the amplitude of the electric fast transient pulse group (EFT) generator to have a variation range of 1kv-4kv, an initial value of 1kv, a final value of 4kv and a step length of 1kv.