CN212515421U - Measurement and control mainboard - Google Patents
Measurement and control mainboard Download PDFInfo
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- CN212515421U CN212515421U CN202021206421.7U CN202021206421U CN212515421U CN 212515421 U CN212515421 U CN 212515421U CN 202021206421 U CN202021206421 U CN 202021206421U CN 212515421 U CN212515421 U CN 212515421U
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Abstract
The utility model discloses a observe and control mainboard, include: the main board body is in communication connection with a computer host, an FPGA chip is arranged on the main board body, and an ADC conversion acquisition chip, a DAC analog-to-digital conversion chip, a multi-path low-noise automatic shimming control DAC chip and a circuit which are connected with the FPGA chip are connected, the FPGA chip is in communication connection with the computer host, the FPGA chip is further connected with a temperature probe, a magnetic field heating module for temperature adjustment, and the nuclear magnetic probe is connected with the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip. The utility model discloses the measurement and control mainboard integrates the height, and is simple high-efficient, low cost, and peripheral accessory is few, and the volume is tiny, and comprehensive properties is good, is fit for quantum computer and uses.
Description
Technical Field
The utility model relates to a quantum computer technical field, in particular to desk-top digital FPGA that observes and controls quantum computer and uses observes and controls mainboard.
Background
Quantum computing is a new equivalent quantum computing technology for chemical measurement, medical scanning imaging, scientific research and teaching, and through the rapid development of the years, the initial analog hardware modulation and hardware demodulation acquisition is converted into the development trend of digital modulation and digital demodulation acquisition and digital control with wider controllable surface. To realize the function of quantum computation, the traditional circuit construction adopts an analog demodulation acquisition circuit, the circuit is more complicated, the hardware volume is huge, the controllability is narrow, the circuit accuracy is low, the stability is poor, the price is high, the assembly is difficult, and the like, which are not beneficial to the assembly and the product batch use of a small-sized desktop quantum computer.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an integrate high, simple high-efficient, low cost, peripheral accessory is few, and the volume is tiny, is fit for the observing and controlling mainboard that quantum computer used.
The utility model provides an above-mentioned technical problem's technical scheme be, provide a observe and control mainboard, include: the mainboard main part, the mainboard main part is connected with the computer mainframe communication, be equipped with the FPGA chip in the mainboard main part, and with ADC conversion collection chip, DAC analog-to-digital conversion chip, the automatic shimming control DAC chip of multichannel low noise and circuit that the FPGA chip is connected, the FPGA chip is connected with the computer mainframe communication, the FPGA chip still is connected with temperature probe, is used for temperature regulation's magnetic field heating module, and passes through ADC conversion collection chip, DAC analog-to-digital conversion chip connect nuclear magnetic probe.
Wherein, observe and control the mainboard and still include: and the Flash memory Flash chip is connected with the FPGA chip.
The main board body is also provided with a multi-channel temperature sensor monitoring input circuit, a multi-channel temperature controller output channel and a multi-channel nuclear magnetic radio frequency transceiving conversion control channel, and the FPGA chip is in communication connection with the temperature probe through the multi-channel temperature sensor monitoring input circuit; the FPGA chip is in communication connection with the magnetic field heating module through the multi-path temperature controller output channel; the FPGA chip is connected with the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip through the multi-channel nuclear magnetic radio frequency transceiving conversion control channel.
And the mainboard main body is also provided with a single clock source circuit which is connected with the FPGA chip.
The main board body is further provided with a USB conversion chip, the FPGA chip is in communication connection with a computer host through the USB conversion chip, and the USB conversion chip utilizes a USB signal bus to realize communication between the FPGA chip and the host.
The channel number and the frequency of the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip are relatively adaptive.
The ADC conversion acquisition chip adopts an 8-bit high-speed ADC conversion chip AD9286, and the DAC analog-to-digital conversion chip adopts a 12-bit high-speed DAC conversion chip AD 9785; the FPGA chip adopts an XLNX-XC7A35T chip; the Flash chip adopts S25FL 032P.
The multi-channel low-noise automatic shimming control DAC chip and the circuit have a 16-channel automatic shimming adjusting function; the FPGA chip is also connected with a 50MHz main clock, and a plurality of groups of frequency multiplication clock conversion are realized in the FPGA chip and provided for the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip to respectively obtain required clock signals with different frequencies.
The FPGA chip is also connected with a T/R switching box control signal output circuit of a multi-channel nuclear magnetic pulse transmitting and nuclear magnetic signal receiving channel; and the FPGA chip is also connected with the enabling control of a plurality of DC TO DCLDO power management modules and is used for closing the idle power management chip in real time.
The FPGA chip is further connected with an output control circuit of a multi-path air exhaust cooling system and used for controlling the air exhaust system to be opened when the temperature in the machine box body rises, and the function of cooling the air exhaust cooling system is achieved.
The utility model provides a pair of observe and control mainboard, include: the mainboard main part, the mainboard main part is connected with the computer mainframe communication, be equipped with the FPGA chip in the mainboard main part to and the ADC conversion collection chip of being connected with the FPGA chip, DAC analog-to-digital conversion chip, the automatic shimming control DAC chip of multichannel low noise and circuit, the FPGA chip is connected with the computer mainframe communication, and the FPGA chip still is connected with temperature probe, is used for temperature regulation's magnetic field heating module, and gathers chip, DAC analog-to-digital conversion chip connection nuclear magnetic probe through the ADC conversion. Compared with the prior art, the utility model discloses the measurement and control mainboard integrates highly, and is simple high-efficient, low cost, and peripheral accessory is few, and the volume is tiny, and comprehensive properties is good, is fit for quantum computer and uses.
Drawings
Fig. 1 is the utility model discloses observe and control the structural schematic diagram of mainboard.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Please refer to fig. 1: fig. 1 is the utility model discloses observe and control the structural schematic diagram of mainboard.
The utility model provides a observe and control mainboard, include: the mainboard main part, the mainboard main part is connected with the computer mainframe communication, be equipped with the FPGA chip in the mainboard main part, and with ADC conversion collection chip, DAC analog-to-digital conversion chip, the automatic shimming control DAC chip of multichannel low noise and circuit that the FPGA chip is connected, the FPGA chip is connected with the computer mainframe communication, the FPGA chip still is connected with temperature probe, is used for temperature regulation's magnetic field heating module, and passes through ADC conversion collection chip, DAC analog-to-digital conversion chip connect nuclear magnetic probe.
Further, the measurement and control main board further comprises: and the Flash memory Flash chip is connected with the FPGA chip.
Furthermore, a multi-channel temperature sensor monitoring input circuit, a multi-channel temperature controller output channel and a multi-channel nuclear magnetic radio frequency transceiving conversion control channel are further arranged on the main board body, and the FPGA chip is in communication connection with the temperature probe through the multi-channel temperature sensor monitoring input circuit; the FPGA chip is in communication connection with the magnetic field heating module through the multi-path temperature controller output channel; the FPGA chip is connected with the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip through the multi-channel nuclear magnetic radio frequency transceiving conversion control channel.
Furthermore, a single clock source circuit is further arranged on the main board body and connected with the FPGA chip.
Furthermore, a USB conversion chip is further arranged on the main board body, the FPGA chip is in communication connection with the computer host through the USB conversion chip, and the USB conversion chip utilizes a USB signal bus to realize communication between the FPGA chip and the host.
Furthermore, the channel number and frequency of the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip are relatively adaptive.
Furthermore, the ADC conversion acquisition chip adopts an 8-bit high-speed ADC conversion chip AD9286, and the DAC analog-to-digital conversion chip adopts a 12-bit high-speed DAC conversion chip AD 9785; the FPGA chip adopts an XLNX-XC7A35T chip; the Flash chip adopts S25FL 032P.
Furthermore, the multi-channel low-noise automatic shimming control DAC chip and the multi-channel low-noise automatic shimming control circuit have a 16-channel automatic shimming adjusting function; the FPGA chip is also connected with a 50MHz main clock, and a plurality of groups of frequency multiplication clock conversion are realized in the FPGA chip and provided for the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip to respectively obtain required clock signals with different frequencies.
Furthermore, the FPGA chip is also connected with a T/R switching box control signal output circuit of a multi-channel nuclear magnetic pulse transmitting and nuclear magnetic signal receiving channel; and the FPGA chip is also connected with the enabling control of a plurality of DC TODC LDO power management modules and is used for closing the idle power management chip in real time.
Furthermore, the FPGA chip is also connected with an output control circuit of a multi-path exhaust cooling system and used for controlling the exhaust system to be opened when the temperature in the machine box body rises, so that the function of cooling the cooling system is realized
The scheme of the utility model is elaborated in detail below:
as shown in fig. 1, the utility model provides a be fit for desktop quantum computing field, be fit for carrying on mainboard that quantum computer used, including the mainboard main part, the USB communication of the USB of mainboard main part and the computer system end is connected to the host computer, and single track 4 lines USB2.0 communication just can realize communicating with the host computer.
The main board body is provided with an FPGA chip, a high-speed ADC conversion acquisition chip, a high-speed DAC analog-to-digital conversion chip, a multi-channel low-noise automatic shimming control DAC chip and a multi-channel low-noise automatic shimming control DAC circuit, a Flash memory Flash chip, a multi-channel temperature sensor monitoring input circuit, a multi-channel temperature controller output channel, a multi-channel nuclear magnetic radio frequency receiving and transmitting conversion control channel, and a single clock source circuit which are connected with the FPGA chip, and PFGA frequency multiplication output is used for providing required clock frequencies, so that the problems of mutual interference of independent clocks and asynchronous clock phases are. The multi-path power supply enables to control output, and the multi-path ventilation cools the control circuit.
The two ends of the 4-wire USB interface are respectively connected with the FPGA chip and the host, and the communication between the FPGA chip and the host is realized by utilizing a USB2.0 signal bus.
The FPGA chip is also connected with a multi-path programmable DAC analog-to-digital conversion chip which can independently generate nuclear magnetic microwave pulse signals with the frequency of 3MHz-100MHz, the DAC analog-to-digital conversion chip comprises a clock source which utilizes the FPGA to realize clock frequency multiplication, the clock source does not need to be independently set up, and an impedance matching device is added to the radio frequency.
The FPGA chip is also connected with an ADC conversion acquisition chip (a multi-channel high-speed nuclear magnetic receiving ADC conversion chip), and the number and the frequency of channels of the high-speed nuclear magnetic receiving ADC conversion chip and the nuclear magnetic pulse transmitting high-speed DAC analog-to-digital conversion chip are relatively adaptive, so that the functions of digital demodulation acquisition data in the FPGA, digital filtering in the FPGA and the like are realized.
The high-speed ADC conversion acquisition chip adopts an 8-bit high-speed ADC conversion chip AD9286, and the high-speed DAC analog-to-digital conversion chip adopts a 12-bit high-speed DAC conversion chip AD 9785; the FPGA chip adopts an XLNX-XC7A35T chip; the flash chip adopts an S25FL032P flash chip.
The FPGA chip is also connected with a high-precision low-noise automatic shimming control output ADC5360 DAC control chip matched with the main system, and the single chip can meet the 16-channel automatic shimming adjusting function.
The FPGA is also connected with the input of a multi-path magnet temperature detection sensor, and the output control function of a multi-path magnet temperature regulation system.
Furthermore, the FPGA chip is also connected with a 50MHz main clock, multiple groups of clocks of a single FPGA clock source are subjected to frequency multiplication conversion in the FPGA to provide high-frequency clock signals with different frequencies required by the ADC and the DAC, and the problems of consistent interference and asynchronous phase difference of independent clocks are solved.
The FPGA is also connected with a T/R switching box control signal output circuit of a multi-channel nuclear magnetic pulse transmitting and nuclear magnetic signal receiving channel.
Furthermore, the FPGA is also connected with the enabling control of a plurality of DC TO DC, LDO and other power management modules, so that the idle power management chip can be effectively closed in real time, and high efficiency and energy conservation are realized.
Furthermore, the FPGA is also connected with an output control circuit of a multi-path exhaust cooling system, so that the exhaust system can be effectively controlled to be opened when the temperature in the machine box body rises, and the function of cooling the cooling system is realized.
The utility model discloses observe and control the advantage of mainboard and lie in: the functions are centralized and complete, the circuit integration level is high, the number of peripheral parts is small, the size of the mainboard is small, the programmability is high, the cost is reduced, the weight is reduced, the size is reduced, and the like.
And the utility model discloses the scheme is through the simple 4 lines USB2.0 conversion serial ports mode's conversion chip with the USB interface connection of FPGA with quantum computer host computer, realized quantum computer customer end with the utility model discloses observe and control the mutual communication of mainboard, reduced complicated multi-thread interfaces such as traditional PCIE/RJ485 and serial ports, will in the past complicated quantum computer equipment's connected mode simplify.
Compared with the prior art, the utility model discloses can be more effective burn FLASH chip through FPGA's JTAG interface with the measurement and control program binary primary code that compiles in advance, open the measurement and control board power and just can observe and control the operation.
Furthermore, the utility model discloses can be more effectual utilize the USB bus to send at quantum computer APP customer end and observe and control pulse signal to FPGA, rethread FPGA's high-speed parallel port communication and DAC are mutual sends the nuclear magnetic pulse instruction and beats the pulse to nuclear magnetic probe, and 3 way nuclear magnetic pulse signal can be beaten simultaneously in step to this observation and control board.
The utility model discloses can be more effectual with the nuclear-magnetic signal collection FPGA that the ADC gathered in, carry out digital filtering, signal processing such as digital demodulation, with effectual nuclear-magnetic signal buffer memory in the FPGA memory, the computer client of the traditional quantum computer of rethread USB carries out the quantum computation process.
The utility model discloses can be more effectual utilize the USB bus to send automatic shimming instruction for FPGA at quantum computer APP customer end, FPGA is mutual through high-speed parallel port mode and 16 way shimming DAC, carries out automatic shimming operation process.
The utility model discloses can more effectually read the temperature information of 4 way temperature probe inputs in magnet and the quick-witted case environment simultaneously through FPGA, can implement 4 way magnet temperature control heating outputs simultaneously more effectively, can transmit the temperature information for the computer APP customer end of quantum computer through FPGA's USB bus in real time, carry out temperature monitoring management and demonstration.
The utility model discloses can be more effectual singly organize the master clock at FPGA and export DAC, the ADC respectively required different frequency clocks after the multiunit clock frequency multiplication of branching through FPGA inside, solved independent clock mutual interference separately, the unable counterpoint problem of originated phase place.
The utility model discloses can more effectually control the control signal output of 6 way T/R radio frequency channel conversion boxes on FPGA, reach high-speed switching receiving and dispatching conversion effect.
The utility model discloses can more effectually control each group AC-DC-DC/LDO etc. enable control output on FPGA, reach the energy-conserving province of complete machine function of consuming simultaneously.
The utility model discloses can more effectual control multichannel machine case exhaust system's on FPGA enable output and the rotational speed of adjusting the air discharge fan through the duty cycle mode, can more effectual realization power saving cooling noise reduction function.
The utility model discloses can be more effectual control the seven various breathing lamp illusion-colour state indication outputs of multichannel RGGB on FPGA, can be more effectual introduce more humanized field with the product.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A measurement and control mainboard is characterized by comprising: the mainboard main part, the mainboard main part is connected with the computer mainframe communication, be equipped with the FPGA chip in the mainboard main part, and with ADC conversion collection chip, DAC analog-to-digital conversion chip, the automatic shimming control DAC chip of multichannel low noise and circuit that the FPGA chip is connected, the FPGA chip is connected with the computer mainframe communication, the FPGA chip still is connected with temperature probe, is used for temperature regulation's magnetic field heating module, and passes through ADC conversion collection chip, DAC analog-to-digital conversion chip connect nuclear magnetic probe.
2. The measurement and control motherboard of claim 1, further comprising: and the Flash memory Flash chip is connected with the FPGA chip.
3. The measurement and control main board according to claim 1, wherein the main board body is further provided with a multi-channel temperature sensor monitoring input circuit, a multi-channel temperature controller output channel, and a multi-channel nuclear magnetic radio frequency transceiving conversion control channel, and the FPGA chip is in communication connection with the temperature probe through the multi-channel temperature sensor monitoring input circuit; the FPGA chip is in communication connection with the magnetic field heating module through the multi-path temperature controller output channel; the FPGA chip is connected with the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip through the multi-channel nuclear magnetic radio frequency transceiving conversion control channel.
4. The measurement and control mainboard of claim 1, wherein a single clock source circuit is further disposed on the mainboard body and connected to the FPGA chip.
5. The measurement and control main board according to claim 1, wherein a USB conversion chip is further disposed on the main board body, the FPGA chip is in communication connection with a computer host through the USB conversion chip, and the USB conversion chip utilizes a USB signal bus to realize communication between the FPGA chip and the computer host.
6. The measurement and control main board according to claim 1, wherein the channel number and frequency of the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip are adapted relatively.
7. The measurement and control main board according to claim 2, wherein the ADC conversion acquisition chip employs an 8-bit high-speed ADC conversion chip AD9286, and the DAC analog-to-digital conversion chip employs a 12-bit high-speed DAC conversion chip AD 9785; the FPGA chip adopts an XLNX-XC7A35T chip; the Flash chip adopts S25FL 032P.
8. The measurement and control main board according to claim 2, wherein the multi-channel low-noise automatic shimming control DAC chip and circuit has a 16-channel automatic shimming adjustment function; the FPGA chip is also connected with a 50MHz main clock, and a plurality of groups of frequency multiplication clock conversion are realized in the FPGA chip and provided for the ADC conversion acquisition chip and the DAC analog-to-digital conversion chip to respectively obtain required clock signals with different frequencies.
9. The measurement and control main board according to claim 1, wherein the FPGA chip is further connected with a multi-channel nuclear magnetic pulse transmitting and nuclear magnetic signal receiving channel T/R switching box control signal output circuit; and the FPGA chip is also connected with the enabling control of a plurality of DC TO DC LDO power management modules and is used for closing the idle power management chip in real time.
10. The measurement and control main board according to claim 1, wherein the FPGA chip is further connected with an output control circuit of a multi-path exhaust cooling system, and is used for controlling the exhaust system to be opened when the temperature in the machine box body rises, so as to realize the function of cooling the cooling system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021206421.7U CN212515421U (en) | 2020-06-24 | 2020-06-24 | Measurement and control mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021206421.7U CN212515421U (en) | 2020-06-24 | 2020-06-24 | Measurement and control mainboard |
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| Publication Number | Publication Date |
|---|---|
| CN212515421U true CN212515421U (en) | 2021-02-09 |
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|---|---|---|---|
| CN202021206421.7U Active CN212515421U (en) | 2020-06-24 | 2020-06-24 | Measurement and control mainboard |
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| CN (1) | CN212515421U (en) |
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- 2020-06-24 CN CN202021206421.7U patent/CN212515421U/en active Active
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