CN212460030U - Pulse width adjustable stepless delay circuit and multi-channel ground penetrating radar - Google Patents
Pulse width adjustable stepless delay circuit and multi-channel ground penetrating radar Download PDFInfo
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- CN212460030U CN212460030U CN202021065786.2U CN202021065786U CN212460030U CN 212460030 U CN212460030 U CN 212460030U CN 202021065786 U CN202021065786 U CN 202021065786U CN 212460030 U CN212460030 U CN 212460030U
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Abstract
The utility model provides a pulse width adjustable stepless delay circuit and multichannel ground penetrating radar. The circuit includes: the high-speed D trigger comprises a coupling capacitor, a first high-speed D trigger, a fifth resistor, a first adjustable resistor and a seventh capacitor, wherein the coupling capacitor is connected to a clock input end of the first high-speed D trigger, a data input end and a set input end of the first high-speed D trigger are connected to a power VCC, an inverted output end of the first high-speed D trigger is connected to one end of the fifth resistor, the other end of the fifth resistor is connected with one stator pin of the first adjustable resistor, the other stator pin of the first adjustable resistor is connected to the rotor pin of the first adjustable resistor and the reset input end of the first high-speed D trigger, and the other stator pin is further connected to one end of the seventh capacitor. The utility model provides a pulse width adjustable stepless delay circuit and multichannel ground penetrating radar can overcome the problem that the delay circuit precision that has now used digital chip to make as the basis is low excessively, the complexity is too high, the consumption is too high.
Description
Technical Field
The utility model relates to a ground penetrating radar technical field especially relates to a pulse width adjustable stepless delay circuit and multichannel ground penetrating radar.
Background
The ultra-wideband radar technology is a nondestructive detection method for detecting the target information hidden in a medium layer after the medium layering condition or an obstacle is detected by using a broadband narrow pulse electromagnetic wave, has the characteristics of strong penetration capability, strong anti-interference capability, high resolution, simple structure and the like, and has very wide application in various civil and military fields such as geological exploration, road quality detection and evaluation, through-wall imaging, anti-terrorism and the like. The multi-channel ground penetrating radar has incomparable advantages in the aspect of detection efficiency, and particularly can greatly improve the operation efficiency in the aspect of urban road disease detection. The trigger signal delayer is an important component of an ultra-wideband radar system, and the consistency of signals of different channels is influenced by the difference of delay amounts of trigger signals among different channels to a certain extent, so that the selection and design of the trigger signal delayer are very important for a multi-channel ground penetrating radar system.
Currently, methods for generating trigger pulse signal delay by using semiconductor devices are roughly classified into several types: one is to generate narrow pulse trigger signals with different delay quantities by using digital chips such as an MCU (microprogrammed control unit) or an FPGA (field programmable gate array); the other method is to realize the adjustment of the delay amount of the trigger signal based on a high-precision precise delay chip; the other is based on that the analog chip generates narrow pulse trigger signals with different delay amounts by utilizing different charging and discharging time of a capacitor or an inductor, and the circuit realizes the delay of the trigger signals by utilizing different time constants generated by different RC or RL combinations of the circuit.
The trigger signal time delay of different channels of the existing multi-channel ground penetrating radar is mostly realized by the time delay of a narrow pulse signal generated by a digital chip, and a finer clock signal can be generated by improving a working clock of the digital chip, so that the precision of the trigger signal time delay is improved, but the improvement of the working clock of the digital chip can increase the power consumption of a system on one hand, and the improvement of the working clock of the digital chip has a limit on the other hand, and the time delay precision of the trigger signal generated by the general digital chip is basically in the nanosecond level and is used for coarse time delay adjustment; although the trigger signals with different delay amounts generated by the high-precision precise delay chip can improve the delay precision and can be generally precise to 5 picoseconds, the complexity of the system can be increased, the high-precision precise delay chip is required to realize that different delay amounts require the digital chip to be matched to generate control words for controlling the delay amounts, a limit resolution is provided, and the power consumption of the high-precision delay chip is generally higher. The time points of the generated transmission signals are different due to different routing lengths and different device parameters among different channels, and the arrival times of the direct wave signals of the echo signals received by the different channels are different due to the factors, so that the consistency of the signals among the different channels is influenced.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a pulse width adjustable stepless delay circuit and multichannel ground penetrating radar can overcome the problem that the delay circuit precision that current used digital chip to make as the basis is low excessively, the complexity is too high, the consumption is too high.
In order to solve the above technical problem, the utility model provides a pulse width adjustable stepless delay circuit, the circuit includes: stepless time delay regulating circuit of pulse signal, wherein, stepless time delay regulating circuit of pulse signal includes: the circuit comprises a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1 and a seventh capacitor C7, wherein the coupling capacitor C6 is connected to a clock input end of a first high-speed D flip-flop U3, a data input end and a set input end of the first high-speed D flip-flop U3 are connected to a power VCC, an inverting output end of the first high-speed D flip-flop U3 is connected to one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected to a stator pin of the first adjustable resistor RP1, the other stator pin of the first adjustable resistor RP1 is connected to a rotor pin of the first adjustable resistor RP1 and a reset input end of the first high-speed D flip-flop U3, the other stator pin is further connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.
In some embodiments, further comprising: the pulse width stepless adjusting circuit comprises: a second high-speed D flip-flop U4, a sixth resistor R6, a second adjustable resistor RP2, an eighth capacitor C8, a ninth capacitor C9 and a first inductor L1, a clock input terminal of the second high-speed D flip-flop U4 is connected to an inverted output terminal of the first high-speed D flip-flop U3, a data input terminal and a set input terminal of the second high-speed D flip-flop U4 are connected to the power VCC, a non-inverted output terminal of the second high-speed D flip-flop U4 is connected to one terminal of the ninth capacitor C9, the other terminal of the ninth capacitor C9 is connected to one terminal of the first inductor L1, the other terminal of the first inductor L1 is connected to the high-voltage power source HV, an inverted output terminal of the second high-speed D flip-flop U4 is connected to one terminal of the sixth resistor R6, the other terminal of the sixth resistor R6 is connected to one stator pin of the second adjustable resistor RP2, the other stator pin of the second adjustable resistor RP2 is connected to a stator pin of the second adjustable resistor RP2 and a reset input terminal, the other stator pin is also connected to one end of an eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded.
In some embodiments, further comprising: a pulse signal shaping circuit, the pulse signal shaping circuit comprising: the high-speed driving circuit comprises a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4 and a fifth diode D5, wherein an output end of the first inverter U1 is connected to a cathode of the first high-speed diode D3, an anode of the first high-speed diode D3 is connected to an input end of the second inverter U2, an output end of the second inverter U2 is respectively connected to an anode of the fourth diode D4, a cathode of the fifth diode D5 and a coupling capacitor C6, a cathode of the fourth diode D4 is connected to one ends of the fifth capacitor C5 and the fourth resistor R4, the other end of the fifth capacitor C5 is grounded, the other end of the fourth resistor R4 is connected to VCC and is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and an anode of the fifth diode D5 is grounded.
In some embodiments, further comprising: filtering and protection circuit, filtering and protection circuit includes: the inverter comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein one end of the first capacitor C1 is connected with an input signal, the other end of the first capacitor C1 is connected with one ends of a first resistor R1 and a second resistor R2, the other end of the first resistor R1 is grounded, the other end of the second resistor R2 is connected with the anode of a first diode D1 and the cathode of a second diode D2, the cathode of the first diode D1 is connected with one ends of a third capacitor C3 and a third resistor R3, the other end of the third capacitor C3 is grounded, the other end of the third resistor R3 is connected with a power supply VCC and is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the anode of a second diode D2 is grounded, and the other end of the second resistor R2 is connected with an input end of a first inverter U1.
In some embodiments, the first inverter U1 and the second inverter U2 are both schmitt inverters.
In some embodiments, the input trigger signal has an amplitude of between 1.8V and 5V, a pulse width of between 50ns and 500ns, and a signal repetition frequency of between 20kHz and 400 kHz.
Furthermore, the utility model also provides a multichannel ground penetrating radar, this multichannel ground penetrating radar includes: the pulse width adjustable stepless delay circuit according to the foregoing.
After adopting such design, the utility model discloses following advantage has at least:
(1) compared with a circuit constructed by a common digital chip or a delay chip, the pulse signal stepless delay adjusting circuit constructed by the high-speed D trigger can realize stepless adjustment of delay amount, has a simple structure, realizes accurate adjustment of the delay amount among different channels, and improves the consistency among the channels.
(2) Compared with a pulse width adjusting circuit constructed by a common digital chip, the pulse signal shaping circuit constructed by the high-speed D trigger has higher adjusting precision, can realize stepless adjustment of the duty ratio of the pulse signal, and has simple structure and higher reliability.
(3) Through shaping of the high-speed diode and the Schmitt inverter, rising edges and falling edges of output signals are steeper, jitter is smaller, and the quality of trigger signals is higher.
Drawings
The foregoing is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clear, the present invention will be further described in detail with reference to the accompanying drawings and the detailed description.
Fig. 1 is a block diagram of a circuit structure of a pulse width adjustable stepless delay circuit suitable for a multi-channel ground penetrating radar provided by the embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a pulse width adjustable stepless delay circuit suitable for a multi-channel ground penetrating radar provided by the embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.
Referring to fig. 1 and fig. 2, a pulse width adjustable stepless delay circuit suitable for a multi-channel ground penetrating radar in the present embodiment includes:
the filtering and protecting circuit 101 is used for filtering an input signal and protecting a back-end circuit so as to prevent the back-end circuit from being damaged due to overlarge input signal; a pulse signal shaping circuit 102, the front end of which is electrically connected to the input signal filtering and protecting circuit, for shaping the edge of the pulse signal; the front end of the pulse signal stepless delay adjusting circuit 103 is electrically connected to the pulse signal shaping circuit and is used for realizing stepless adjustment on the delay of the pulse signal, realizing accurate adjustment of trigger delay of different channels and ensuring consistency among the channels; the front end of the pulse width stepless adjusting circuit 104 is electrically connected to the pulse signal stepless delay adjusting circuit, and is used for stepless adjusting the width (duty ratio) of the pulse signal to adapt to the triggering requirements of different transmitters or receivers.
The following respectively describes each component of the pulse width adjustable stepless delay circuit suitable for the multi-channel ground penetrating radar of the present embodiment in detail.
First, the circuit structure of the filtering and protection circuit 101 is described.
In this embodiment, the input trigger pulse signal is a square wave signal with an amplitude of 3.3V, a pulse width of 200ns and a signal repetition frequency of 200kHz, the present invention is not limited thereto, the amplitude of the trigger signal may be between 1.8V to 5V, the pulse width may be between 50ns to 500ns, and the signal repetition frequency may be between 20kHz to 400 kHz.
Referring to fig. 2, the filtering and protection circuit 101 includes: the trigger circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein a first end of the first capacitor C1 is connected to a trigger pulse signal input end, a second end of a first capacitor C1 is connected to a first end of the first resistor R1 and a first end of the second resistor R2, a second end of the first resistor R1 is grounded, a second end of the second resistor R2 is connected to a first end of the first diode D1 and a second end of the second diode D2, a first end of the second diode D2 is grounded, a second end of the first diode D1 is connected to a first end of the third resistor R3 and a first end of the second capacitor C2, a second end of the second capacitor C2 is grounded, a second end of the third resistor R3 is connected to a power supply VCC and a first end of the third capacitor C3, and a second end of the third capacitor C3 is grounded.
In the filtering and protecting circuit 101, a high-pass filtering network formed by a first resistor R1 and a first capacitor C1 performs preliminary filtering on an input signal, isolates interference signals such as direct current components and the like, so that the signal in a designed repetition frequency range (20 kHz-400 kHz) passes through, a second resistor R2 is used as a matched input resistor of a pulse shaping circuit, and a first diode D1, a second diode D2, a third resistor R3, a second capacitor C2 and a third capacitor C3 form an input protecting circuit together, so that the input signal is clamped between 0 and VCC, and the damage of a rear-end circuit caused by the overlarge input signal is prevented.
Next, a circuit configuration of the pulse signal shaping circuit 102 will be described.
Referring to fig. 2, the pulse shaping circuit 102 includes: a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4, a fifth diode D5, the first end of the first inverter U1 is connected to the second end of the second resistor R2 of the input signal filtering and protecting circuit, the second end of the first inverter U1 is connected to the second end of the first high-speed diode D3, the first end of the first high-speed diode D3 is connected to the first end of the second inverter U2, the second end of the second inverter U2 is connected to the first end of the fourth diode D4 and the second end of the fifth diode D5, the first end of the fifth diode D5 is grounded, the second end of the fourth diode D4 is connected to the first end of the fourth resistor R4 and the first end of the fifth capacitor, the second end of the fourth resistor R4 and the first end of the fourth capacitor C4 are commonly connected to the power source VCC, and the second end of the fourth capacitor C4 and the second end of the fifth capacitor C5 are commonly grounded.
In the pulse signal shaping circuit 102, the first inverter U1, the second inverter U2 shapes the edge of the pulse signal, converts the pulse signal with slow edge change into a rectangular pulse signal with steep edge, and prevents the change of the output signal caused by the tiny change (lower than a certain threshold) of the input voltage, the first high-speed diode D3 shapes the negative pulse signal output by the U1, so that the edge of the pulse signal is steeper, and the quality of the trigger pulse signal is improved, and the first high-speed diode D3, the fourth diode D4, the fourth resistor R4, the fourth capacitor C4 and the fifth capacitor C5 jointly form an output protection device of the pulse shaping circuit, clamp the output signal between 0 and VCC, and prevent the rear end circuit from being damaged due to the overlarge output signal.
Next, a circuit configuration of the pulse signal stepless delay adjusting circuit 103 will be described.
Referring to fig. 2, the pulse signal stepless delay adjusting circuit 103 includes: a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1, and a 7 th capacitor C7, wherein a first end of the coupling capacitor C6 is connected to a second end of the second inverter, which is an output end of the shaping circuit, a second end of the sixth capacitor C6 is connected to a third end, which is a clock input end of the first high-speed D flip-flop U3, a second end of the data input end and a fourth end of the set input end of the first high-speed D flip-flop are connected to the power VCC, a fifth output end of the non-inverting output end of the first high-speed D flip-flop U3 is not connected, a sixth end of the inverting output end of the first high-speed D flip-flop U3 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a second end of the adjustable resistor RP1, a first end of the adjustable resistor RP1 is connected to a reset input end of the first high-speed D flip-flop U3 and a third end of, a second terminal of the seventh capacitor C7 is connected to ground.
In the pulse signal stepless delay adjusting circuit 103, the coupling capacitor C6 shapes the input trigger square wave signal, the differential action of the capacitor on the square wave signal is used to sharpen the trigger signal and serve as the input clock signal of the first high-speed D flip-flop U3, the input signal and the set end of the first high-speed D flip-flop U3 are both connected to the high-level VCC, the output signal of the flip-flop is only determined by the rising edge and the reset (zero clearing) end of the clock, the positive phase output end of the first high-speed D flip-flop U3 is not used, the utility model discloses only the negative phase output end of the first high-speed D flip-flop U3 is used, the negative phase output end of the first high-speed D flip-flop U3 is connected to the reset end of the first high-speed D flip-flop U3, the output end of the first high-speed D flip-flop U3 is connected to the fifth resistor R5, the first adjustable resistor RP1 and the seventh capacitor C7 to form an RC network, and the output signal is fed, The time constant of an RC network formed by the first adjustable resistor RP1 and the seventh capacitor C7 is adjusted by the parameter values of the first adjustable resistor RP1 and the seventh capacitor C7, so that the time of arrival of the low level of a feedback signal fed back to a reset end is used for realizing the time of the pulse signal delay, the approximate time of the pulse signal delay can be determined by adjusting the parameter values of the fifth resistor R5 and the seventh capacitor C7, and the precise stepless adjustment of the pulse signal delay can be realized by adjusting the parameter value of the first adjustable resistor RP1 (precise adjustable resistor).
Finally, the circuit configuration of the pulse width stepless adjustment circuit 104 is explained.
Referring to fig. 2, the pulse signal stepless delay adjusting circuit 104 includes: a second high-speed D flip-flop U4, a sixth resistor R6, a second adjustable resistor RP2, an 8 th capacitor C8, a ninth capacitor C9, and a first inductor L1, wherein a clock input terminal, i.e. a third terminal, of the first high-speed D flip-flop U3 is connected to an output terminal of the pulse signal stepless delay adjusting circuit, i.e. a sixth terminal of an inverting output terminal of the first high-speed D flip-flop, a fourth segment of a second terminal of a data input terminal and a set input terminal of the second high-speed D flip-flop is connected to the power source VCC, a sixth terminal of an inverting output terminal of the second high-speed D flip-flop is connected to a first terminal of the sixth resistor R6, a second terminal of the sixth resistor R6 is connected to a second terminal of the adjustable resistor RP2, a first terminal of the adjustable resistor RP2 is connected to a reset input terminal of the second high-speed D flip-flop U4 and a third terminal of itself, a third terminal of the adjustable resistor RP2 is connected to a, the fifth end of the non-inverting output end of the second high-speed D flip-flop U4 is connected to the first end of the ninth capacitor C9, the second end of the ninth capacitor C9 is connected to the first end of the first inductor L1 to be the output end of the whole circuit, and the second end of the first inductor L1 is connected to the high voltage power supply (100V-500V).
In the pulse width stepless adjusting circuit 104, the output signal of the previous stage circuit is used as the input clock signal of the second high-speed D flip-flop U4, the input signal and the set terminal of the second high-speed D flip-flop U4 are both connected to the high level VCC, so that the output signal of the flip-flop is only determined by the rising edge and the reset (clear) terminal of the clock, the negative phase output terminal of the second high-speed D flip-flop U4 is connected to the sixth resistor R6, the second adjustable resistor RP2 and the eighth capacitor C8 to form an RC network, and the output signal is fed back to the reset terminal of the second high-speed D flip-flop U4 through the first terminal of the second adjustable resistor RP2, the time constant of the RC network formed by the sixth resistor R6, the second adjustable resistor RP2 and the eighth capacitor C8 is adjusted by adjusting the values of the parameters, so that the arrival time of the low level of the feedback signal fed back to the reset terminal adjusts the width of the output pulse signal, the approximate width of a pulse signal can be determined by adjusting the parameter values of the six resistors R6 and the eighth capacitor C8, the precise stepless adjustment of the pulse signal width can be realized by adjusting the parameter values of the second adjustable resistor RP2 (precise adjustable resistor), the pulse signal is output through the non-inverting output end of the second high-speed D trigger U4, the finally adjusted signal is coupled to the output end by the coupling capacitor C9, if the pulse signal is used as a trigger signal of some transmitters, a high-voltage power supply can be used as output to the transmitters through the first inductor L1, and at the moment, the coupling capacitor C9 needs to adopt a high-voltage-resistant capacitor to prevent the second high-speed D trigger from being broken down and damaged by direct-current high voltage.
The working process of the pulse width adjustable stepless delay circuit suitable for the multi-channel ground penetrating radar is as follows:
the method comprises the following steps: when the trigger signal is in a low level state, the first diode D1, the second diode D2, the first high-speed diode D3, the fourth diode D4, and the fifth diode D5 are in a reverse cut-off state, the inverted output terminal of the sixth terminal of the first high-speed D flip-flop U3 is in a high level state, the reset terminal of the first terminal is in a high level state, the inverted output terminal of the sixth terminal of the second high-speed D flip-flop U4 is in a high level state, the reset terminal of the first terminal is in a high level state, the seventh charging and discharging capacitor C7 is charged by the fifth resistor R5 and the first adjustable resistor RP1, and the eighth charging and discharging capacitor C8 is charged by the sixth resistor R6 and the second adjustable resistor RP 2.
Step two: when the rising edge of the trigger signal comes, the trigger signal changes into high level, the pulse is sharpened through the action of the first capacitor C1, the direct current component in the trigger signal is isolated by matching with the action of the first resistor R1, high-pass filtering is carried out, and the direct current component is input into the pulse shaping circuit through the input matching resistor and the second resistor R2. The third resistor R3, the second capacitor C2 and the third capacitor C3 form a power supply filter network for VCC filtering, some noise waves are filtered, the input pulse signal is clamped between 0 and VCC through the first diode D1 and the second diode D2, if the amplitude of the input signal is higher than VCC + Uth, the first diode D1 is conducted to stabilize the voltage at VCC + Uth, if the amplitude of the input signal is lower than-Uth, the second diode D2 is conducted to stabilize the voltage at-Uth, the voltage is generally smaller and is between 0.2 and 0.7V, and therefore the input voltage can be clamped in a safe range, and the safety of a rear-stage circuit is guaranteed.
Step three: the filtered trigger signal is shaped for the first time through the first inverter U1, the filtered trigger signal is converted from a rising edge to a falling edge, and the edge signal is sharpened, the state of the output end of the first inverter U1 changes from a high level to a low level, at this time, the first high-speed diode D3 is turned on, the input end of the second inverter U2 is converted from a high level to a low level, and the edge of the trigger signal is sharpened and shaped by the fast turn-on of the first high-speed diode D3, then the trigger signal is input into the second inverter U2 for the third shaping, the falling edge is converted to a rising edge, the edge signal is sharpened, the state of the output end of the second inverter U2 is also quickly converted from a low level to a high level, the fourth resistor R4, the fourth capacitor C4, the fifth capacitor C5, the fourth diode D4 and the fifth diode D5 jointly form a protection network to clamp the output signal within a safe range, and the safe operation of the rear-stage circuit is ensured.
Step four: the shaped trigger signal is output to the clock input end of the first high-speed D flip-flop U3 through the coupling capacitor C6, when a rising edge of the trigger signal at the clock input end arrives, the state of the inverted output end at the sixth end is changed from high level to low level, the seventh capacitor C7 starts to discharge through the fifth resistor R5 and the first adjustable resistor RP1, the voltage at the first end of the seventh capacitor C7 cannot be suddenly changed to low level immediately, but is slowly reduced to low level (0V) through discharging, meanwhile, the voltage at the first end of the first adjustable resistor RP1 is also slowly reduced from high level to low level and is fed back to the reset end of the first high-speed D flip-flop U3, when the voltage is reduced to low level, the first high-speed D flip-flop U3 is reset, the inverted output end at the sixth end thereof is changed to high level, and the seventh capacitor C7 is charged through the fifth resistor R5 and the first adjustable resistor RP1, the input voltage of the reset end is enabled to be high level, wherein the time for changing the input level of the reset end from high level to low level is related to the time constant tau 1 of an RC network consisting of the fifth resistor R5, the first adjustable resistor RP1 and the seventh capacitor C7, if tau 1 is larger, the level change is slower, the reset time of the first high-speed D trigger U3 is longer, the delay time of the output trigger signal is longer, conversely, if the time constant tau 1 is smaller, the level change is faster, the reset time of the first high-speed D trigger U3 is shorter, the delay time of the output trigger signal is shorter, the approximate length of the delay time can be preliminarily determined through the values of the fifth resistor R5 and the seventh capacitor C7, and the delay time of the trigger signal can be precisely and steplessly adjusted through the adjustment of the value of the precise adjustable resistor RP 1.
Step five: the delayed trigger signal is used as the clock input of the second high-speed D flip-flop U4, the phase of the delayed trigger signal changes, the rising edge changes to the falling edge, the falling edge changes to the rising edge, the rising edge of the delay signal output by the first high-speed D flip-flop U3 through reset is used as the input trigger signal of the second high-speed D flip-flop U4, when the state changes from the low level to the high level, the state of the inverted output end of the sixth end of the second high-speed D flip-flop U4 changes from the high level to the low level, the eighth capacitor C7 starts to discharge through the sixth resistor R6 and the second adjustable resistor RP2, the voltage at the first end of the eighth capacitor C8 cannot be suddenly changed to the low level immediately, but is slowly reduced to the low level (0V) through discharge, and the voltage at the first end of the second adjustable resistor RP2 also slowly decreases from the high level to the low level and feeds back to the reset end of the second high-speed D flip-flop U4, when the voltage is lowered to low level, the second high-speed D flip-flop U4 is reset, the inverted output terminal of the sixth terminal thereof is changed to high level, and the eighth capacitor C8 is charged through the sixth resistor R6 and the second adjustable resistor RP2, so that the input voltage of the reset terminal is high level, wherein the time for changing the input level of the reset terminal from high level to low level and the time constant τ 2 of the RC network formed by the sixth resistor R6, the first adjustable resistor RP2 and the eighth capacitor C8 are related, if τ 2 is relatively large, the level change is relatively slow, the reset time of the second high-speed D flip-flop U4 is long, the time for maintaining high level of the trigger signal output from the fifth terminal is long, the pulse width is wide, conversely, if the time constant τ 2 is relatively small, the level change is relatively fast, the reset time of the second high-speed D flip-flop U4 is short, the time for maintaining high level of the trigger signal output from the fifth terminal is short, the pulse width is narrowed, an approximate pulse width can be preliminarily determined through the values of the sixth resistor R6 and the eighth capacitor C8, and the pulse width of the output trigger signal can be precisely and steplessly adjusted through adjusting the value of the precisely adjustable resistor RP2, so that different requirements of different transmitters or receivers on the trigger pulse width are met.
Step six: the trigger signal after delay and pulse width adjustment is output to the output end from the fifth-end non-inverting output end of the second high-speed D trigger U4 through the ninth capacitor C9 of the coupling capacitor, if the trigger signal is used as a trigger signal of some transmitters, a high-voltage direct-current power supply HV (100-500V) is further coupled into the output trigger signal through the first inductor L1, meanwhile, the first inductor L1 can also play a role in filtering high-frequency alternating-current signals, ripple waves and partial harmonic alternating-current noise components in the high-voltage HV can be effectively filtered, the influence of noise on a rear-end circuit is reduced, and if the trigger signal does not need the high-voltage direct-current component, the first inductor L1 and the high-voltage power supply.
Practical tests prove that the pulse trigger signal after delay adjustment can be subjected to stepless delay between 0 and 1000ps, the pulse width can be subjected to stepless adjustment between 1ns and 500ns, the signal repetition frequency can be between 20kHz and 400kHz, the processed signal has steep rising edge, small jitter and high trigger quality, can meet the trigger requirements of different transmitters and receivers, can accurately adjust the radar echo signals of different channels in the multi-channel ground penetrating radar to be consistent in delay, and fully ensures the consistency between channels.
The above description is only for the preferred embodiment of the present invention, and not intended to limit the present invention in any way, and those skilled in the art can make various modifications, equivalent changes and modifications using the above-described technical content, all of which fall within the scope of the present invention.
Claims (7)
1. An adjustable pulse width stepless delay circuit, comprising: stepless time delay regulating circuit of pulse signal, wherein, stepless time delay regulating circuit of pulse signal includes: the circuit comprises a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1 and a seventh capacitor C7, wherein the coupling capacitor C6 is connected to a clock input end of a first high-speed D flip-flop U3, a data input end and a set input end of the first high-speed D flip-flop U3 are connected to a power VCC, an inverting output end of the first high-speed D flip-flop U3 is connected to one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected to a stator pin of the first adjustable resistor RP1, the other stator pin of the first adjustable resistor RP1 is connected to a rotor pin of the first adjustable resistor RP1 and a reset input end of the first high-speed D flip-flop U3, the other stator pin is further connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.
2. The pulse width adjustable stepless delay circuit of claim 1, further comprising: the pulse width stepless adjusting circuit comprises: a second high-speed D flip-flop U4, a sixth resistor R6, a second adjustable resistor RP2, an eighth capacitor C8, a ninth capacitor C9 and a first inductor L1, a clock input terminal of the second high-speed D flip-flop U4 is connected to an inverted output terminal of the first high-speed D flip-flop U3, a data input terminal and a set input terminal of the second high-speed D flip-flop U4 are connected to the power VCC, a non-inverted output terminal of the second high-speed D flip-flop U4 is connected to one terminal of the ninth capacitor C9, the other terminal of the ninth capacitor C9 is connected to one terminal of the first inductor L1, the other terminal of the first inductor L1 is connected to the high-voltage power source HV, an inverted output terminal of the second high-speed D flip-flop U4 is connected to one terminal of the sixth resistor R6, the other terminal of the sixth resistor R6 is connected to one stator pin of the second adjustable resistor RP2, the other stator pin of the second adjustable resistor RP2 is connected to a stator pin of the second adjustable resistor RP2 and a reset input terminal, the other stator pin is also connected to one end of an eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded.
3. The pulse width adjustable stepless delay circuit of claim 1, further comprising: a pulse signal shaping circuit, the pulse signal shaping circuit comprising: the high-speed driving circuit comprises a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4 and a fifth diode D5, wherein an output end of the first inverter U1 is connected to a cathode of the first high-speed diode D3, an anode of the first high-speed diode D3 is connected to an input end of the second inverter U2, an output end of the second inverter U2 is respectively connected to an anode of the fourth diode D4, a cathode of the fifth diode D5 and a coupling capacitor C6, a cathode of the fourth diode D4 is connected to one ends of the fifth capacitor C5 and the fourth resistor R4, the other end of the fifth capacitor C5 is grounded, the other end of the fourth resistor R4 is connected to VCC and is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and an anode of the fifth diode D5 is grounded.
4. The pulse width adjustable stepless delay circuit of claim 3, further comprising: filtering and protection circuit, filtering and protection circuit includes: the inverter comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein one end of the first capacitor C1 is connected with an input signal, the other end of the first capacitor C1 is connected with one ends of a first resistor R1 and a second resistor R2, the other end of the first resistor R1 is grounded, the other end of the second resistor R2 is connected with the anode of a first diode D1 and the cathode of a second diode D2, the cathode of the first diode D1 is connected with one ends of a third capacitor C3 and a third resistor R3, the other end of the third capacitor C3 is grounded, the other end of the third resistor R3 is connected with a power supply VCC and is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the anode of a second diode D2 is grounded, and the other end of the second resistor R2 is connected with an input end of a first inverter U1.
5. The pulse width adjustable stepless delay circuit of claim 3, wherein the first inverter U1 and the second inverter U2 are both Schmitt inverters.
6. The pulse width adjustable stepless delay circuit of claim 1, wherein the amplitude of the input trigger signal is between 1.8V and 5V, the pulse width is between 50ns and 500ns, and the signal repetition frequency is between 20kHz and 400 kHz.
7. A multi-channel ground penetrating radar, comprising: the pulse width adjustable stepless delay circuit of any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021065786.2U CN212460030U (en) | 2020-06-11 | 2020-06-11 | Pulse width adjustable stepless delay circuit and multi-channel ground penetrating radar |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021065786.2U CN212460030U (en) | 2020-06-11 | 2020-06-11 | Pulse width adjustable stepless delay circuit and multi-channel ground penetrating radar |
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| CN212460030U true CN212460030U (en) | 2021-02-02 |
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| CN202021065786.2U Active CN212460030U (en) | 2020-06-11 | 2020-06-11 | Pulse width adjustable stepless delay circuit and multi-channel ground penetrating radar |
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| CN (1) | CN212460030U (en) |
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