CN212391588U

CN212391588U - Resistance adjustment circuit, reference resistance network and battery management system

Info

Publication number: CN212391588U
Application number: CN202022170990.7U
Authority: CN
Inventors: 周号
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-22
Anticipated expiration: 2030-09-28

Abstract

The present disclosure provides a resistance adjustment circuit, which includes: a fuse resistor that is fusible by a voltage applied across the fuse resistor; the first electronic switch is arranged on a circuit with the fusing resistor connected with a power supply or grounded; a pull-up resistor disposed in a circuit between the fuse resistor and the power supply; the latch is connected to one end of the pull-up resistor connected with the fusing resistor; the second electronic switch is arranged on a circuit connected with the fusing resistor and the latch; applying a first PWM waveform to the first electronic switch to enable the resistance adjusting circuit to be intermittently connected to a power supply; a second PWM waveform is applied to the second electronic switch to turn off the second electronic switch after sampling by the latch. The disclosure also provides a reference resistance network and a battery management system.

Description

Resistance adjustment circuit, reference resistance network and battery management system

Technical Field

The disclosure relates to a resistance adjusting circuit, a reference resistance network and a battery management system, and belongs to the technical field of integrated circuits.

Background

In the battery system, overcharge and overdischarge of the battery may not only reduce the service life of the battery, but also may cause safety accidents such as explosion and fire.

The overvoltage and overcurrent detection of the battery in the prior art is realized through a comparator circuit, namely, whether the overvoltage and overcurrent are detected by comparing the collected voltage with the reference voltage, so that the accuracy of the reference voltage directly influences the overvoltage and overcurrent detection result of the battery.

A common reference voltage is obtained by the circuit shown in fig. 1, but during the manufacturing process of the circuit, the resistor, the transistor and the operational amplifier all generate deviation due to the semiconductor manufacturing process, and the deviation has a substantial influence on the reference voltage. Measured and calculated, V caused by semiconductor process_REFError of about 30mV, thereby causing inaccuracy in detecting battery overvoltage, with a voltage detection deviation of 30 mV.

Further, if the MOS on-resistance is 5m Ω, namely rds (on) is 5m Ω, because V_REFErrors can cause inaccurate overcurrent detection, and the current deviation is as follows: v_REF/Rds(on)＝30mV/5mΩ＝6A。

For integrated circuits, once the chip is taped out, the relevant characteristics of the circuit are determined. However, due to the influence of non-ideal factors such as process environment, some parameters do not meet the design expectations, resulting in the accuracy and performance of the chip after tape-out being far from expectations. In order to make up for the gap between circuit design expectations and chip ultimate performance, tuning techniques need to be employed.

At the solution of V_REFBefore packaging the chip, V can be found through wafer level testing (wafer level testing)_REFThen, the metal wiring is cut off by using a film resistance laser trimming technique (laser cut), and the ratio of R1/R2 is changed, and the basic principle is shown in FIG. 2.

However, in the completion ofAfter wafer level testing, the chip enters a packaging process, and after packaging is finished, a reference voltage generating circuit (silicon bandgap reference source) can cause V due to the influence of the stress of the chip on a packaging base and the stress of plastic package at the top of the package_REFAgain, a deviation occurs.

In order to solve the deviation caused by the manufacturing process and the error caused by the package stress, after the chip package is completed, a high-current fuse polysilicon resistor (poly fuse) adjustment mode is adopted to cut off the resistor connection, change the ratio of the resistor R1/R2, and eliminate the system (process manufacturing and package stress) error, and the schematic diagram is shown in FIG. 3.

Referring to the circuit shown in fig. 3, when the fuse resistor fuse is not blown, the resistance value is much smaller than the pull-up resistor RU. At this time, the inverter outputs high, and the NMOS M1 is turned on. Since the on-resistance of the NMOS M1 is much smaller than that of R2 and R1, the equivalent resistance between AB is R1. After the fuse resistor fuse is fused, the resistor is infinite, at the moment, the inverter outputs low level, the NMOS M1 is turned off, and the equivalent resistor between the AB is R1+ R2.

However, the problem of adjusting the resistance by blowing the polysilicon resistor/fuse resistor with a large current is that it easily causes circuit leakage, and the system power consumption increases, which is not allowed in the low power consumption circuit design.

After the polysilicon resistor/fuse resistor is completely fused, a maximum resistance value of 1-10M omega can be achieved, but if the fuse is not completely fused, or along with circuit aging or circuit temperature change, the polysilicon resistor can be 200-500 k omega, and if the power supply voltage is 5V, the leakage current can be 10-25 uA.

Therefore, it is desirable to provide a resistance adjusting circuit, which can solve the errors caused by package stress and manufacturing process, and can solve the leakage problem after the polysilicon resistor is blown by a large current, thereby reducing the system power consumption.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides a resistance adjustment circuit, a reference resistance network and a battery management system.

According to an aspect of the present disclosure, there is provided a resistance adjustment circuit including:

a fuse resistor that is fusible by a voltage applied across the fuse resistor;

the first electronic switch is arranged on a circuit with the fusing resistor connected with a power supply or grounded;

a pull-up resistor disposed in a circuit between the fuse resistor and the power supply;

the latch is connected to one end of the pull-up resistor connected with the fusing resistor; and

the second electronic switch is arranged on a circuit for connecting the fusing resistor and the latch;

applying a first PWM waveform to the first electronic switch to enable the resistance adjusting circuit to be intermittently connected to a power supply; a second PWM waveform is applied to the second electronic switch to turn off the second electronic switch after sampling by the latch.

According to the resistance adjustment circuit of at least one embodiment of the present disclosure, one end of the fuse resistor is grounded, and the other end is connected to the adjustment pad through the first switching device.

According to at least one embodiment of this disclosure, the resistance adjustment circuit, the latch includes:

the input end of the first inverter is connected with the second electronic switch;

the input end of the second inverter is connected to the output end of the first inverter, and the output end of the second inverter is connected to the input end of the first inverter through a third electronic switch; and

the input end of the third inverter is connected to the output end of the first inverter;

wherein a third PWM waveform applied to the third electronic switch is inverted from a second PWM waveform applied to the second electronic switch.

The resistance adjustment circuit according to at least one embodiment of the present disclosure further includes: a comparator disposed in the circuit between the fuse resistor and the second electronic switch.

According to the resistance adjustment circuit of at least one embodiment of the present disclosure, the second PWM waveform and the first PWM waveform have the same period; in a high level period of a first PWM waveform of one cycle, a falling edge of the second PWM waveform precedes a falling edge of the first PWM waveform.

According to the resistance adjustment circuit of at least one embodiment of the present disclosure, a rising edge of the second PWM waveform follows a rising edge of the first PWM waveform.

According to the resistance adjustment circuit of at least one embodiment of the present disclosure, the period of the second PWM waveform is at least twice the period of the first PWM waveform; a falling edge of the second PWM waveform precedes a falling edge of the first PWM waveform corresponding to a high level period of the first PWM waveform.

According to the resistance adjustment circuit of at least one embodiment of the present disclosure, a rising edge of the second PWM waveform follows a rising edge of the first PWM waveform corresponding to a high level period of the first PWM waveform.

According to an aspect of the present disclosure, there is provided a reference resistance network comprising:

at least two adjusting resistors, wherein the at least two adjusting resistors are arranged in series;

resistance adjusting circuits, the number of which is smaller than the number of adjusting resistors; and

the resistance adjusting circuit controls the on-off of the second switching device so as to short-circuit the adjusting resistance connected with the second switching device in parallel when the second switching device is opened;

the resistance adjusting circuit is the resistance adjusting circuit.

According to the reference resistor network of at least one embodiment of the present disclosure, the second switching device is an MOS transistor, a source and a drain of the MOS transistor are respectively connected to two ends of the adjusting resistor, and the resistor adjusting circuit is connected to a gate of the MOS transistor.

According to the reference resistance network of at least one embodiment of the present disclosure, the output terminal of the latch is connected to the gate of the MOS transistor.

According to an aspect of the present disclosure, a battery management system is provided, which includes the above resistance adjustment circuit or the above reference resistance network, and obtains a reference resistance through the resistance adjustment circuit or the reference resistance network, so as to detect whether overcurrent or overvoltage according to the obtained reference resistance.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a reference voltage circuit in the prior art;

FIG. 2 is a schematic diagram of a prior art laser trimming technique for thin film resistors;

FIG. 3 is a schematic diagram of a prior art fuse trim circuit;

FIG. 4 is a schematic diagram of a resistance adjustment circuit of the present disclosure;

FIG. 5 is a schematic diagram of another configuration of the resistance adjustment circuit of the present disclosure;

FIG. 6 is a schematic diagram of a plurality of resistance adjustment circuits of the present disclosure;

FIG. 7 is a schematic diagram of a reference resistor network of the present disclosure;

FIG. 8 is a flow chart of a detection method of the present disclosure;

the reference numbers in the figures are in particular:

1 fuse resistor

2 first electronic switch

3 pull-up resistor

4 first switching device

5 adjusting pad

6 second electronic switch

7 first inverter

8 second inverter

9 third electronic switch

10 third inverter

11 comparator

12 adjusting resistance

13 second switching device

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

Fig. 4 is a schematic diagram of a resistance adjustment circuit of the present disclosure.

The resistance adjustment circuit shown in fig. 4 includes: a fuse resistor 1, the fuse resistor 1 being capable of being blown by a voltage applied across the fuse resistor 1; the first electronic switch 2 is arranged on a circuit of the fusing resistor 1 connected with a power supply or grounded; wherein a first PWM waveform is applied to the first electronic switch 2 such that the resistance adjusting circuit is intermittently switched in to the power supply.

In the present disclosure, the fuse resistor 1 may be a fuse resistor or a polysilicon resistor, and thus, only when the first electronic switch 2 is at a high level, there is a direct current. Assuming that the first PWM waveform with the duty ratio d is input to the first electronic switch 2, and when the first electronic switch 2 is at the high level, the dc current is I1, the equivalent dc current is I1 × d, so that the dc current can be greatly reduced, and the requirement of low power consumption can be met.

In the present disclosure, the resistance adjustment circuit further includes a pull-up resistor 3, and the pull-up resistor 3 is disposed in a circuit between the fuse resistor 1 and a power supply. As an example, one end of the fuse resistor 1 is grounded, the other end is connected to one end of the pull-up resistor 3, and the other end of the pull-up resistor 3 is connected to a power supply through the first electronic switch 2.

On the other hand, the other end of the fuse resistor 1 is also connected to a pad 5 through a first switching device 4, so that the fuse resistor 1 can be blown when a voltage is applied to the pad 5 and the first switching device 4 is in a conductive state.

Preferably, when controlling the first switching device 4 of the present disclosure, the control may be performed through an I2C interface, so that only two pins are needed to selectively turn on the plurality of first switching devices 4, thereby greatly saving pin resources.

That is, the I2C interface outputs T0 TX, only 1 of which is at high level, and the high level signal turns on the corresponding first switch device 4(NMOS) in fig. 4, and since a voltage is applied between the pad 5 and the power ground in fig. 4, a large current can only blow through the fuse connected to the first switch device 4 (NMOS); and, if a plurality of fuse resistors need to be blown, the above process is repeated.

In the present disclosure, a latch is connected to one end of the pull-up resistor 3 connected to the fusing resistor 1, so that a voltage value at a connection point of the pull-up resistor 3 and the fusing resistor 1 is stably output to the outside through the latch.

Preferably, the resistance adjustment circuit further includes a second electronic switch 6, where the second electronic switch 6 is disposed in a circuit where the fuse resistor 1 is connected to the latch, so that after sampling of the latch, the second electronic switch 6 is turned off, and thus, a level signal can be continuously output to a corresponding NMOS of the right resistor string, and a resistance value between the AB points is guaranteed to be a modified voltage.

More preferably, the latch comprises: a first inverter 7, wherein the input end of the first inverter 7 is connected with the second electronic switch 6; the input end of the second inverter 8 is connected to the output end of the first inverter 7, and the output end of the second inverter 8 is connected to the input end of the first inverter 7 through a third electronic switch 9; and a third inverter 10, an input end of the third inverter 10 is connected to an output end of the first inverter 7; wherein the third PWM waveform applied to the third electronic switch 9 is in anti-phase to the second PWM applied to the second electronic switch 6.

And, in order to realize latch voltage acquisition, need to control first PWM waveform and second PWM waveform.

Specifically, in one aspect, the second PWM waveform and the first PWM waveform have the same period; in the same period, the time axis of the high level signal of the second PWM waveform is included in the time of the high level signal of the first PWM waveform; that is, the rising edge time of the second PWM waveform is after the rising edge time of the first PWM waveform, and the falling edge time of the second PWM waveform is before the falling edge time of the first PWM waveform.

On the other hand, the period of the second PWM waveform may also be at least twice the period of the first PWM waveform, the time axis of the high-level signal of the second PWM waveform being included in the time axis of the high-level signal of the first PWM waveform, i.e., corresponding to the high-level period of the first PWM waveform, the rising edge of the second PWM waveform following the rising edge of the first PWM waveform, the falling edge of the second PWM waveform preceding the falling edge of the first PWM waveform.

Thus, when the first PWM waveform is at a high level, pull-up resistor 3 is connected to the power supply, and it is detected whether or not fuse resistor 1 is blown. Then, the second PWM waveform is high, and the voltage at the connection point of pull-up resistor 3 and fuse resistor 1 is sampled: if the fuse resistor is blown, the supply voltage will be sampled, otherwise the GND voltage will be sampled.

Fig. 5 is a schematic diagram of another structure of the resistance adjustment circuit of the present disclosure.

In the present disclosure, the resistance adjustment circuit shown in fig. 5 further includes a comparator 11, where the comparator 11 is disposed in a circuit between the fuse resistor 1 and the second electronic switch 6, that is, one input terminal of the comparator 11 is connected to a connection point of the pull-up resistor 3 and the fuse resistor 1, the other input terminal of the comparator 11 is connected to a reference voltage, and an output terminal of the comparator 11 is connected to the second electronic switch 6, so that the voltage at the connection point of the pull-up resistor 3 and the fuse resistor 1 can be more accurately collected as a high level or a low level through the setting of the comparator 11.

Fig. 6 is a schematic diagram of a plurality of resistance adjustment circuits of the present disclosure.

Referring to fig. 6, when a plurality of resistance adjustment circuits of the present disclosure are used, the adjustment pad 5 and the power source are common components, and thus a plurality of resistance adjustment circuits are disposed in series therebetween.

According to another aspect of the present disclosure, there is provided a resistance adjustment method, which may be implemented by the above resistance adjustment circuit, the resistance adjustment method including: selectively applying a voltage across the fuse resistor 1 according to a desired resistance value to fuse the fuse resistor 1; providing a first PWM waveform to the first electronic switch 2; and to provide a second PWM waveform to the second electronic switch 6; wherein the second PWM waveform and the first PWM waveform have the same period; in a high level time period of a first PWM waveform of one cycle, a falling edge of the second PWM waveform is located before a falling edge of the first PWM waveform; or, the period of the second PWM waveform is at least twice the period of the first PWM waveform; a falling edge of the second PWM waveform precedes a falling edge of the first PWM waveform corresponding to a high level period of the first PWM waveform.

Of course, since some resistors do not need to be adjusted, fuse resistor 1 in the resistor adjustment circuit may not be fused. Of course, in most cases, at least one fuse resistor 1 needs to be blown.

On the other hand, when the periods of the second PWM waveform and the first PWM waveform are the same, the rising edge of the second PWM waveform is after the rising edge of the first PWM waveform, that is, after the resistance adjustment circuit is connected to the power supply, the latch is started again.

Also, a rising edge of the second PWM waveform follows a rising edge of the first PWM waveform corresponding to a high level period of the first PWM waveform.

Fig. 7 is a schematic structural diagram of a reference resistor network according to the present disclosure.

According to another aspect of the present disclosure, there is provided a reference resistance network as shown in fig. 7, including: at least two adjusting resistors 12, wherein the at least two adjusting resistors 12 are arranged in series; resistance adjusting circuits, the number of which is smaller than the number of adjusting resistors; and a second switching device 13, the resistance adjustment circuit controlling the on/off of the second switching device 13 to short-circuit the adjustment resistance 12 connected in parallel with the second switching device 13 when the second switching device 13 is opened; the resistance adjusting circuit is the resistance adjusting circuit.

Preferably, the number of the resistance adjustment circuits is 1 less than the number of the adjustment resistors 12, that is, the other adjustment resistors 12 correspond to one resistance adjustment circuit except for the first adjustment resistor 12.

In this disclosure, the second switching device 13 is an MOS transistor, a source and a drain of the MOS transistor are respectively connected to two ends of the adjusting resistor 12, the resistor adjusting circuit is connected to a gate of the MOS transistor, for example, an output end of the latch is connected to the gate of the MOS transistor; furthermore, the output end of the third inverter of the latch is connected to the gate of the MOS transistor.

Fig. 8 is a flow chart of the detection method of the present disclosure.

According to another aspect of the present disclosure, referring to fig. 8, the present disclosure provides a detection method for detecting overvoltage or overcurrent of a battery through a battery overvoltage/overcurrent detection circuit, where the battery overvoltage/overcurrent detection circuit includes a reference resistor and the reference resistor network, and the detection method includes: closing the reference resistor network, and detecting whether the battery is in overvoltage or overcurrent or not based on the reference voltage obtained by the reference resistor; and if the detection result is overvoltage or overcurrent, starting the reference resistance network, and carrying out overvoltage or overcurrent detection again based on the reference voltage obtained by the reference resistance network.

Furthermore, after the overvoltage or overcurrent detection process is finished by adopting the reference resistance network, the reference resistance network is closed to reduce the power consumption.

According to another aspect of the present disclosure, the present disclosure further provides a battery management system, which includes the above resistance adjusting circuit or the above reference resistance network, and obtains a reference resistance through the resistance adjusting circuit or the reference resistance network, so as to detect whether overcurrent or overvoltage according to the obtained reference resistance.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. A resistance adjustment circuit, comprising:

a fuse resistor that is fusible by a voltage applied across the fuse resistor;

2. The resistance adjustment circuit of claim 1, wherein one end of the fuse resistor is connected to ground and the other end is connected to the adjustment pad through the first switching device.

3. The resistance adjustment circuit of claim 1, wherein the latch comprises:

4. The resistance adjustment circuit of claim 3, further comprising:

a comparator disposed in the circuit between the fuse resistor and the second electronic switch.

5. The resistance adjustment circuit of claim 4, wherein the second PWM waveform and the first PWM waveform have the same period; in a high level period of a first PWM waveform of one cycle, a falling edge of the second PWM waveform precedes a falling edge of the first PWM waveform.

6. The resistance adjustment circuit of claim 5, wherein a rising edge of the second PWM waveform follows a rising edge of the first PWM waveform.

7. The resistance adjustment circuit of claim 4, wherein the period of the second PWM waveform is at least twice the period of the first PWM waveform; a falling edge of the second PWM waveform precedes a falling edge of the first PWM waveform corresponding to a high level period of the first PWM waveform.

8. The resistance adjustment circuit of claim 7, wherein a rising edge of the second PWM waveform follows a rising edge of the first PWM waveform corresponding to a high period of the first PWM waveform.

9. A reference resistor network, comprising:

wherein the resistance adjustment circuit is the resistance adjustment circuit of any one of claims 1-8.

10. A battery management system comprising the resistance adjustment circuit of any one of claims 1 to 8 or the reference resistance network of claim 9, and deriving a reference resistance from the resistance adjustment circuit or the reference resistance network so as to detect whether overcurrent or overvoltage is generated based on the derived reference resistance.