CN112072757A - VDMOS device, control circuit, battery management chip and electrical equipment - Google Patents

VDMOS device, control circuit, battery management chip and electrical equipment Download PDF

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Publication number
CN112072757A
CN112072757A CN202011024951.4A CN202011024951A CN112072757A CN 112072757 A CN112072757 A CN 112072757A CN 202011024951 A CN202011024951 A CN 202011024951A CN 112072757 A CN112072757 A CN 112072757A
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China
Prior art keywords
mosfet
sampling
voltage
charging
current
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CN202011024951.4A
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Chinese (zh)
Inventor
乔明
陈勇
张发备
周号
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Zhuhai Maiju Microelectronics Co Ltd
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Zhuhai Maiju Microelectronics Co Ltd
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Priority to CN202011024951.4A priority Critical patent/CN112072757A/en
Publication of CN112072757A publication Critical patent/CN112072757A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The present disclosure provides a VDMOS device for controlling a charging current and a discharging current of a battery, including: a substrate of a first conductivity type; an epitaxial layer disposed on the substrate and of a first conductivity type; a first cell structure region including a cell structure formed in the epitaxial layer to constitute a charging MOSFET serving as a charging switch; a second cell structure region including a cell structure formed in the epitaxial layer to constitute a discharge MOSFET serving as a discharge switch; and a third cell structure region including cell structures formed in the epitaxial layer to constitute a sampling MOSFET for collecting current flowing through the charging MOSFET and the discharging MOSFET. The disclosure also provides a control circuit, a battery management chip and an electrical device.

Description

VDMOS device, control circuit, battery management chip and electrical equipment
Technical Field
The disclosure relates to a VDMOS device, a control circuit, a battery management chip and an electrical device.
Background
When controlling charging and discharging of a battery such as a lithium battery, it is necessary to measure a charging and discharging current of the battery for safety, battery life, and the like. An external resistor is usually required to detect the charging current and the discharging current.
In the prior art, when an external detection resistor is used for detecting a charging current and a discharging current (for example, the detection resistor and a charging and discharging switch are connected in series in a current loop), the detection resistor needs to be connected in series in the current loop, so that the power consumption of the detection resistor is large under the condition of large charging and discharging current.
The current may be detected by the on-resistance of the charge/discharge switch, but the on-resistance must be sufficiently large to collect a sufficiently large detection voltage for detection. If the on-resistance is large, the power consumption generated by the charge and discharge switch is inevitably large.
In addition, in terms of filter protection, fig. 19 shows an overcurrent protection circuit for lithium battery protection in the prior art.
When the battery is normally discharged, the voltage of the output OD and OC ports of the protection switch driving circuit is usually VDD, 5V or 15V, OD and OC are respectively connected to the grid (G) of MOSFETs M1 and M2, at this time, M1 and M2 work in a linear region, the drain (D) and source (S) of M1 and M2 are equivalent to an on-resistance with a resistance value of RON. Discharge current IdsgThe voltage of the P-end is higher when the P-end flows to the B-end, and when the voltage difference (I) between the P-end and the B-end is detecteddsg*RON) When a certain limit is reached, the OD voltage changes from VDD to B-, OC still holds VDD potential, so that the discharge switch M1 is turned off. Similarly, when the battery is normally charged, the gates (G) of M1, M2 are at the battery voltage VDD. The current flows from the B-terminal to the P-terminal, the voltage of the P-terminal is lower when the voltage difference (I) between the B-terminal and the P-terminalchg*RON) To a certain limit, the OC voltage is changed from VDD to B-OD holding the VDD potential, so that the charge switch M2 is turned off.
However, the on-resistance of the MOSFETs M1 and M2 is related to the battery temperature and the battery voltage. If the overcurrent is judged by only detecting the pressure difference between the B-end and the P-end, the error can reach more than +/-30 percent.
In addition, in the prior art, there is also a drain-source voltage V of the sense MOSFETs M1 and M2DSThe charge and discharge current scheme is sampled.
The basic principle of sampling the charge and discharge current according to the on-resistance of the MOSFET is shown in fig. 20 (taking NMOS as an example for explanation, the same principle is applied to PMOS, and details are not described here).
IgIs the current flowing from VCC voltage to the NMOS gate (G), since the NMOS gate is in high impedance state and the current is short circuited, therefore IgAll flow directions RgThen VGS＝Ig*Rg. When I isg*Rg0 or < VTH(NMOS on threshold voltage), NMOS is off, which is not on because of the high resistance state. When I isg*Rg＞VTH(NMOS on threshold voltage), the NMOS transistor is turned on, and starts to conduct current. When I isg*Rg＞VDS(NMOS Source-Drain Voltage Difference), Ig*Rg＞VTHThe NMOS works in a deep linear region, and the NMOS is equivalent to a voltage-controlled resistor. On-resistance and VGSThe relationship of (1) is: ron＝1/[μn*Cox*W*(VGS-VTH)/L]Wherein, munIs the mobility of the charge carriers, CoxIs unit capacitance of gate, VTHTurn on threshold voltage, V, for NMOSGSIs the gate-source voltage, W is the channel geometry width of the NMOS, and L is the channel geometry length of the NMOS. Then, when there is a current IdsWhen the current flows through the MOSFET switch, the voltage difference V between the drain (D) and the source (S)DS＝Ids*Ron＝Ids/[μn*Cox*(W/L)*(VGS-VTH)]。
From the above formula, it can be seen that the source-drain voltage difference V of the MOSFET switch is detectedDSThe charge/discharge current is sampled. However, the problem if the charging/discharging current is sampled directly with the on-resistance of the charging/discharging MOSFET switch is as follows:
1. the electron mobility μ of discrete MOSFET switches cannot be known accurately in advancenWidth to length ratio W/L, threshold turn-on voltage VTHGrid unit capacitance CoxTherefore, even if the source-drain voltage difference V is accurately measuredDSThe charging and discharging current cannot be accurately obtained because of Ids＝VDS*μn*Cox*(W/L)*(VGS-VTH). The above parameters are usually the process and design parameters of the discrete MOSFET manufacturers, and are not published to the outside.
2. Electron mobility μnThreshold turn-on voltage VTHGrid unit capacitance CoxThe resistance of the MOSFET switch changes with temperature, that is, the on-resistance of the same MOSFET switch is different at different temperature points. That is, at different temperature points, the same source-drain voltage difference VDSThe current magnitude corresponding to different charging and discharging is because the resistance of the MOSFET switch changes with the temperature. Therefore, the magnitude of the charging and discharging currents at all the different temperature points cannot be obtained in advance by measuring the resistance of the MOSFET at one temperature point.
3. Electron mobility μ of the same type of discrete MOSFET switches of the same or different batchesnThreshold turn-on voltage VTHGrid unit capacitance CoxAll have a variance that is typically gaussian due to manufacturing process variations. That is, the on-resistance of the same type of discrete MOSFET switch may be different for the same or different batches. Therefore, it is not possible to measure the resistance of one MOSFET in advance to obtain the on-resistance of the same type of discrete MOSFET switch for one batch, the same batch, or different batches.
In view of the problems of the prior art, how to detect the charging and discharging current of the battery with high precision is a technical problem to be solved.
Disclosure of Invention
In order to solve one of the above technical problems, the present disclosure provides a VDMOS device, a control circuit, a battery management chip, and an electrical apparatus.
According to an aspect of the present disclosure, a VDMOS device for controlling a charging current and a discharging current of a battery, includes:
a substrate of a first conductivity type;
an epitaxial layer disposed on the substrate and of a first conductivity type;
a first cell structure region including a cell structure formed in the epitaxial layer to constitute a charging MOSFET serving as a charging switch;
a second cell structure region including a cell structure formed in the epitaxial layer to constitute a discharge MOSFET serving as a discharge switch; and
a third cell structure region including a cell structure formed in the epitaxial layer to constitute a sampling MOSFET for collecting current flowing through the charging MOSFET and the discharging MOSFET.
According to at least one embodiment of the present disclosure, the ratio of the number of cell structures in the third cell structure region to the number of cell structures in the first and second cell structure regions is 1: k is more than or equal to 2.
According to at least one embodiment of the present disclosure, the charging MOSFET and the discharging MOSFET are configured such that drains of the two are connected.
According to at least one embodiment of the present disclosure, the number of the third cell structure region and the sampling MOSFET is one, and the source of the sampling MOSFET is configured to be connected to the source of the charging MOSFET or to the source of the discharging MOSFET, and the drain of the sampling MOSFET is configured to be a sampling terminal of the charging current or the discharging current.
According to at least one embodiment of the present disclosure, the number of the third cell structure region and the sampling MOSFETs is two, and one sampling MOSFET is connected to a drain of the other sampling MOSFET, and a source of the one of the two sampling MOSFETs is configured to be connected to a source of the charging MOSFET or to a source of the discharging MOSFET, and a source of the other sampling MOSFET is configured to be a sampling terminal of a charging current or a discharging current.
According to at least one embodiment of the present disclosure, a well resistor structure is further included to constitute a well resistor, one end of the well resistor is configured to be connected to the source of the other sampling MOSFET, and the other end of the well resistor is configured to be connected to the source of the discharging MOSFET or to the source of the charging MOSFET, and one end of the well resistor is configured to be a sampling end of a discharging current or a charging current.
According to at least one embodiment of the present disclosure, the number of the third cell structure region and the sampling MOSFET is four, wherein
Two sampling MOSFETs in the four sampling MOSFETs, wherein one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the one sampling MOSFET is connected with the source electrode of the charging MOSFET, and the source electrode of the other sampling MOSFET is a charging current sampling end; and
and the other two sampling MOSFETs in the four sampling MOSFETs, one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the one sampling MOSFET is connected with the source electrode of the discharge MOSFET, and the source electrode of the other sampling MOSFET is configured as a discharge current sampling end.
According to at least one embodiment of the present disclosure, the three cell structure regions and the sampling MOSFETs are connected to each other, the source of one sampling MOSFET is connected to one end of one well resistor, the other end of the one well resistor is connected to the source of the charging MOSFET, the other end of the other well resistor is connected to the source of the other sampling MOSFET, the other end of the other well resistor is connected to the source of the discharging MOSFET, the one end of the one well resistor is a charging current sampling terminal, and the one end of the other well resistor is a discharging current sampling terminal.
According to at least one embodiment of the present disclosure, each of the cell structures includes:
the two trenches are respectively provided with a gate oxide layer, polycrystalline silicon and a dielectric layer positioned on the polycrystalline silicon;
a first well region of a second conductivity type and located between the two trenches and over the epitaxial layer; and
a heavily doped region located over the first well region and between the two trenches, the heavily doped region being of a first conductivity type.
According to at least one embodiment of the present disclosure, each of the cell structures includes:
the two trenches are respectively provided with a gate oxide layer, a control grid, a shielding grid, a first dielectric layer and a second dielectric layer, the control grid is positioned on the shielding grid and separated by the first dielectric layer, and the second dielectric layer is positioned on the control grid;
a first well region of a second conductivity type and located between the two trenches and over the epitaxial layer; and
a heavily doped region located over the first well region and between the two trenches, the heavily doped region being of a first conductivity type.
According to another aspect of the present disclosure, a charge and discharge control circuit includes the VDMOS device as described above, the battery is charged and discharged through a first connection terminal and a second connection terminal, the charge and discharge is controlled by controlling a charge and discharge switch formed by the charge MOSFET and the discharge MOSFET, the charge MOSFET and the discharge MOSFET are connected in series on a current path between the battery and the first connection terminal or between the battery and the second connection terminal, wherein a sampling MOSFET and/or a well resistor in the VDMOS device constitute a detection unit of the control circuit, and the control circuit further includes:
a first input end of the comparison unit is connected with a voltage related to the voltage of the first end of the detection unit, a second input end of the comparison unit is connected with a voltage related to the voltage of the first end of the charge and discharge switch, and a second end of the detection unit is connected with a second end of the charge and discharge switch; and
a control logic unit controlling the charging MOSFET and the discharging MOSFET according to the comparison result output by the comparison unit,
and the impedance ratio between the on-resistance value of the charge and discharge switch and the on-resistance value of the detection unit is kept constant.
According to at least one embodiment of the present disclosure, a current ratio between a current flowing through the charge and discharge switch and a current flowing through the detection unit is kept constant.
According to at least one embodiment of the present disclosure, a current ratio between the current flowing through the charge and discharge switch and the current flowing through the detection unit is independent of a system voltage and a system temperature.
According to at least one embodiment of the present disclosure, in case of controlling the discharge current,
the source of the sampling MOSFET of the detection unit is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and a discharge current flows from the charge MOSFET to the discharge MOSFET.
According to at least one embodiment of the present disclosure, when a voltage of a source side of the charging MOSFET is greater than a voltage of a drain side of the sampling MOSFET, a comparison result of the comparison unit is inverted, and the control logic unit controls turn-off of the discharging MOSFET.
According to at least one embodiment of the present disclosure, in case of controlling the charging current,
the source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and a discharge current flows from the discharging MOSFET to the charging MOSFET.
According to at least one embodiment of the present disclosure, when a voltage of a source side of the discharge MOSFET is greater than a voltage of a drain side of the sampling MOSFET, a comparison result of the comparison unit is inverted, and the control logic unit controls turn-off of the charge MOSFET.
According to at least one embodiment of the present disclosure, the circuit further comprises a mirror circuit and a comparator,
a source of the sampling MOSFET is connected to a source of the discharge MOSFET, a drain of the sampling MOSFET is connected to a mirror circuit, a voltage on a drain side of the sampling MOSFET is set equal to a voltage on a source side of the charge MOSFET, a discharge current flows from the charge MOSFET to the discharge MOSFET,
when the voltage of the source side of the charging MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current, the voltage generated based on the mirror current is input to the first input end of the comparator, the reference voltage is input to the second input end of the comparator, and the control logic unit is controlled to turn off the discharging MOSFET according to the comparison result of the comparator.
According to at least one embodiment of the present disclosure, the circuit further comprises a mirror circuit and a comparator,
a source of the sampling MOSFET is connected to a source of the charging MOSFET, a drain of the sampling MOSFET is connected to a mirror circuit, a voltage on a drain side of the sampling MOSFET is set equal to a voltage on a source side of the discharging MOSFET, and a charging current flows from the discharging MOSFET to the charging MOSFET,
when the voltage of the source side of the discharge MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current, the voltage generated based on the mirror current is input to the first input end of the comparator, the reference voltage is input to the second input end of the comparator, and the control logic unit is controlled to turn off the charge MOSFET according to the comparison result of the comparator.
According to at least one embodiment of the present disclosure, in case that the detection cell includes a well resistor and a sampling MOSFET,
in case of controlling a discharge current, a connection point of the well resistor and the sampling MOSFET is connected to a first input terminal of the comparison unit, a second input terminal of the comparison unit is connected to a reference voltage generated based on a source side voltage of the discharge MOSFET, a comparison result of the comparison unit is inverted when a voltage of the first input terminal of the comparison unit is greater than a voltage of the second input terminal, and the control logic unit controls turn-off of the discharge MOSFET.
According to at least one embodiment of the present disclosure, the well resistor has a much smaller resistance than the on-resistance of the sampling MOSFET.
According to at least one embodiment of the present disclosure, in case that the detection cell includes a well resistor and a sampling MOSFET,
in the case of controlling the charging current, and a connection point of the well resistor and the sampling MOSFET is connected to a first input terminal of the comparison unit, a second input terminal of the comparison unit is connected to a reference voltage generated based on a source side voltage of the charging MOSFET, when a voltage of the first input terminal of the comparison unit is greater than a voltage of the second input terminal, a comparison result of the comparison unit is inverted, and the control logic unit controls turn-off of the charging MOSFET.
According to at least one embodiment of the present disclosure, the well resistor has a much smaller resistance than the on-resistance of the sampling MOSFET.
According to still another aspect of the present disclosure, a battery management chip includes the above charge and discharge control circuit.
According to at least one embodiment of this disclosure, still include the charge and discharge switch.
According to yet another aspect of the present disclosure, an electrical device includes:
a battery management chip as above; and
the battery is used for supplying power to other components of the electrical equipment, and the battery management chip is used for managing the battery.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 2 shows a circuit diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 3 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 5 shows a circuit diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 6 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 7 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 8 shows a schematic diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 9 shows a VDMOS device circuit diagram according to one embodiment of the present disclosure.
Fig. 10 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 11 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 12 shows a schematic diagram of a VDMOS device according to one embodiment of the disclosure.
Fig. 13 shows a schematic application diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 14 shows an application schematic diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 15 shows a schematic diagram of a VDMOS device according to one embodiment of the present disclosure.
Fig. 16 shows a VDMOS device circuit diagram according to one embodiment of the present disclosure.
Fig. 17 shows an application schematic diagram of a VDMOS device according to an embodiment of the present disclosure.
Fig. 18 shows a schematic diagram of a VDMOS device according to one embodiment of the disclosure.
Fig. 19 shows a schematic diagram of a battery management system according to the prior art.
Fig. 20 shows a schematic diagram of the on-resistance of a prior art NMOS transistor.
Detailed Description
The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.
The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.
When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.
According to an embodiment of the present disclosure, a VDMOS device integrating a current sampling function is provided.
Fig. 1 shows a VDMOS device having a current sampling function according to a first embodiment of the present disclosure.
As shown in fig. 1, the VDMOS device 100 may include: substrate 102, epitaxial layer 104, and cell structures, wherein each cell structure includes a gate oxide layer 106, polysilicon 108, a dielectric layer 110, a first well region 112, a second well region 114, and a heavily doped region 116.
The substrate 102 may be a silicon wafer and it is a first conductivity type substrate. An epitaxial layer 104 is prepared on the substrate 102, which is of the first conductivity type. A plurality of cell structures are disposed in the epitaxial layer 104, wherein each cell structure includes two trenches with a gate oxide layer 106, polysilicon 108, and a dielectric layer 110 disposed in each trench. The gate oxide layer 106 is located outside the polysilicon 108 and a dielectric layer 110 is disposed over the polysilicon 108.
A second well region 114 is disposed above the epitaxial layer 104 and between the two trenches, the second well region 114 being of the second conductivity type. And a heavily doped region 116 is disposed above second well region 114, heavily doped region 116 having a doping concentration higher than that of epitaxial layer 104, and heavily doped region 116 being of the first conductivity type.
The first well regions 112 are respectively disposed outside the two trenches, wherein the conductivity type of the first well regions 112 is the second conductivity type.
In addition, source electrode 118 may be drawn from heavily doped region 116. And a drain electrode 120 is provided on the other side of the substrate 102.
As shown in fig. 1, the VDMOS device may be integrated with a charging MOSFET MD, a discharging MOSFET MC, a first sampling MOSFET MS1, a second sampling MOSFET MS2, a third sampling MOSFET MS3, and a fourth sampling MOSFET MS 4.
The charging MOSFET MD and the discharging MOSFET MC may respectively include a plurality of cell structures, and the first sampling MOSFET MS1, the second sampling MOSFET MS2, the third sampling MOSFET MS3, and the fourth sampling MOSFET MS4 may respectively include one or more cell structures, wherein a ratio of the number of cell structures of the first sampling MOSFET MS1, the second sampling MOSFET MS2, the third sampling MOSFET MS3, and the fourth sampling MOSFET MS4 to the number of cell structures of the charging MOSFET MD and the discharging MOSFET MC may be 1: k, wherein K is greater than or equal to 1.
Through the structure of the VDMOS device, the proportion of the currents flowing through the sampling MOSFETs MS1-MS4 and the charge and discharge switches MD and MS can be adjusted by adjusting the number of the unit cells, so that the accurate sampling of the currents is realized.
The VDMOS device structure shown in fig. 1 corresponds to the application circuit shown in fig. 2, which can be used for charge and discharge control of a battery in a battery management system.
As shown in fig. 2, MD in the application circuit is used as a discharge MOSFET, MC is used as a charge MOSFET, MS1 and MS2 are used as discharge current sampling branches, and MS3 and MS4 are used as charge current sampling branches.
Fig. 3 shows the use of the application circuit in a battery management system. The charge and discharge control unit may include a detection unit and a comparator CMP2 configured of MS3 and MS4, a resistor R2, and the like.
In the case of discharge, a discharge current Idsg flows from the P-terminal to the B-terminal.
A first input terminal of the comparator CMP2 is connected to a voltage related to the detection result of the detection unit, and a second input terminal of the comparator CMP2 is connected to the reference voltage VREF 2. The detection voltage generated from the detection current Idsg/K obtained from MS3 and MS4 and the resistance value of the resistor R2 is compared with the reference voltage VREF 2. When the voltage of the first input terminal of the comparator CMP2 is greater than the voltage of the second input terminal, the comparison result of the comparator CMP2 is inverted and the control logic unit controls the opening of the discharge switch MD. The MOSFET MD is turned off by the drive unit outputting a control signal OD. For example, the OD voltage changes from VDD to B-, OC still holds VDD potential.
The MOSFETs MS3 and MS4 are the same type of MOSFETs as the MOSFETs MD and MC. The ratio of the on-resistance of the MOSFETs MS3 and MS4 to the on-resistance of the MOSFETs MD and MC is constant K: 1.
since the current flowing through the MOSFETs MD and MC is VREF2/R2 × K when the MOSFETs MD are turned off. VREF2 and R2 are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through MOSFETs MD and MC will not change, i.e., the detected discharge current will not change with voltage or temperature.
In the charging case, the charging current Ichg flows from the B-terminal to the P-terminal.
A first input terminal of the comparator CMP1 is connected to a voltage related to the detection result of the detection unit, and a second input terminal of the comparator CMP1 is connected to the reference voltage VREF 1. The detection voltage generated from the detection current Ichg/K obtained from MS1 and MS2 and the resistance value of the resistor R1 is compared with the reference voltage VREF 1. When the voltage of the first input terminal of the comparator CMP1 is greater than the voltage of the second input terminal, the comparison result of the comparator CMP1 is inverted and the control logic unit controls the turn-off of the MOSFET MC. The MOSFET MC is turned off by the drive unit outputting the control signal OC. For example, the OC voltage changes from VDD to P-OD, which still holds the VDD potential.
The MOSFETs MS1 and MS2 are the same type of MOSFETs as the MOSFETs MD and MC. The ratio of the on-resistance of the MOSFETs MS1 and MS2 to the on-resistance of the MOSFETs MD and MC is constant K: 1.
since the current flowing through MOSFETs MD and MC is VREF1/R1 × K when MOSFET MC is turned off. VREF1 and R1 are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through MOSFETs MD and MC will not change, i.e., the detected charging current will not change with voltage or temperature.
Fig. 4 shows a VDMOS device having a current sampling function according to a second embodiment of the present disclosure.
As shown in fig. 4, the VDMOS device 100 may include: substrate 102, epitaxial layer 104, and cell structures, wherein each cell structure includes a gate oxide layer 106, polysilicon 108, a dielectric layer 110, a first well region 112, a second well region 114, and a heavily doped region 116.
The substrate 102 may be a silicon wafer and it is a first conductivity type substrate. An epitaxial layer 104 is prepared on the substrate 102, which is of the first conductivity type. A plurality of cell structures are disposed in the epitaxial layer 104, wherein each cell structure includes two trenches with a gate oxide layer 106, polysilicon 108, and a dielectric layer 110 disposed in each trench. The gate oxide layer 106 is located outside the polysilicon 108 and a dielectric layer 110 is disposed over the polysilicon 108.
A second well region 114 is disposed above the epitaxial layer 104 and between the two trenches, the second well region 114 being of the second conductivity type. And a heavily doped region 116 is disposed above second well region 114, heavily doped region 116 having a doping concentration higher than that of epitaxial layer 104, and heavily doped region 116 being of the first conductivity type.
The first well regions 112 are respectively disposed outside the two trenches, wherein the conductivity type of the first well regions 112 is the second conductivity type.
In addition, source electrode 118 may be drawn from heavily doped region 116. And a drain electrode 120 is provided on the other side of the substrate 102.
As shown in fig. 4, the VDMOS device may be integrated with a charging MOSFET MD, a discharging MOSFET MC, and a first sampling MOSFET MS 1.
The charging MOSFET MD and the discharging MOSFET MC may respectively include a plurality of cell structures, and the first sampling MOSFET MS1 includes one or more cell structures, wherein a ratio of the number of cell structures of the first sampling MOSFET MS1 to the number of cell structures of the charging MOSFET MD and the discharging MOSFET MC may be 1: k, wherein K is greater than or equal to 1.
Through the structure of the VDMOS device, the proportion of the currents flowing through the sampling MOSFET MS1 and the charge and discharge switches MD and MS can be adjusted by adjusting the number of the unit cells, so that the accurate sampling of the currents is realized.
The VDMOS device structure shown in fig. 4 corresponds to the application circuit shown in fig. 5, which can be used for charge and discharge control of a battery in a battery management system.
As shown in fig. 5, MD in the application circuit is used as a discharge MOSFET, MC is used as a charge MOSFET, and MS1 is used as a charging current sampling branch.
Fig. 6 shows an application of the VDMOS device structure shown in fig. 4.
The application is used for controlling the battery charging overcurrent.
The charging and discharging control unit can comprise a detection unit formed by a MOSFET MS1 and a comparator, wherein the second input end of the comparator is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparator is connected with the voltage related to the voltage of the second end of the charging and discharging switch, and the first end of the detection unit is connected with the first end of the charging and discharging switch. The charge and discharge switches are a charge MOSFET MC and a discharge MOSFET MD.
In this embodiment, the source of the MOSFET M1 of the detection cell is connected with a constant current Idc that is independent of the voltage and temperature of the system. And the charging current Ichg flows from the second terminal of the charge and discharge switch (the right end of the discharge switch, i.e., the negative terminal B-terminal of the battery is shown in the figure) to the first terminal P-terminal. When the voltage of the second end of the charge and discharge switch is greater than the detection voltage of the detection unit, the comparison result of the comparator is inverted, and the control logic unit controls the charging MOSFET MC to be switched off.
Specifically, a constant current Idc that generates a voltage Vb across the MOSFET MS1 regardless of the voltage and temperature of the system can be generated inside the chip. Since the MOSFETs MD, MC, and MS1 are MOSFETs of the same type, even if the temperature or voltage of the system changes, the sum of the equivalent on-resistance of the MOSFET MS1 and the equivalent on-resistance of the MOSFETs MD and MC can be maintained at a constant value K: 1.
the comparator is used for voltage Vb and voltage VB- (voltage of a B-terminal), when VB-is larger than Vb, the output signal of the comparator is overturned, and after the control logic unit receives the overturned signal, the control logic unit outputs a control signal OC to turn off the charging MOSFET through the driving unit. For example, the OC voltage changes from VDD to P-OD, which still holds the VDD potential.
Since the current through the MOSFETs MD, MC is Idc × K when the charging MOSFET is turned off. And Idc is a constant current and K is a constant ratio, so that the two constant values do not change when the system voltage and temperature change, and thus the current flowing through the MOSFETs MD and MC does not change, that is, the detected charging overcurrent does not change with the voltage or the temperature.
As a modified embodiment of this embodiment, two or more sampling MOSFETs may be used, so that the structure of the VDMOS device may be modified accordingly.
According to the third embodiment of the present disclosure, it is also possible to provide only the sampling MOSFET on the side of the discharge MOSFET, and thus detect the discharge current, for example, only the sampling MOSFET on the side of the discharge MOSFET MD is included, as in the principle shown in fig. 5.
Fig. 7 shows an example of an application including one sampling MOSFET.
This example is used to control battery discharge over-current.
The charging and discharging control unit can comprise a detection unit and a comparator, wherein the detection unit is composed of a sampling MOSFET, a first input end of the comparator is connected with a voltage related to the voltage of a first end of the detection unit, a second input end of the comparator is connected with a voltage related to the voltage of a first end of the charging and discharging switch, and a second end of the detection unit is connected with a second end of the charging and discharging switch. The charge and discharge switches are a charge MOSFET and a discharge MOSFET.
In this embodiment, the detecting unit is a sampling MOSFET, the source of the sampling MOSFET is connected to the second end of the charge and discharge switch (the right end of the discharge switch, i.e. the negative terminal B-end of the battery is shown in the figure), and the drain of the sampling MOSFET of the detecting unit is connected to a constant current Idc, which is independent of the voltage and temperature of the system.
And the discharge current Idsg flows from a first terminal (shown in the figure as a negative terminal connected to an external charger or an external load, i.e., a P-terminal) of the charge and discharge switch to a second terminal. When the voltage of the first end of the charge and discharge switch is greater than the voltage of the drain side of the sampling MOSFET of the detection unit, the comparison result of the comparator is inverted, and the control logic unit controls the disconnection of the discharge MOSFET.
Specifically, a constant current Idc that generates a voltage Va (voltage at the drain terminal of the sampling MOSFET) across the sampling MOSFET can be generated inside the chip regardless of the voltage and temperature of the system. Since the charge and discharge switches and the sampling MOSFET are the same type of MOSFET, even if the temperature or voltage of the system changes, the sum of the equivalent on-resistance of the sampling MOSFET and the equivalent on-resistance of the charge and discharge switches can be maintained at a constant value K: 1.
the comparator is used for voltage Va and voltage VP- (voltage of P-end), when VP-is larger than Va, the output signal of the comparator is inverted, and after the control logic unit receives the inverted signal, the control logic unit outputs a control signal OD to turn off the discharge MOSFET. For example, the OD voltage changes from VDD to B-, OC still holds VDD potential.
When the discharge MOSFET is turned off, the current flowing through the charge and discharge switch is Idc. And Idc is a constant current, and K is a constant ratio, so that the two constant values do not change when the system voltage and the temperature change, and the current flowing through the charge and discharge switch does not change, namely the detected discharge overcurrent does not change along with the voltage or the temperature.
Fig. 8 shows a VDMOS device structure according to a fourth embodiment of the present disclosure. The difference from the device structure shown in fig. 4 is that the well resistance R is increased. The same portions as those of fig. 4 will not be described again. The well resistive structure includes a second well region 114 disposed in epitaxial layer 104, the second well region 114 being of the second conductivity type. And a heavily doped region 116 is disposed in second well region 114, heavily doped region 116 having a doping concentration higher than that of epitaxial layer 104, and heavily doped region 116 being of the first conductivity type.
Fig. 9 is a circuit diagram corresponding to the structure of the VDMOS device shown in fig. 8. Fig. 10 shows a practical application of the VDMOS device.
This practical application is used for controlling the battery discharge overcurrent. The discharge current Idsg flows from the P-terminal to the B-terminal.
The charge and discharge control unit may include a detection unit composed of two sampling MOSFETs and a resistor R, and a comparator.
The first input end of the comparator is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparator is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switches are a charge MOSFET MC and a discharge MOSFET MD.
The detection unit comprises a resistor R and MOSFETs MS1 and MS2 connected in series, the number of the MOSFETs connected in series is one or more, and the MOSFETs connected in series can be in the form of one MOSFET or more MOSFETs.
Under the condition of controlling the discharge current, one end of a resistor of a detection unit is connected to the second end of the charge and discharge switch, the other end of the resistor of the detection unit is connected to one end of an MOSFET of the detection unit, the other end of the resistor of the detection unit is connected to the first end of the charge and discharge switch, a connection point of the resistor of the detection unit and the MOSFET is connected to a first input end of a comparator, a second input end of the comparator is connected with a reference voltage generated based on the voltage of the second end of the charge and discharge switch, when the voltage of the first input end of the comparator is larger than the voltage of the second input end, a comparison result of the comparator is inverted, and the control logic unit controls the discharge MOSFET to be disconnected.
The resistance value of the resistor of the detection unit is far smaller than the on-resistance of the MOSFET of the detection unit.
For example, referring to fig. 10, two sampling MOSFETs are connected in series, one sampling MOSFET has its source connected to the P-terminal, its drain connected to the drain of the other sampling MOSFET, its source connected to one end of a resistor R, and the other end of a resistor 533e connected to the B-terminal. The junction of the other sampling MOSFET and resistor R is connected to one input terminal of the comparator, and the other input terminal of the comparator is connected to a reference voltage Vref generated based on VB- (voltage at terminal B). The generation of the reference voltage Vref may be based on a VB-pass voltage generation unit DC (e.g., a voltage with VB-as a reference zero potential, which may be generated inside the chip).
The sampling MOSFET and the MOSFET which is the same as the charge and discharge switch are the same. The ratio of the sum of the conduction impedances of the sampling MOSFETs to the conduction impedance of the charge and discharge switch is constant to K: 1. meanwhile, in order to ensure the precision, the resistance Re of the resistor R is set to be far smaller than the sum of the on-resistance of the sampling MOSFET. Therefore, the voltage Ve of the connection point of the sampling MOSFET is compared with the voltage Vref, when Ve is larger than Vref, the comparator overturns, so that the logic control unit can control the driving unit according to the overturning signal, and the discharging MOSFET is turned off by outputting a control signal OD through the driving unit. For example, the OD voltage changes from VDD to B-, OC still holds VDD potential.
When the discharge MOSFET is turned off, the current flowing through the charge and discharge switch is Vref/Re xK. And Vref and Re are fixed values, and K is a constant ratio, so that when the system voltage and the temperature change, the three values do not change, the current flowing through the charge and discharge switch does not change, namely the detected discharge overcurrent does not change along with the voltage or the temperature.
According to a fifth embodiment of the present disclosure, there is also provided a VDMOS device structure. The fifth embodiment is different from the fourth embodiment in that MOSFETs MS1 and MS2 and a resistor are provided on one side of a discharge MOSFET.
Fig. 11 shows an application of the VDMOS device. For controlling the battery charging overcurrent. The charging current Ichg flows from the B-terminal to the P-terminal.
The charge and discharge control unit may include a detection unit composed of a sampling MOSFET and a resistor, and a comparator.
The first input end of the comparator is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparator is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switches are a charge MOSFET and a discharge MOSFET.
The detection unit comprises a resistor R and sampling MOSFETs which are connected in series, the number of the sampling MOSFETs connected in series is one or more, and the sampling MOSFETs can be in the form of one sampling MOSFET or more sampling MOSFETs.
Under the condition of controlling the charging current, one end of a resistor of the detection unit is connected to a first end of the charging and discharging switch, the other end of the resistor of the detection unit is connected to one end of a sampling MOSFET of the detection unit, the other end of the resistor of the detection unit is connected to a second end of the charging and discharging switch, a connection point of the resistor of the detection unit and the sampling MOSFET is connected to a first input end of the comparator, a second input end of the comparator is connected with a reference voltage generated based on the voltage of the second end of the charging and discharging switch, when the voltage of the first input end of the comparator is larger than the voltage of the second input end, a comparison result of the comparator is inverted, and the control logic unit controls the charging MOSFET to be disconnected.
The resistance value of the resistor of the detection unit is far smaller than the on-resistance of the sampling MOSFET of the detection unit.
For example, referring to fig. 11, two sampling MOSFETs are included in series, one sampling MOSFET having its source connected to the B-terminal and its drain connected to the drain of the other sampling MOSFET, and having its source connected to one end of a resistor R, the other end of the resistor R connected to the P-terminal. The junction of the MOSFET and the resistor is connected to one input of a comparator, and the other input of the comparator is connected to a reference voltage Vref generated based on VP- (voltage of P-terminal). The generation of the reference voltage Vref may be generated based on a VP-pass voltage generation unit (e.g., a voltage with VP-as a reference zero potential, which may be generated inside a chip).
The sampling MOSFET and the charge and discharge switch are the same type of MOSFET. The ratio of the on-resistance of the sampling MOSFET to the on-resistance of the charge and discharge switch is constant as K: 1. meanwhile, in order to ensure the accuracy, the resistance Rf of the resistor is set to be much smaller than the on-resistance of the sampling MOSFET. Therefore, the voltage Vf of the connection point of the sampling MOSFET and the resistor is compared with the voltage Vref, when Vf is larger than Vref, the comparator overturns, so that the logic control unit can control the driving unit according to the overturning signal, and the charging MOSFET is turned off by outputting the control signal OC through the driving unit. For example, the OC voltage changes from VDD to VP-and the OD still holds the VDD potential.
When the charging MOSFET is turned off, the current flowing through the charging and discharging switch is Vref/Rf & ltx & gt K. And Vref and Rf are fixed values, and K is a constant ratio, so that when the system voltage and the temperature change, the three values do not change, the current flowing through the charge and discharge switch does not change, namely the detected charging overcurrent does not change along with the voltage or the temperature.
Fig. 12 shows a VDMOS device structure according to a sixth embodiment of the present disclosure.
This device structure differs from the device structure shown in fig. 4 in that two sampling MOSFETs are included.
Fig. 13 shows an application of the VDMOS device structure shown in fig. 12. For controlling the battery charging overcurrent. The charging current Ichg flows from the B-terminal to the P-terminal.
The charge and discharge control unit may include a detection unit and a comparator.
The first input end of the comparator is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparator is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switches are a charge MOSFET MC and a discharge MOSFET MD.
In this embodiment, the comparator is an operational amplifier, a detection resistor is connected in series between the second input terminal of the operational amplifier and the output terminal of the operational amplifier, one end of the nmosfet of the comparator is connected to the second input terminal of the operational amplifier, the other end of the nmosfet of the comparator is connected to the second end of the charge and discharge switch, and the first input terminal of the operational amplifier is connected to the first end of the charge and discharge switch.
And obtaining the current value of the charging current or the discharging current according to the voltage generated by the detection resistor and the resistance value of the detection resistor.
This will be described in detail with reference to fig. 11. Wherein the detection cells may include sampling MOSFETs MS1 and MS 2. The sampling MOSFETs MS1 and MS2 may be the same type of MOSFET as the charging MOSFET MC and the discharging MOSFET MD.
The source of the MOSFET MS1 is connected to the P-terminal, the drain thereof is connected to the drain of the MOSFET MS2, and the source of the MOSFET MS2 is connected to one input terminal of the operational amplifier. The gate of nmosfet MS1 is connected to control signal OC and the gate of MOSFET MS2 is connected to control signal OD. The other input end of the operational amplifier is connected with the B-end.
The MOSFET MS1 is the same type of MOSFET as the discharge MOSFET MD and the MOSFET MS2 is the same type of MOSFET as the charge MOSFET MC. Therefore, even if the temperature or voltage changes, the ratio of the series equivalent on-resistance of the sampling MOSFETs MS1 and MS2 to the series equivalent on-resistance of the charging MOSFET mc and the discharging MOSFET MD is always maintained at a constant value K: 1. thus, the current flowing through the sampling MOSFET and the current flowing through the charge and discharge switch are constantly kept to be 1: K.
during charging, the external charger is connected between the output positive electrode (P +) of the battery and the output negative electrode (P-) of the battery, and the magnitude of the charging current from the external charger to the battery pack is Ichg (1+ 1/K). The current flowing through the charge and discharge switch is Ichg, and the current flowing through the sampling MOSFET is Ichg/K.
The operational amplifier may set the voltage at the source terminal of MOSFET MS1 to be the same as the voltage at the negative terminal B-of the battery, and since the voltage at the negative terminal B-of the battery pack is at the system "ground" point, V (B-) > is 0.
The negative input of the operational amplifier, i.e., the source terminal voltage of the MOSFET MS1, is the same as the voltage of the negative pole P-of the battery output because of the negative feedback effect of the operational amplifier.
And because the impedance of the input end of the operational amplifier is approximate to infinity, the current of the sampling MOSFET all flows into the sampling resistor R (the resistance value of which is Rh).
Thus, the output voltage V of the operational amplifiersns＝Rh*Ichg/K+V(B-)Rh Ichg/K. Because of VsnsThe value can be obtained by a subsequent voltage sampling circuit, Rh is a designed value of a previous circuit, so that the charging current Ichg flowing through the charging and discharging switch can be accurately obtained, and the influence of the voltage or the temperature of a system can not be caused.
According to a seventh embodiment of the present disclosure, there is also provided a VDMOS device structure.
This device structure differs from that of the sixth embodiment in that two sampling MOSFETs are located on the discharge MOSFET side.
Fig. 14 shows an application diagram according to the present embodiment. For controlling the battery charging overcurrent. The discharge current Idsg flows from the P-terminal to the B-terminal.
The charge and discharge control unit may include a detection unit and a comparator.
The first input end of the comparator is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparator is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switch is a charge and discharge switch.
In this embodiment, the comparator is an operational amplifier, a detection resistor is connected in series between the second input terminal of the operational amplifier and the output terminal of the operational amplifier, one end of the MOSFET of the detection unit is connected to the second input terminal of the operational amplifier and the other end of the MOSFET of the detection unit is connected to the second end of the charge and discharge switch, and the first input terminal of the operational amplifier is connected to the first end of the charge and discharge switch.
And obtaining the current value of the charging current or the discharging current according to the voltage generated by the detection resistor and the resistance value of the detection resistor.
As will be described in detail below with reference to fig. 14. Wherein the detection cells may include sampling MOSFETs MS1 and MS 2. The sampling MOSFETs MS1 and MS2 may be the same type of MOSFET as the charging MOSFET MC and the discharging MOSFET MD. The source of the MOSFET MS1 is connected to the B-terminal, the drain thereof is connected to the drain of the MOSFET MS2, and the source of the MOSFET MS2 is connected to one input terminal of the operational amplifier. The gate of the MOSFET MS1 is connected to the control signal OC, and the gate of the MOSFET MS2 is connected to the control signal OD. The other input end of the operational amplifier is connected with the P-end.
The principle of this embodiment will be explained in detail below.
When charging, the battery is externally connected with an external load, the external load is connected between the output positive pole P + and the output negative pole P-, and the resistance value is RLoadThe discharge current Idsg of the battery thus obtained is [ V (P +) -V (P-)]/RLoad。
The operational amplifier may cause the source terminal voltage of the MOSFET MS1 to be the same as the voltage at the negative P-terminal of the battery output, the nmosfet MS1 being the same type of MOSFET as the discharge MOSFET, and the nmosfet MS2 being the same type of MOSFET as the charge MOSFET. Therefore, even if the temperature or voltage changes, the ratio of the series equivalent on-resistance of the MOSFET MS1 and the MOSFET MS2 to the series equivalent on-resistance of the MOSFET MD and the MOSFET MS is always maintained at a constant value K: 1. thus, the current flowing through the MOSFET MS1 and the MOSFET MS2 and the current flowing through the MOSFET MD and the MOSFET MS are constantly maintained at 1: K.
the negative input of the operational amplifier, i.e., the source terminal voltage of MOSFET MS1, is the same as the negative P-terminal voltage of the battery output because of the negative feedback effect of the operational amplifier.
Since the input impedance of the operational amplifier is approximately infinite, the currents of the MOSFET MS1 and the MOSFET MS2 all flow into the sampling resistor R (resistance value Rg).
Thus, the output voltage V of the operational amplifiersnsRg Idsg/k + V (P-). V (P-) is the P-terminal voltage.
V(P-)＝V(B-)+Idsg*(Ron1+Ron2). V (B-) is the voltage at the B-terminal, Ron1Is the equivalent resistance of MOSFET MD, Ron2Is the equivalent resistance of the MOSFET MS.
The B-terminal is the ground terminal of the battery, so V (B-) can be considered as the "ground" point of the system, and thus V (B-) > is 0.
Thus, V (P-) ═ Idsg (R)on1+Ron2)。
Vsns＝Rg*Idsg/K+V(P-)＝Rg*Idsg/K+Idsg*(Ron1+Ron2)
＝Idsg*[(Rg/K+(Ron1+Ron2)]。
Typically, Rg/K>>(Ron1+Ron2) Therefore, the above formula can be equivalent to Vsns＝Idsg*Rg/K，Idsg＝K*Vsns/Rg。
VsnsThe value can be obtained by a subsequent voltage sampling circuit, Rg is a designed value of a previous circuit, so that the discharge current Idsg passing through the charge and discharge switch is accurately obtained, and the influence of the voltage or the temperature of a system is avoided.
Fig. 15 shows a VDMOS device structure according to an eighth embodiment of the present disclosure.
The device structure is different from that of the first embodiment in that a resistance structure of two detection resistances Rsns1 and Rsns2 is added. For example, the description related to fig. 8 can be referred to for specific implementation of the resistance structures of the detection resistors Rsns1 and Rsns2, and details thereof are not repeated here.
Fig. 16 shows a circuit diagram corresponding to the VDMOS device structure of fig. 15.
Fig. 17 shows an application of the VDMOS device structure of fig. 15 and the circuit shown in fig. 16. The charge and discharge control unit may include a detection unit constituted by MS1 and MS2 and resistors Rsns1 and Rsns3, and comparators CMP1 and CMP2, and the resistances of Rsns1 to Rsns6 may be equal. MOSFETs MD and MC constitute a discharge MOSFET and a charge MOSFET, respectively.
The control principle of charging and discharging in this embodiment is similar to that in the first embodiment, and is not described herein again.
The MOSFETs MS1 and MS2 are the same type of MOSFETs as the MOSFETs MD and MC. The ratio of the on-resistance of the MOSFETs MS1 and MS2 to the on-resistance of the MOSFETs MD and MC is constant K: 1, the ratio of the number of the cells is 1: K. The number of cells of the MOSFETs MS1 and MS2 may be the same, and the number of cells of the MOSFETs MD and MC may be the same.
In the discharging case, since the current flowing through the MOSFETs MD and MC at the time when the MOSFET MD is turned off is VREF2/Rsns6 ×.k. VREF2 and Rsns6 are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through MOSFETs MD and MC will not change, i.e., the detected discharge current will not change with voltage or temperature.
In the charging case, the current flowing through the MOSFETs MD and MC is VREF1/Rsns4 × K when the MOSFET MC is turned off. VREF1 and Rsns4 are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through MOSFETs MD and MC will not change, i.e. the detected charging current will not change with voltage or temperature.
Fig. 18 shows a VDMOS device structure according to a ninth embodiment of the present disclosure. The device structure differs from the first embodiment in that the cell structures are each replaced with the structure of an SGT MOSFET. The VDMOS device 200 may include: substrate 202, epitaxial layer 204, and cell structures, wherein each cell structure includes a gate oxide layer 206, a dielectric layer 210, a first well region 112, a second well region 214, and a heavily doped region 216. In addition, a source electrode 218 and a drain electrode 220 may be included.
In this embodiment, the polysilicon 108 shown in fig. 1 is replaced with a shield gate 2081 and a control gate 2082, with the shield gate 2081 and the control gate 2082 separated by a dielectric layer 210.
Thus, the functions of the above embodiments can be realized by the VDMOS device structure of this embodiment as well. In addition, for embodiments other than the first embodiment, the cell structure thereof may be replaced with the cell structure shown in the ninth embodiment, and the same function is achieved. And will not be described in detail herein.
In addition, the structure of the SGT MOSFET can be replaced by an LDMOS structure.
According to the present disclosure, the battery management chip comprises the above charge and discharge control circuit and further comprises the charge and discharge switch.
According to the present disclosure, an electrical device comprises: a battery management chip as above; and the battery is used for supplying power to other components of the electrical equipment, and the battery management chip is used for managing the battery.
According to the VDMOS structure disclosed by the invention, the proportion of the current of the charge-discharge loop and the sampling branch circuit is achieved by adjusting the cell number of the charge-discharge power tube and the sampling tube, so that the accurate sampling of the current is realized; meanwhile, due to the compatibility of the process, the sampling tube and the power tube can be integrated together to achieve the purpose of current sampling; the resistor can be integrated, and the voltage sampling at the two ends of the integrated resistor is used for realizing the integration of the resistor, so that the integration level of the system can be greatly increased from the application perspective, the problem of large volume is avoided, and the cost of the system is reduced.
In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims (10)

1. A VDMOS device for controlling a charging current and a discharging current of a battery, comprising:
a substrate of a first conductivity type;
an epitaxial layer disposed on the substrate and of a first conductivity type;
a first cell structure region including a cell structure formed in the epitaxial layer to constitute a charging MOSFET serving as a charging switch;
a second cell structure region including a cell structure formed in the epitaxial layer to constitute a discharge MOSFET serving as a discharge switch; and
a third cell structure region including a cell structure formed in the epitaxial layer to constitute a sampling MOSFET for collecting current flowing through the charging MOSFET and the discharging MOSFET.
2. The VDMOS device of claim 1, wherein a ratio of the number of cell structures in the third cell structure region to the number of cell structures in the first and second cell structure regions is 1: k is more than or equal to 2.
3. The VDMOS device of claim 2, wherein the charging MOSFET and the discharging MOSFET are configured such that their drains are connected.
4. The VDMOS device of claim 2, wherein the number of the third cell structure region and the sampling MOSFET is one, and wherein a source of the sampling MOSFET is configured to be connected to a source of the charging MOSFET or to a source of the discharging MOSFET, and a drain of the sampling MOSFET is configured to be a sampling terminal for a charging current or a discharging current;
or,
the number of the third cell structure region and the sampling MOSFETs is two, one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the sampling MOSFET is connected with the source electrode of the charging MOSFET or the source electrode of the discharging MOSFET, and the source electrode of the other sampling MOSFET is a sampling end of the charging current or the discharging current;
or,
a well resistor structure is further included to form a well resistor, one end of the well resistor is configured to be connected with the source of the other sampling MOSFET, the other end of the well resistor is configured to be connected with the source of the discharging MOSFET or the source of the charging MOSFET, and one end of the well resistor is configured to be a sampling end of the discharging current or the charging current;
or,
two sampling MOSFETs in the four sampling MOSFETs, wherein one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the one sampling MOSFET is connected with the source electrode of the charging MOSFET, and the source electrode of the other sampling MOSFET is a charging current sampling end; and
the other two sampling MOSFETs in the four sampling MOSFETs, one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the one sampling MOSFET is connected with the source electrode of the discharge MOSFET, and the source electrode of the other sampling MOSFET is a discharge current sampling end;
or,
the three cell structure regions and the sampling MOSFETs are two, one sampling MOSFET is connected with the drain electrode of the other sampling MOSFET, the source electrode of the one sampling MOSFET is connected with one end of the one well resistor, the other end of the one well resistor is connected with the source electrode of the charging MOSFET, one end of the other well resistor is connected with the source electrode of the other sampling MOSFET, the other end of the other well resistor is connected with the source electrode of the discharging MOSFET, one end of the one well resistor is a charging current sampling end, and one end of the other well resistor is a discharging current sampling end.
5. The VDMOS device of any one of claims 1-4, wherein each cell structure comprises:
the two trenches are respectively provided with a gate oxide layer, polycrystalline silicon and a dielectric layer positioned on the polycrystalline silicon;
a first well region of a second conductivity type and located between the two trenches and over the epitaxial layer; and
a heavily doped region located above the first well region and between the two trenches, the heavily doped region being of a first conductivity type;
or,
each cell structure includes:
the two trenches are respectively provided with a gate oxide layer, a control grid, a shielding grid, a first dielectric layer and a second dielectric layer, the control grid is positioned on the shielding grid and separated by the first dielectric layer, and the second dielectric layer is positioned on the control grid;
a first well region of a second conductivity type and located between the two trenches and over the epitaxial layer; and
a heavily doped region located over the first well region and between the two trenches, the heavily doped region being of a first conductivity type.
6. A charge and discharge control circuit comprising a VDMOS device according to any one of claims 1 to 5, wherein the battery is charged and discharged through a first connection terminal and a second connection terminal, and the charge and discharge is controlled by controlling a charge and discharge switch formed by a charge MOSFET and a discharge MOSFET connected in series in a current path between the battery and the first connection terminal or between the battery and the second connection terminal, wherein a sampling MOSFET and/or a well resistor in the VDMOS device constitutes a detection unit of the control circuit, the control circuit further comprising:
a first input end of the comparison unit is connected with a voltage related to the voltage of the first end of the detection unit, a second input end of the comparison unit is connected with a voltage related to the voltage of the first end of the charge and discharge switch, and a second end of the detection unit is connected with a second end of the charge and discharge switch; and
a control logic unit controlling the charging MOSFET and the discharging MOSFET according to the comparison result output by the comparison unit,
and the impedance ratio between the on-resistance value of the charge and discharge switch and the on-resistance value of the detection unit is kept constant.
7. The charge and discharge control circuit according to claim 6, wherein a current ratio between a current flowing through the charge and discharge switch and a current flowing through the detection unit is kept constant;
or,
the current ratio of the current flowing through the charge and discharge switch to the current flowing through the detection unit is independent of the system voltage and the system temperature;
or,
in the case of controlling the discharge current,
the source of the sampling MOSFET of the detection unit is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected with a constant current which is independent of voltage and temperature, and the discharge current flows from the charge MOSFET to the discharge MOSFET;
or,
when the voltage of the source side of the charging MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, and the control logic unit controls the disconnection of the discharging MOSFET;
or,
in the case of controlling the charging current,
the source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected with a constant current which is independent of voltage and temperature, and a discharging current flows from the discharging MOSFET to the charging MOSFET;
or,
when the voltage of the source side of the discharge MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, and the control logic unit controls the disconnection of the charge MOSFET;
or,
also comprises a mirror image circuit and a comparator,
a source of the sampling MOSFET is connected to a source of the discharge MOSFET, a drain of the sampling MOSFET is connected to a mirror circuit, a voltage on a drain side of the sampling MOSFET is set equal to a voltage on a source side of the charge MOSFET, a discharge current flows from the charge MOSFET to the discharge MOSFET,
when the voltage of the source side of the charging MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current, the voltage generated based on the mirror current is input to the first input end of the comparator, the reference voltage is input to the second input end of the comparator, and the control logic unit is controlled to turn off the discharging MOSFET according to the comparison result of the comparator;
or,
also comprises a mirror image circuit and a comparator,
a source of the sampling MOSFET is connected to a source of the charging MOSFET, a drain of the sampling MOSFET is connected to a mirror circuit, a voltage on a drain side of the sampling MOSFET is set equal to a voltage on a source side of the discharging MOSFET, and a charging current flows from the discharging MOSFET to the charging MOSFET,
when the voltage of the source side of the discharge MOSFET is larger than the voltage of the drain side of the sampling MOSFET, the comparison result of the comparison unit is inverted, the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current, the voltage generated based on the mirror current is input to the first input end of the comparator, the reference voltage is input to the second input end of the comparator, and the control logic unit is controlled to turn off the charge MOSFET according to the comparison result of the comparator;
or,
in the case where the sensing cell includes a well resistor and a sampling MOSFET,
in the case of controlling a discharge current, a connection point of the well resistor and the sampling MOSFET is connected to a first input terminal of the comparison unit, a second input terminal of the comparison unit is connected to a reference voltage generated based on a source side voltage of the discharge MOSFET, when a voltage of the first input terminal of the comparison unit is greater than a voltage of the second input terminal, a comparison result of the comparison unit is inverted, and the control logic unit controls turn-off of the discharge MOSFET;
or,
the resistance value of the trap resistor is far smaller than the on-resistance of the sampling MOSFET;
or,
in the case where the sensing cell includes a well resistor and a sampling MOSFET,
in the case of controlling the charging current, and a connection point of the well resistor and the sampling MOSFET is connected to a first input terminal of the comparison unit, a second input terminal of the comparison unit is connected to a reference voltage generated based on a source side voltage of the charging MOSFET, when a voltage of the first input terminal of the comparison unit is greater than a voltage of the second input terminal, a comparison result of the comparison unit is inverted, and the control logic unit controls turn-off of the charging MOSFET;
or,
the resistance value of the well resistor is far smaller than the on-resistance of the sampling MOSFET.
8. A battery management chip comprising the charge and discharge control circuit according to any one of claims 6 to 7.
9. The battery management chip of claim 8, further comprising the charge and discharge switch.
10. An electrical device, comprising:
the battery management chip of claim 8 or 9; and
the battery is used for supplying power to other components of the electrical equipment, and the battery management chip is used for managing the battery.
CN202011024951.4A 2020-09-25 2020-09-25 VDMOS device, control circuit, battery management chip and electrical equipment Pending CN112072757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011024951.4A CN112072757A (en) 2020-09-25 2020-09-25 VDMOS device, control circuit, battery management chip and electrical equipment

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Publication Number Publication Date
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114068496A (en) * 2022-01-17 2022-02-18 深圳市威兆半导体有限公司 Integrated SGT-MOSFET device for voltage sampling
CN114496995A (en) * 2022-04-18 2022-05-13 深圳市威兆半导体有限公司 Shielding gate device with temperature sampling function

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114068496A (en) * 2022-01-17 2022-02-18 深圳市威兆半导体有限公司 Integrated SGT-MOSFET device for voltage sampling
CN114068496B (en) * 2022-01-17 2022-03-18 深圳市威兆半导体有限公司 Integrated SGT-MOSFET device for voltage sampling
CN114496995A (en) * 2022-04-18 2022-05-13 深圳市威兆半导体有限公司 Shielding gate device with temperature sampling function
CN114496995B (en) * 2022-04-18 2022-06-17 深圳市威兆半导体有限公司 Shielding gate device with temperature sampling function

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