CN214314667U

CN214314667U - Integrated device and battery/battery pack management chip

Info

Publication number: CN214314667U
Application number: CN202120458752.8U
Authority: CN
Inventors: 周号
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2021-03-03
Filing date: 2021-03-03
Publication date: 2021-09-28
Anticipated expiration: 2031-03-03

Abstract

The present disclosure provides an integrated device for charge control and/or discharge control of a battery/battery pack, comprising: the field effect transistor comprises a grid electrode, a source electrode, a drain electrode, a substrate, a first parasitic diode and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are reversely connected in series; and one end of the connecting resistor is connected with the connecting point, and the other end of the connecting resistor is connected with the source electrode. The present disclosure also provides a battery/battery pack management chip.

Description

Integrated device and battery/battery pack management chip

Technical Field

The present disclosure relates to an integrated device and a battery/battery pack management chip.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the lifespan of the battery, but also cause safety accidents of explosion and fire when serious. The battery is, for example, a lithium battery pack or the like.

The MOS transistor serving as the charge and discharge switch has an on-resistance, and the on-resistances of the charge switch and the discharge switch are too large, which causes a power loss and affects the performance of the battery system. In addition, the charge switch and the discharge switch also need to be reliably turned on and off in charge and discharge control.

In addition, the charging and discharging current of the battery needs to be detected to ensure the safety of the battery. In the prior art, the detection can be realized by adding a separate detection resistor, and can also be realized by detecting the on-resistance of a charging and discharging MOSFET. The mode of external resistance will bring unfavorable condition such as increase pin. In the method of measuring the current by detecting the on-resistance of the MOSFET, the process and design parameters of each MOSFET are different, and the MOSFET is also subject to temperature interference and the like. Therefore, how to detect the charging and discharging current of the battery with high precision is a technical problem to be solved.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides an integrated device and a battery/battery pack management chip.

According to an aspect of the present disclosure, 1. an integrated device for charge control and/or discharge control of a battery/battery pack, comprising:

a field effect transistor including a gate, a source, a drain, a substrate, a first parasitic diode, and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of a series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and a connection point of the first parasitic diode and the second parasitic diode is connected to the substrate; and

and one end of the connecting resistor is connected with the connecting point, and the other end of the connecting resistor is connected with the source electrode.

According to at least one embodiment of the present disclosure, the series circuit of the first parasitic diode and the second parasitic diode is arranged such that no conductive path is formed between the source and the drain through the series circuit.

According to at least one embodiment of the present disclosure, the field effect transistor is an NMOS transistor, the field effect transistor is turned on when a gate-source voltage between the gate and the source is greater than a turn-on threshold voltage of the field effect transistor, and the field effect transistor is turned off when the gate-source voltage is less than the turn-on threshold voltage; alternatively, the first and second electrodes may be,

the field effect transistor is a PMOS transistor, the field effect transistor is switched on when the grid-source voltage between the grid electrode and the source electrode is smaller than the switching-on threshold voltage of the field effect transistor, and the field effect transistor is switched off when the grid-source voltage is larger than the switching-on threshold voltage.

According to at least one embodiment of the present disclosure, when the field effect transistor is an NMOS transistor, an anode of the first parasitic diode is connected to an anode of the second parasitic diode, a cathode of the first parasitic diode is connected to the drain, and a cathode of the second parasitic diode is connected to the source; or

When the field effect transistor is a PMOS transistor, the cathode of the first parasitic diode is connected with the cathode of the second parasitic diode, the anode of the first parasitic diode is connected with the drain, and the anode of the second parasitic diode is connected with the source.

According to at least one embodiment of the present disclosure, a first switch is connected between a gate and a drain of the field effect transistor,

the first switch is configured to: when the field effect transistor is switched off, the first switch ensures that the gate oxide of the field effect transistor is not broken down and/or that the field effect transistor does not form a conducting channel.

According to at least one embodiment of the present disclosure, a first switch is connected between a gate and a drain of the field effect transistor, the first switch is a voltage-resistant diode,

when the field effect transistor is an NMOS transistor, the anode of the voltage-withstanding diode is directly or indirectly connected with the grid of the field effect transistor, and the cathode of the voltage-withstanding diode is directly or indirectly connected with the drain of the field effect transistor; or when the field effect transistor is a PMOS transistor, the cathode of the voltage-resistant diode is directly or indirectly connected with the grid of the field effect transistor, and the anode of the voltage-resistant diode is directly or indirectly connected with the drain of the field effect transistor.

According to at least one embodiment of the present disclosure, a triode is connected between a gate and a drain of the field effect transistor, an emitter/collector of the triode is connected to the gate of the field effect transistor, and a collector/emitter of the triode is connected to the drain of the field effect transistor.

when the field effect transistor is an NMOS transistor, the first switch is a second NMOS transistor switch, the second NMOS transistor switch is provided with a third parasitic diode, the source electrode of the second NMOS transistor is directly or indirectly connected with one end of the third parasitic diode and the grid electrode of the field effect transistor, and the drain electrode of the second NMOS transistor is directly or indirectly connected with the other end of the third parasitic diode and the drain electrode of the field effect transistor; or

When the field effect transistor is a PMOS transistor, the first switch is a second PMOS transistor switch, the second PMOS transistor switch is provided with a third parasitic diode, the source electrode of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected with the grid electrode of the field effect transistor, and the drain electrode of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected with the drain electrode of the field effect transistor.

According to another aspect of the present disclosure, an integrated device for charge control and/or discharge control of a battery/cell pack, wherein the battery/cell pack is charged and discharged through a first connection terminal and a second connection terminal, the integrated device being integrated with:

a field effect transistor including a gate, a source, a drain, a substrate, a first parasitic diode, and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of a series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and a connection point of the first parasitic diode and the second parasitic diode is connected to the substrate; one end of the connecting resistor is connected with the connecting point, and the other end of the connecting resistor is connected with the source electrode; and

a current detection MOS transistor for detecting a charging current and/or a discharging current flowing through the field effect transistor.

According to at least one embodiment of the present disclosure, the power supply further comprises a comparison unit, wherein a first input end of the comparison unit is connected with a voltage related to the voltage of a first end of the current detection MOS transistor, a second input end of the comparison unit is connected with a voltage related to the voltage of a first end of the field effect transistor, and a second end of the current detection MOS transistor is connected with a second end of the field effect transistor; and

a control logic unit which controls the field effect transistor according to the comparison result output by the comparison unit,

wherein an impedance ratio between an on-resistance value of the field effect transistor and an on-resistance value of the current detection MOS transistor is kept constant.

According to at least one embodiment of the present disclosure, a current ratio between a current flowing through the field effect transistor and a current flowing through the current detection MOS transistor is kept constant.

According to at least one embodiment of the present disclosure, a current ratio between a current flowing through the field effect transistor and a current flowing through the current detection MOS transistor is independent of a system voltage and a system temperature.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to the load terminal/charger terminal and the second input terminal of the comparison unit, a source of the field effect transistor is connected to the battery/battery pack terminal, a source of the current detection MOS transistor is connected to the source of the field effect transistor, a drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit and to the constant current source, and an output terminal of the comparison unit serves as a current detection output terminal.

According to at least one embodiment of the present disclosure, the drain of the field effect transistor is connected to the load terminal/charger terminal and the drain of the current detection MOS transistor, the source of the current detection MOS transistor is connected to the constant current source, the source of the field effect transistor is connected to the battery/battery pack terminal and to the first input terminal of the comparison unit, the source of the current detection MOS transistor is connected to the second input terminal of the comparison unit, and the output terminal of the comparison unit serves as the current detection output terminal.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to the load/charger terminal and the second input terminal of the comparison unit, a source of the field effect transistor is connected to the battery/battery pack terminal, a source of the current detection MOS transistor is connected to the source of the field effect transistor, a drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit, a drain of the current detection MOS transistor is connected to a drain of the first PMOS transistor, a source of the first PMOS transistor is connected to a source of the second PMOS transistor, gates of the first PMOS transistor and the second PMOS transistor are connected to and to an output terminal of the comparison unit, a drain of the second PMOS transistor is connected to the first input terminal of the second comparison unit and one terminal of the first resistor, and the other terminal of the first resistor is grounded, and a second input end of the second comparison unit is connected with a reference voltage, and an output end of the second comparison unit is used as a current detection output end.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor, a first input terminal of the comparison unit is connected to a source of the field effect transistor and to a battery/battery pack terminal, a second input terminal of the comparison unit is connected to a source of the current detection MOS transistor, a source of the current detection MOS transistor is connected to a drain of a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of a second PMOS transistor and to an output terminal of the comparison unit, a source of the first PMOS transistor is connected to a source of the second PMOS transistor, a drain of the second PMOS transistor is connected to a first input terminal of the second comparison unit and to one terminal of a first resistor, the other terminal of the first resistor is grounded, a second input terminal of the second comparison unit is connected to the load terminal/charger terminal, and the output end of the second comparison unit is used as a current detection output end.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor, a source of the current detection MOS transistor is connected to a source of the field effect transistor and a battery/battery pack terminal via a first resistor, and is connected to a second input terminal of a comparison unit, a first input terminal of the comparison unit is connected to a reference voltage, the reference voltage is generated based on a voltage of the battery/battery pack terminal, and an output terminal of the comparison unit serves as a current detection output terminal.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor via a first resistor, a source of the current detection MOS transistor is connected to a source of the field effect transistor and a battery/battery pack terminal, a drain of the current detection MOS transistor is connected to a second input terminal of the comparison unit, a first input terminal of the comparison unit is connected to a reference voltage, the reference voltage is generated based on a voltage of the load terminal/charger terminal, and an output terminal of the comparison unit serves as a current detection output terminal.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to a load terminal/charger terminal and a second input terminal of the comparison unit, a source of the field effect transistor is connected to a source of the current detection MOS transistor and a battery/battery pack terminal, a drain of the current detection MOS transistor is connected to a first input terminal of the comparison unit, an output terminal of the comparison unit serves as a current detection output terminal, and an output terminal of the comparison unit and the first input terminal are connected to a first resistor.

According to at least one embodiment of the present disclosure, a drain of the field effect transistor is connected to the load/charger terminal and the drain of the current detection MOS transistor, a source of the current detection MOS transistor is connected to the second input terminal of the comparison unit, a first input terminal of the comparison unit is connected to the source of the field effect transistor, an output terminal of the comparison unit serves as a current detection output terminal, and an output terminal of the comparison unit and the second input terminal are connected to the first resistor.

According to another aspect of the present disclosure, a battery/battery pack management chip includes the integrated device as described in any one of the above.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 2 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 3 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 4 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 5 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 6 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 7 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 8 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 9 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 10 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 11 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 12 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 13 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 14 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 15 shows a battery management schematic according to an embodiment of the present disclosure.

Fig. 16 shows a battery management schematic according to an embodiment of the present disclosure.

FIG. 17 shows a schematic diagram of an electrical device according to one embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

When an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

Fig. 1 shows an integrated device (switching circuit) according to the present disclosure. In this embodiment, an NMOS transistor is used as an example for description.

As shown in fig. 1, the integrated device may include a field effect transistor 511 and a resistor 512.

The field effect transistor 511 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode 513, and a second parasitic diode 514, wherein the first parasitic diode 513 and the second parasitic diode 514 are connected in reverse series, one end of a series circuit of the first parasitic diode 513 and the second parasitic diode 514 is connected to the source S, and the other end of the series circuit is connected to the drain D, and a connection point of the first parasitic diode 513 and the second parasitic diode 514 is connected to the substrate B.

The anode of the first parasitic diode 513 is connected to the anode of the second parasitic diode 514, the cathode of the first parasitic diode 513 is connected to the drain, and the cathode of the second parasitic diode 514 is connected to the source.

The series circuit of the first parasitic diode 513 and the second parasitic diode 514 is arranged such that no conductive path is formed through the series circuit between the source S and the drain D of the field effect transistor 511.

One end of the resistor 512 is connected to the connection point, and the other end of the resistor 512 is connected to the source S. As an example, the resistor 512 is a large resistor.

A gate-source voltage V between the gate G and the source S of the field effect transistor 511_GSGreater than the turn-on threshold voltage V of the field effect transistor_THThe field effect transistor 511 is turned on.

A first switch 515 is connected between the gate G and the drain D of the field effect transistor 511.

The first switch is arranged to: when the field effect transistor is switched off, the first switch ensures that the gate oxide of the field effect transistor is not broken down and/or that the field effect transistor does not form a conducting channel.

In some cases, when the voltage of the drain D of the FET 511 is less than or equal to 0, for example, 0V to 40V, the first switch 515 is turned on to connect the gate G and the drain D of the FET 511, and when the voltage of the drain D of the FET 511 is greater than 0, the first switch 515 is turned off to disconnect the gate G and the drain D of the FET 511. Or in some cases, the first switch is turned off when the drain voltage is greater than the gate voltage, and the first switch is turned on when the drain voltage is less than or equal to the gate voltage. Or in some cases, the drain voltage is less than or equal to the gate voltage minus the turn-on voltage of the first switch, and the first switch is turned on.

The first switch 515 is a voltage-resistant diode, an anode of which is directly or indirectly connected to the gate G of the field-effect transistor 511, and a cathode of which is directly or indirectly connected to the drain of the field-effect transistor 511. In the case of direct connection, one end of the voltage-resistant diode is connected to the gate G of the field-effect transistor 511, and the other end is connected to the drain D of the field-effect transistor 511. In the case of indirect connection, the first switch 515 may form a series circuit with the second resistor 516, one end of the series circuit being connected to the gate G of the field effect transistor 511 and the other end being connected to the drain D of the field effect transistor 511. It should be noted that the series order of the first switch 515 and the second resistor 516 is not limited.

In fig. 1, the first switch 515 is shown in the form of a zener diode, the first switch 515 may also be a schottky diode or the like.

According to still other examples, the first switch may be an NMOS transistor. For example, as shown in fig. 2, the NMOS transistor 517 has a parasitic diode 518, the source of the NMOS transistor 517 and one end of the parasitic diode 518 are directly or indirectly connected to the gate of the field effect transistor 517, and the drain of the NMOS transistor and the other end of the parasitic diode 518 are directly or indirectly connected to the drain of the field effect transistor. In the case of direct connection, one end of the field-effect transistor 517 is connected to the gate G of the field-effect transistor 511, and the other end is connected to the drain D of the field-effect transistor 511. In the case of an indirect connection, the field effect transistor 517 may form a series circuit with the second resistor 516, one end of the series circuit being connected to the gate G of the field effect transistor 511 and the other end being connected to the drain D of the field effect transistor 511. It should be noted that the series order of the fet 517 and the second resistor 516 is not limited.

In the case of using an NMOS transistor as the first switch, the parasitic diode 518 of the NMOS transistor 517 is used as a withstand voltage diode, and thus can function as the first switch.

By using the first switch, the high voltage at the drain terminal D of the NMOS transistor 511 can be prevented from damaging the NMOS transistor 511, for example, breaking down the gate oxide layer.

When the circuit is normally charged, the conductive channel of the NMOS transistor 511 is formed, and the NMOS transistor 511 is turned on, so that the substrate Bulk region of the NMOS transistor 511 communicates with the source S of the NMOS transistor 511.

When the circuit is charged over-current, the conduction channel of NMOS transistor 511 is not formed and the channel of NMOS transistor 511 is in an off state. The Bulk region of the NMOS transistor 511 is disconnected from the source S, and the Bulk region is in a floating state.

Since the

parasitic diodes

513 and 514 are connected in reverse series, the series circuit of the

parasitic diodes

513 and 514 cannot be turned on, and therefore, the source S of the NMOS transistor 511 to the drain D of the NMOS transistor 511 also has no current path. According to the present disclosure, the gate oxide layer of the NMOS transistor 511 is not broken down.

As shown in fig. 3 and 4, the first switch may also be in the form of a transistor 519.

As shown in fig. 5, when the battery discharges to the external load, the current flow direction in the loop is: discharge current I_dsgFlowing from the P-terminal to the B-terminal, the voltage at the B-terminal is higher than that at the P-terminal, when the voltage difference (I) between the P-terminal and the B-terminal is detected_dsg*R_on) When a certain threshold is reached, the MOS transistor 511 is turned off, and the discharge path is turned off.

Parasitic diodes

513 and 514 in anti-series connection do not form a current path. The same principle applies to the first switch in the form of an NMOS transistor, a PMOS transistor, or a triode, etc.

Fig. 6 illustrates a charge and discharge switch according to the present disclosure. In this embodiment, a PMOS transistor is used as an example for description.

As shown in fig. 6, the charge/discharge switch includes a field effect transistor 511(PMOS transistor) and a resistor 512.

The cathode of the first parasitic diode 513 is connected to the cathode of the second parasitic diode 514, the anode of the first parasitic diode 513 is connected to the drain, and the anode of the second parasitic diode 514 is connected to the source.

One end of the switch 512 is connected to a connection point of the first parasitic diode 513 and the second parasitic diode 514, and the other end of the switch is connected to the source.

As one example, the field effect transistor is a PMOS transistor. The gate G of the PMOS transistor 512 is connected to the gate G of the PMOS transistor 511 of the field effect transistor.

A gate-source voltage V between the gate G and the source S of the field effect transistor 511_GSLess than the turn-on threshold voltage V of the field effect transistor_THThe field effect transistor 511 is turned on and the switch is turned on to make the source S of the field effect transistor 511 communicate with the substrate B when the gate-source voltage V is applied_GSGreater than a turn-on threshold voltage V_THThe field effect transistor 511 is off and the switch is off so that the source S of the field effect transistor 511 is disconnected from the substrate B, which is in a floating state.

By the switch bringing the source S of the field-effect transistor 511 into communication with the substrate B and the field-effect transistor 511 being on, a conduction channel of the field-effect transistor 511 is formed, and by the switch disconnecting the source S of the field-effect transistor 511 from the substrate B, a conduction channel of the field-effect transistor 511 is not formed.

A first switch 515 is connected between the gate G and the drain D of the field effect transistor 511. The first switch is configured to: when the field effect transistor is switched off, the first switch ensures that the gate oxide of the field effect transistor is not broken down and/or that the field effect transistor does not form a conducting channel. When the voltage of the drain D of the field effect transistor 511 is greater than 0, the first switch 515 is turned on to connect the gate G and the drain D of the field effect transistor 511, and when the voltage of the drain D of the field effect transistor 511 is less than or equal to 0, the first switch 515 is turned off to disconnect the gate G and the drain D of the field effect transistor 511. Or in some cases, the first switch is turned off when the drain voltage is less than or equal to the gate voltage, and the first switch is turned on when the drain voltage is greater than the gate voltage. Or in some cases, the drain voltage is greater than the gate voltage plus the turn-on voltage of the first switch, and the first switch is turned on.

In fig. 7, the first switch 515 is shown in the form of a zener diode, the first switch 515 may also be a schottky diode or the like.

According to still other examples, the first switch may be a PMOS transistor. For example, as shown in fig. 7, the PMOS transistor 517 has a parasitic diode 518, a source of the PMOS transistor 517 and one end of the parasitic diode 518 are directly or indirectly connected to a gate of the field effect transistor 517, and a drain of the PMOS transistor 517 and the other end of the parasitic diode 518 are directly or indirectly connected to a drain of the field effect transistor. In the case of direct connection, one end of the field-effect transistor 517 is connected to the gate G of the field-effect transistor 511, and the other end is connected to the drain D of the field-effect transistor 511. In the case of an indirect connection, the field effect transistor 517 may form a series circuit with the second resistor 516, one end of the series circuit being connected to the gate G of the field effect transistor 511 and the other end being connected to the drain D of the field effect transistor 511. It should be noted that the series order of the fet 517 and the second resistor 516 is not limited.

In the case of using a PMOS transistor as the first switch, the parasitic diode 618 of the PMOS transistor 617 is used as a withstand voltage diode, and can function as the first switch.

By using the first switch, the high voltage at the drain terminal D of the PMOS transistor 511 can be prevented from damaging the PMOS transistor 511.

When the circuit is normally charged, the conductive channel of the PMOS transistor 511 is formed, and the PMOS transistor 511 is turned on, so that the substrate Bulk region of the PMOS transistor 511 communicates with the source S of the PMOS transistor 511.

For example, when the battery discharges to the external load, the principle is the same, and the first switch may be converted into NMOS transistor, triode, etc., which can be referred to the above description, and will not be described again.

In the present disclosure, the field effect transistor, the first switch, the second resistor, and the like may be integrated in one device, and in addition, the resistor 512 may also be integrated in the device.

As shown in fig. 8, a battery management system 10 is provided according to the present disclosure, wherein the battery management system may be used to manage a battery or battery pack 20, which may be in the form of a chip. It should be noted that in the present disclosure, the charge and discharge switch may be integrated inside the chip or may be disposed outside the chip. In the drawings of the present disclosure, a description is made in a form in which a charge and discharge switch is provided inside a chip. In addition, an external charger or external load 30 may be connected across the battery or battery pack 20 to perform charging or discharging operations on the battery or battery pack 20.

As shown in fig. 8, the battery management system 10 may include a VDD generator 100, a voltage acquisition unit 200, a logic control unit 300, a driving unit 400, and a current control detection circuit 500 (integrated device).

The VDD generator 100 generates a VDD voltage according to the highest voltage of the battery pack 20 for use inside the chip.

The voltage collecting unit 200 is used for collecting the voltage of the battery or the battery pack 20, when the battery pack is used, the voltage collecting unit 200 collects the voltage of each battery, the voltage collecting unit 200 provides the collected battery voltage to the control logic unit 300, and the control logic unit 300 controls the charge and discharge switches through the driving unit 400.

The current control detection circuit 500 receives a signal from the driving unit 400 to control charging and discharging of the battery. The current control detection circuit 500 may include a charge/discharge switch 510 and a current detection unit 520.

The charge and discharge switch 510 is connected in series on a current path between the battery and the first connection terminal P-or between the battery and the second connection terminal P +.

The current detection unit 520 is used to detect the charge and discharge current flowing through the charge and discharge switch 510.

The control logic unit 300 controls the charge and discharge switch 510 according to the current value detected by the current detection unit 520, wherein the ratio between the on-resistance value of the charge and discharge switch and the on-resistance value of the current detection unit is kept constant. The ratio between the current flowing through the charge and discharge switch and the current flowing through the current detection unit is kept constant.

The ratio of the current flowing through the charge and discharge switch to the current flowing through the detection unit is independent of the system voltage and the system temperature.

That is, the ratio between the on-resistance value of the charge and discharge switch and the on-resistance value of the detection unit, and the ratio between the current flowing through the charge and discharge switch and the current flowing through the detection unit are not affected by the system voltage and the system temperature.

The charge and discharge switch is a MOS transistor and realizes charge current control and discharge current control by one MOS transistor.

The MOS transistor of the detection unit and the charge and discharge switch are the same type of MOS transistor.

First, a MOS transistor (the MOS transistor 511 mentioned above) is used as the charge/discharge switch in the present disclosure. Which will be described in detail below.

In the present disclosure, the MOS transistor of the charge/discharge switch and the MOS transistor of the detection unit are integrated in one chip. In addition, other devices can be integrated into the chip.

In the present disclosure, the current detection unit and the charge and discharge switch are integrated in one chip, and may be disposed in one wafer, for example.

The following description will be given taking the charge and discharge switches shown in the drawings as an example, and for other forms, reference may be made to the description with respect to the drawings. Specifically, the charge and discharge switch of the figure is replaced with another form of charge and discharge switch. Embodiments of various current control sensing circuits 500 are described in detail below with reference to fig. 9-16, wherein the components shown in dashed boxes in fig. 9-16 may be integrated into a wafer to form a single device.

Fig. 9 shows a schematic diagram of a first embodiment according to the present disclosure. The first embodiment is used for controlling the battery discharge overcurrent.

The charging and discharging control unit may include a detection unit and a comparison unit, a first input end of the comparison unit is connected to a voltage related to a voltage of a first end of the detection unit, a second input end of the comparison unit is connected to a voltage related to a voltage of a first end of the charging and discharging switch, and a second end of the detection unit is connected to a second end of the charging and discharging switch. The charge and discharge switches are 511. The detection unit is an NMOS transistor 531 a.

The drain of the transistor 531a is connected to a first input of the comparing unit, the drain of the transistor 511 is connected to an external negative terminal P-and to a second input of the comparing unit, the source of the transistor 531a is connected to the source of the transistor 511 and to the battery negative terminal B-. A gate of the transistor 531a may be connected to a gate of the transistor 511 and receive a driving control signal IN of the driving unit to be turned on and off. Alternatively, the gate of the transistor 511 is connected to the driving control signal IN, and the gate of the transistor 531a may receive another control signal to keep it at least on during detection. In addition, Bulk (substrate) of the transistor 531a and the transistor 511 may or may not be connected together (for the embodiments in fig. 10 to 16, the

transistors

531a and 511 may also be connected in this manner). The drain of the NMOS transistor 531a of the detection unit is connected with a constant current Idc that is independent of the voltage and temperature of the system.

And the discharge current Idsg flows from a first terminal (shown connected to a negative terminal, i.e., the P-terminal, of the external charger or external load 300) of the charge and discharge switch to a second terminal. When the voltage of the first end of the charge and discharge switch is greater than the voltage of the drain side of the NMOS transistor of the detection unit, the comparison result of the comparison unit is inverted, and the control logic unit controls the discharge control switch to be turned off.

Specifically, a constant current Idc that generates a voltage Va (voltage at the drain terminal of the NMOS transistor 531 a) across the NMOS transistor 531a regardless of the voltage and temperature of the system may be generated inside the chip. Since the

NMOS transistors

511 and 531a are NMOS transistors of the same type, even if the temperature or voltage of the system changes, the sum of the equivalent on-resistance of the NMOS transistor 531a and the equivalent on-resistance of the NMOS transistor 511 can be maintained at a constant value K: 1 (corresponding to a size ratio of 1: K).

The comparing unit 532a is used for the voltage Va and the voltage VP- (voltage of P-terminal), when VP-is greater than Va, the output signal of the comparing unit 532a is inverted, and after the control logic unit 300 receives the inverted signal, the driving unit 400 outputs the control signal OD to turn off the charge and discharge switch.

Fig. 10 shows a schematic diagram of a second embodiment according to the present disclosure. The second embodiment is used for controlling the battery charging overcurrent. The charging and discharging control unit may include a detection unit and a comparison unit, a second input end of the comparison unit is connected to a voltage related to a voltage of a second end of the detection unit, a first input end of the comparison unit is connected to a voltage related to a voltage of a second end of the charging and discharging switch, and a first end of the detection unit is connected to a first end of the charging and discharging switch. The charge and discharge switch is a charge and discharge switch 511. The detection unit is an NMOS transistor 531 b. One input terminal of the comparing unit 532B is connected to the voltage of the B-terminal, the other input terminal is connected to the source of the transistor 531B, and the drain thereof is connected to the P-terminal.

Specifically, a constant current Idc that generates a voltage Vb (the voltage at the drain terminal of the NMOS transistor 531 b) across the NMOS transistor 531b regardless of the voltage and temperature of the system can be generated inside the chip. Since the

NMOS transistors

511 and 531b are NMOS transistors of the same type, even if the temperature or voltage of the system changes, the sum of the equivalent on-resistance of the NMOS transistor 531b and the equivalent on-resistance of the NMOS transistor 511 can be maintained at a constant value K: 1.

the comparison unit 532B is used for comparing the voltage Vb with the voltage VB- (voltage at the B-terminal), when VB-is greater than Vb, the output signal of the comparison unit 532B is inverted, and after the control logic unit 300 receives the inverted signal, the control logic unit 400 outputs a control signal to disconnect the charge and discharge switches. As for the connection manner of the gates of the

NMOS transistors

531b and 511, the description of the first embodiment may be referred to, and the connection manner in the following embodiments may also be referred to.

Fig. 11 shows a schematic diagram of a third embodiment according to the present disclosure. The third embodiment is used for controlling the battery discharge overcurrent. The discharge current Idsg flows from the P-terminal to the B-terminal.

In this embodiment, the detecting unit is an NMOS transistor 531c, and the source of the NMOS transistor 531c is connected to the second terminal of the charge/discharge switch 511 (the right end of the discharge switch, i.e. the negative terminal B-of the battery is shown in the figure).

The drain of NMOS transistor 531c is connected to a mirror circuit, which includes

PMOS transistors

533c and 534c, the drain of NMOS transistor 531c may be connected to the drain of PMOS transistor 533c, and the source of PMOS transistor 533c may be connected to a system voltage (e.g., VDD), and the gate of PMOS transistor 533c is connected to the gate of PMOS transistor 534c, and the source of PMOS transistor 534c may be connected to the system voltage.

The source of the NMOS transistor 531c is connected to the B-terminal, and the gate thereof may be connected to the system voltage VDD, one input terminal of the comparing unit 532c is connected to the drain of the NMOS transistor 531c, and the other input terminal of the comparing unit 532c is connected to the first terminal of the charge and discharge switch (shown in the figure as being connected to the negative terminal, i.e., the P-terminal, of the external charger or external load 300).

The output of the comparison unit 532c is connected to the gates of

PMOS transistors

533c and 534c, and the drain of PMOS transistor 534c is connected to a resistor 535 c.

Further included is a comparator 536c, one input terminal of the comparator 536c being connected to the drain of the PMOS transistor 534c so as to input the voltage generated by the resistor 535c to one input terminal of the comparator 536a, the other input terminal of the comparator 536c being connected to a reference voltage Vref.

In this embodiment, the comparison unit 532c may make the voltage Vc of the drain side of the NMOS transistor 531c the same as the voltage VP-of the P-side.

Here, the

NMOS transistors

531c and 511 are NMOS transistors of the same type, so even if the temperature and the voltage change, the comparison between the equivalent on-resistance of the NMOS transistor 531c and the equivalent on-resistance of the NMOS transistor 511 will be maintained at a constant value K: 1. thus, since Vc ═ VP-, the current flowing through the NMOS transistor 531c and the current flowing through the NMOS transistor 511 are kept at 1: K.

the

PMOS transistors

533c and 534c are the same type PMOS transistors, and operate in the saturation region. Thus, the current flowing through the NMOS transistor 531c can be mirrored to the path of the resistor 535c, which generates a voltage on the resistor 535c (the resistance is assumed to be Rc), and by comparing the voltage Vr with the reference voltage Vref, when Vr is greater than Vref, the comparator 536c performs inversion, so that the logic control unit 300 can control the driving unit 400 according to the inversion signal, and the driving unit 400 outputs a control signal to turn off the NMOS transistor 511.

Since the current flowing through the NMOS transistor 511 is Vref/Rc × K when the discharge NMOS transistor 520 is turned off. Vref and Rc are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through the NMOS transistor 511 will not change, i.e. the detected discharge over-current will not change with the voltage or temperature.

Fig. 12 shows a schematic diagram of a fourth embodiment according to the present disclosure.

The fourth embodiment is used for controlling the battery charging overcurrent. The charging current Ichg flows from the B-terminal to the P-terminal.

In this embodiment, the detecting unit is an NMOS transistor 531d, and the source of the NMOS transistor 531d is connected to the first terminal of the charge/discharge switch (shown as the negative terminal, i.e., the P-terminal, connected to the external charger or external load 300).

The drain of NMOS transistor 531d is connected to a mirror circuit that includes

PMOS transistors

533d and 534d, the drain of NMOS transistor 531d may be connected to the drain of PMOS transistor 533d, and the source of PMOS transistor 533d may be connected to a system voltage (e.g., VDD), and the gate of PMOS transistor 533d is connected to the gate of PMOS transistor 534d, and the source of PMOS transistor 534d may be connected to the system voltage.

The source of the NMOS transistor 531d is connected to the P-terminal, and the gate thereof may be connected to the system voltage VDD, one input terminal of the comparing unit 532d is connected to the drain of the NMOS transistor 531d, and the other input terminal of the comparing unit 532d is connected to the second terminal of the charge and discharge switch (the right terminal of the discharge switch, i.e. the negative terminal B-terminal of the battery is shown in the figure).

The output of the comparison unit 532d is connected to the gates of the

PMOS transistors

533d and 534d, and the drain of the PMOS transistor 534d is connected to the resistor 535 d.

Further included is a comparator 536d, one input terminal of the comparator 536d being connected to the drain of the PMOS transistor 534d so as to input the voltage generated by the resistor 535d to one input terminal of the comparator 536d, the other input terminal of the comparator 536d being connected to the reference voltage Vref.

In this embodiment, the comparison unit 532d may make the voltage Vc of the drain side of the NMOS transistor 531d the same as the voltage VB-of the B-side.

Here, the

NMOS transistors

531d and 511 are NMOS transistors of the same type, so even if the temperature and the voltage change, the comparison between the equivalent on-resistance of the NMOS transistor 531d and the equivalent on-resistance of the NMOS transistor 511 will be maintained at a constant value K: 1. thus, since Vc ═ VB —, the current flowing through the NMOS transistor 531d and the current flowing through the NMOS transistor 511 are kept at 1: K.

the PMOS transistor 533d and the PMOS transistor 534d are the same type PMOS transistors, and operate in the saturation region. Thus, the current flowing through the NMOS transistor 531d can be mirrored to the path of the resistor 535d, which generates a voltage on the resistor 535d (the resistance is assumed to be Rd), and by comparing the voltage Vr with the reference voltage Vref, when Vr is greater than Vref, the comparator 536c flips, so that the logic control unit 300 can control the driving unit 400 according to the flipping signal, and the driving unit 400 outputs a control signal to turn off the transistor 511.

Since the current flowing through the NMOS transistor 511 is Vref/Rd × K when the transistor 511 is turned off. Vref and Rd are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through the NMOS transistor 5511 will not change, i.e., the detected charging overcurrent will not change with the voltage or temperature.

Fig. 13 shows a schematic diagram of a fifth embodiment according to the present disclosure.

The fifth embodiment is for controlling a battery discharge overcurrent. The discharge current Idsg flows from the P-terminal to the B-terminal. The charge and discharge switches are transistors 511. The detection unit includes a resistor 533e and an NMOS transistor 531e connected in series.

The resistance of the resistor 533e is much smaller than the on-resistance of the NMOS transistor 531 e. The drain of transistor 531e is connected to the P-terminal, the source is connected to one terminal of resistor 533e, and the other terminal of resistor 533e is connected to the B-terminal.

A connection point of the NMOS transistor 531e and the resistor 533e is connected to one input terminal of the comparison unit 534e, and the other input terminal of the comparison unit 534e is connected to the reference voltage Vref generated based on VB- (the voltage of the B-terminal). The generation of the reference voltage Vref may be generated based on a VB-pass voltage generation unit 535e (e.g., a voltage with VB-as a reference zero potential, which may be generated inside a chip).

The NMOS transistor 531e is the same type of NMOS transistor as the NMOS transistor 511. The ratio of the on-resistance of the NMOS transistor 531e to the on-resistance of the NMOS transistor 511 is constant K: 1. meanwhile, in order to ensure accuracy, the resistance Re of the resistor 533e is set to be much smaller than the on-resistance of the NMOS transistor 531 e. Thus, the voltage Ve at the connection point of the NMOS transistor 532e and the resistor 533e is compared with Vref, and when Ve is greater than Vref, the comparator 534e inverts, so that the logic control unit 300 can control the driving unit 400 according to the inverted signal, and the discharging NMOS transistor 511 is turned off by the driving unit 400 outputting a control signal.

Since the current flowing through the NMOS transistor 511 is Vref/Re × K when the NMOS transistor is turned off. Vref and Re are fixed values, and K is a constant ratio, which will not change when the system voltage and temperature change, so that the current flowing through the NMOS transistor 511 will not change, i.e. the detected discharge overcurrent will not change with the voltage or temperature.

Fig. 14 shows a schematic diagram of a sixth embodiment according to the present disclosure.

The sixth embodiment is for controlling the battery charging overcurrent. The charging current Ichg flows from the B-terminal to the P-terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input end of the comparison unit is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparison unit is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch.

The charge and discharge switches are NMOS transistors 511.

The detection unit includes a resistor 533f and an NMOS transistor 531f connected in series. Under the condition of controlling the charging current, one end of a resistor of the detection unit is connected to a first end of the charging and discharging switch, the other end of the resistor of the detection unit is connected to one end of an NMOS (N-channel metal oxide semiconductor) tube of the detection unit, the other end of the resistor of the detection unit is connected to a second end of the charging and discharging switch, a connection point of the resistor of the detection unit and an NMOS transistor is connected to a first input end of the comparison unit, a second input end of the comparison unit is connected with a reference voltage generated based on the voltage of the second end of the charging and discharging switch, when the voltage of the first input end of the comparison unit is larger than the voltage of the second input end of the comparison unit, the comparison result of the comparison unit is inverted, and the control logic unit controls the charging control switch to be switched off. The resistance value of the resistor of the detection unit is far smaller than the on-resistance of the NMOS transistor of the detection unit.

The source of the NMOS transistor 531f is connected to the B-terminal, the drain is connected to one end of the resistor 533f, and the other end of the resistor 533f is connected to the P-terminal. A connection point of the NMOS transistor 531f and the resistor 533f is connected to one input terminal of the comparison unit 534f, and the other input terminal of the comparison unit 534f is connected to the reference voltage Vref generated based on VP- (voltage of P-terminal). The generation of the reference voltage Vref may be generated based on a VP-pass voltage generation unit (e.g., a voltage with VP-as a reference zero potential, which may be generated inside a chip).

The NMOS transistor 531f is an NMOS transistor of the same type as the NMOS transistor 511. The ratio of the on-resistance of the NMOS transistor 531f to the on-resistance of the NMOS transistor 511 is constant K: 1. meanwhile, in order to ensure accuracy, the resistance Rf of the resistor 533f is set to be much smaller than the on-resistance of the NMOS transistor 531 f. Thus, the voltage Vf of the connection point of the NMOS transistor 532f and the resistor 533f is compared with Vref, and when Vf is greater than Vref, the comparator 534f inverts, so that the logic control unit 300 can control the driving unit 400 according to the inverted signal, and the driving unit 400 outputs the control signal to turn off the switch 511.

Since the current flowing through the NMOS transistor 511 is Vref/Rf × K when the switch 511 is turned off. Vref and Rf are fixed values, K is a constant ratio, and the three values do not change when the system voltage and temperature change, so that the current flowing through the NMOS transistor 511 does not change, that is, the detected charging overcurrent does not change with the voltage or temperature.

Fig. 15 shows a schematic diagram of a seventh embodiment according to the present disclosure.

The seventh embodiment is for controlling the battery charging overcurrent. The discharge current Idsg flows from the P-terminal to the B-terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input end of the comparison unit is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparison unit is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switch is charge 511.

In this embodiment, the comparison unit is an operational amplifier, a detection resistor is connected in series between the second input terminal of the operational amplifier and the output terminal of the operational amplifier, one end of the NMOS transistor of the comparison unit is connected to the second input terminal of the operational amplifier and the other end of the NMOS transistor of the comparison unit is connected to the second end of the charge and discharge switch, and the first input terminal of the operational amplifier is connected to the first end of the charge and discharge switch.

And obtaining the current value of the charging current or the discharging current according to the voltage generated by the detection resistor and the resistance value of the detection resistor.

This will be described in detail with reference to fig. 15. Wherein the detection unit may include an NMOS transistor 531 g. The NMOS transistor 531g may be an NMOS transistor of the same type as the NMOS transistor 511.

The source of the NMOS transistor 531g is connected to the B-terminal, and the drain thereof is connected to one input terminal of the operational amplifier 533 g. The other input terminal of the operational amplifier 533g is connected to the P-terminal.

The principle of this embodiment will be explained in detail below.

When charging, the battery is externally connected with an external load, the external load is connected between the output positive pole P + and the output negative pole P-, and the resistance value is R_LoadThe discharge current Idsg of the battery thus obtained is [ V (P +) -V (P-)]/R_Load。

The operational amplifier 533g may make the source terminal voltage of the NMOS transistor 531g the same as the voltage of the negative P-terminal of the battery output, and the NMOS transistor 531g and the NMOS transistor 511 are the same type of NMOS transistor. Therefore, even if the temperature or voltage changes, the ratio of the on-resistance of the NMOS transistor 531g to the on-resistance of the NMOS transistor 511 is always maintained at a constant value K: 1. thus, the current flowing through the NMOS transistor 531g and the current flowing through the NMOS transistor 511 are constantly maintained at 1: K.

because of the negative feedback effect of the operational amplifier 533g, the negative input terminal of the operational amplifier 533g, i.e., the source terminal voltage of the NMOS transistor 531g, is the same as the negative P-terminal voltage of the battery output.

Since the impedance of the input terminal of the operational amplifier 533g is approximately infinite, the current of the NMOS transistor 531g flows entirely into the sampling resistor 534g (with a resistance value Rg).

Thus, the output voltage V of the operational amplifier 533g_snsRg Idsg/k + V (P-). V (P-) is the P-terminal voltage.

V(P-)＝V(B-)+Idsg*(R_on). V (B-) is the voltage at the B-terminal, R_on1Being NMOS transistor 511An equivalent resistance.

The B-terminal is the ground terminal of the battery, so V (B-) can be considered as the "ground" point of the system, and thus V (B-) > is 0.

Thus, V (P-) ═ Idsg (R)_on)。

V_sns＝Rg*Idsg/K+V(P-)＝Rg*Idsg/K+Idsg*(R_on)

＝Idsg*[(Rg/K+(R_on)]。

Typically, Rg/K>>(R_on) Therefore, the above formula can be equivalent to V_sns＝Idsg*Rg/K， Idsg＝K*V_sns/Rg。

V_snsThe value can be obtained by a subsequent voltage sampling circuit, Rg is a designed value of a previous circuit, so that the discharge current Idsg passing through the charge and discharge switch is accurately obtained, and the influence of the voltage or the temperature of a system is avoided.

Fig. 16 shows a schematic diagram of an eighth embodiment according to the present disclosure.

The eighth embodiment is for controlling the battery charging overcurrent. The charging current Ichg flows from the B-terminal to the P-terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input end of the comparison unit is connected with the voltage related to the voltage of the second end of the detection unit, the first input end of the comparison unit is connected with the voltage related to the voltage of the first end of the charge and discharge switch, and the first end of the detection unit is connected with the first end of the charge and discharge switch. The charge and discharge switch is charge 511.

The detection unit may include an NMOS transistor 531 h. The NMOS transistor 531h may be an NMOS transistor of the same type as the NMOS transistor 511.

The drain of the NMOS transistor 531h is connected to the P-terminal, and the source thereof is connected to one input terminal of the operational amplifier 533 h. The gate of the NMOS transistor 531h is connected to the control signal IN. The other input terminal of the operational amplifier 533h is connected to the B-terminal.

The principle of this embodiment will be explained in detail below.

The NMOS transistor 531h is the same type of NMOS transistor as the NMOS transistor 511. Therefore, even if the temperature or voltage changes, the ratio of the on-resistance of the NMOS transistor 531h to the on-resistance of the NMOS transistor 511 is always maintained at a constant value K: 1. thus, the current flowing through the NMOS transistor 531h and the current flowing through the NMOS transistor 511 are constantly maintained at 1: K.

during charging, the external charger is connected between the output positive electrode (P +) of the battery and the output negative electrode (P-) of the battery, and the magnitude of the charging current from the external charger to the battery pack is Ichg (1+ 1/K). The current flowing through charge NMOS transistor 511 is Ichg, and the current flowing through NMOS transistor 531h is Ichg/K.

The operational amplifier 533h may have the source terminal voltage of the NMOS transistor 531h equal to the voltage of the battery negative electrode B-, and since the voltage of the battery negative electrode B-is the system "ground" point, V (B-) > becomes 0.

The negative input terminal of the operational amplifier 533h, i.e., the source terminal voltage of the NMOS transistor 531h, is the same as the voltage of the negative pole P-of the battery output due to the negative feedback action of the operational amplifier 533 h.

Also, since the impedance of the input terminal of the operational amplifier 533h is approximately infinite, the current of the NMOS transistor 531h flows into the sampling resistor 534h (whose resistance is Rh) entirely.

Thus, the output voltage V of the operational amplifier 533h_snsRh Ichg/K + V (B-) ═ Rh Ichg/K. Because of V_snsThe value can be obtained by a subsequent voltage sampling circuit, Rh is a designed value of a previous circuit, so that the charging current Ichg flowing through the charging and discharging switch can be accurately obtained, and the influence of the voltage or the temperature of a system can not be caused.

In addition, although the NMOS transistor is illustrated in the drawings and the description, other types of MOS transistors, such as a PMOS transistor, may be used.

Through the embodiment of the disclosure, the system temperature or voltage can be avoided, and the influence of the transistor can also be avoided, so that according to the technical scheme of the disclosure, the high-precision detection of the charging and discharging current can be realized.

According to a further aspect of the present disclosure, the present disclosure provides a battery management chip 10, wherein the battery management chip may be integrated with the current control detection circuit; the battery management chip can be integrated with a current control detection circuit and a charge and discharge switch. In addition, the battery management chip may further integrate a voltage acquisition unit, a VDD generator, a driving unit, and the like as shown in the figure.

The present disclosure also provides an electrical device, as shown in fig. 17, including a battery or a battery pack and a battery management chip, where the battery is used to supply power to other devices of the electrical device or to supply power to the battery through a charger, and a battery management system is used to manage the battery.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. An integrated device for charge control and/or discharge control of a battery/battery pack, comprising:

2. The integrated device of claim 1, wherein the series circuit of the first parasitic diode and the second parasitic diode is configured such that no conductive path is formed between the source and the drain through the series circuit.

3. The integrated device of claim 2,

the field effect transistor is an NMOS transistor, the field effect transistor is switched on when the grid-source voltage between the grid electrode and the source electrode is greater than the switching-on threshold voltage of the field effect transistor, and the field effect transistor is switched off when the grid-source voltage is less than the switching-on threshold voltage; alternatively, the first and second electrodes may be,

4. The integrated device of claim 3,

when the field effect transistor is an NMOS transistor, the anode of the first parasitic diode is connected with the anode of the second parasitic diode, the cathode of the first parasitic diode is connected with the drain, and the cathode of the second parasitic diode is connected with the source; or

5. The integrated device of claim 1, wherein a first switch is connected between the gate and the drain of the field effect transistor,

6. The integrated device according to claim 1, wherein a first switch is connected between a gate and a drain of the field effect transistor, the first switch being a voltage-resistant diode,

7. The integrated device according to claim 1, wherein a triode is connected between a gate and a drain of the field effect transistor, wherein an emitter/collector of the triode is connected to the gate of the field effect transistor, and wherein a collector/emitter of the triode is connected to the drain of the field effect transistor.

8. The integrated device of claim 1, wherein a first switch is connected between the gate and the drain of the field effect transistor,

9. An integrated device for charge control and/or discharge control of a battery/cell stack, wherein the battery/cell stack is charged and discharged via a first connection terminal and a second connection terminal, characterized in that the integrated device is integrated with:

10. The integrated device of claim 9, wherein the series circuit of the first parasitic diode and the second parasitic diode is configured such that no conductive path is formed between the source and the drain through the series circuit.

11. The integrated device of claim 10,

12. The integrated device of claim 11,

13. The integrated device of claim 9, wherein a first switch is connected between the gate and the drain of the field effect transistor,

14. The integrated device according to claim 9, wherein a first switch is connected between a gate and a drain of the field effect transistor, the first switch being a voltage-resistant diode,

15. The integrated device according to claim 9, wherein a triode is connected between the gate and the drain of the field effect transistor, wherein an emitter/collector of the triode is connected to the gate of the field effect transistor, and wherein a collector/emitter of the triode is connected to the drain of the field effect transistor.

16. The integrated device of claim 9, wherein a first switch is connected between the gate and the drain of the field effect transistor,

17. The integrated device according to any one of claims 9 to 16, further comprising a comparison unit, a first input terminal of the comparison unit being connected to a voltage related to a voltage of the first terminal of the current detection MOS transistor, a second input terminal of the comparison unit being connected to a voltage related to a voltage of the first terminal of the field effect transistor, a second terminal of the current detection MOS transistor being connected to the second terminal of the field effect transistor; and

18. The integrated device according to claim 17, wherein a current ratio between a current flowing through the field-effect transistor and a current flowing through the current detection MOS transistor is kept constant.

19. The integrated device of claim 18, wherein a current ratio between a current flowing through the field effect transistor and a current flowing through the current sensing MOS transistor is independent of a system voltage and a system temperature.

20. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to the load terminal/charger terminal and the second input terminal of the comparison unit, a source of the field effect transistor is connected to the battery/battery pack terminal, a source of the current detection MOS transistor is connected to the source of the field effect transistor, a drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit and to a constant current source, and an output terminal of the comparison unit serves as a current detection output terminal.

21. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to the load terminal/charger terminal and a drain of a current detection MOS transistor, a source of the current detection MOS transistor is connected to a constant current source, a source of the field effect transistor is connected to the battery/battery pack terminal and to a first input terminal of a comparison unit, a source of the current detection MOS transistor is connected to a second input terminal of the comparison unit, and an output terminal of the comparison unit serves as a current detection output terminal.

22. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and a second input terminal of the comparison unit, a source of the field effect transistor is connected to a battery/battery pack terminal, a source of the current detection MOS transistor is connected to a source of the field effect transistor, a drain of the current detection MOS transistor is connected to a second input terminal of the comparison unit, a drain of the current detection MOS transistor is connected to a drain of a first PMOS transistor, a source of the first PMOS transistor is connected to a source of a second PMOS transistor, gates of the first PMOS transistor and the second PMOS transistor are connected to and connected to an output terminal of the comparison unit, a drain of the second PMOS transistor is connected to a first input terminal of the second comparison unit and one terminal of a first resistor, and the other terminal of the first resistor is grounded, and a second input end of the second comparison unit is connected with a reference voltage, and an output end of the second comparison unit is used as a current detection output end.

23. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor, a first input terminal of the comparison unit is connected to a source of the field effect transistor and to a battery/battery pack terminal, a second input terminal of the comparison unit is connected to a source of the current detection MOS transistor, a source of the current detection MOS transistor is connected to a drain of a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of a second PMOS transistor and to an output terminal of the comparison unit, a source of the first PMOS transistor is connected to a source of the second PMOS transistor, a drain of the second PMOS transistor is connected to a first input terminal of the second comparison unit and one terminal of a first resistor, and the other terminal of the first resistor is grounded, and a second input end of the second comparison unit is connected with a load end/charger end, and an output end of the second comparison unit is used as a current detection output end.

24. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor, a source of the current detection MOS transistor is connected to a source of the field effect transistor and a battery/pack terminal via a first resistor, and is connected to a second input terminal of a comparison unit, a first input terminal of the comparison unit is connected to a reference voltage, the reference voltage is generated based on a voltage of the battery/pack terminal, and an output terminal of the comparison unit serves as a current detection output terminal.

25. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and to a drain of the current detection MOS transistor via a first resistor, a source of the current detection MOS transistor is connected to a source of the field effect transistor and a battery/battery pack terminal, a drain of the current detection MOS transistor is connected to a second input terminal of the comparison unit, a first input terminal of the comparison unit is connected to a reference voltage, the reference voltage is generated based on a voltage of the load terminal/charger terminal, and an output terminal of the comparison unit serves as a current detection output terminal.

26. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and a second input terminal of a comparison unit, a source of the field effect transistor is connected to a source of the current detection MOS transistor and a battery/battery pack terminal, a drain of the current detection MOS transistor is connected to a first input terminal of the comparison unit, an output terminal of the comparison unit serves as a current detection output terminal, and an output terminal of the comparison unit is connected to the first input terminal through a first resistor.

27. The integrated device according to claim 17, wherein a drain of the field effect transistor is connected to a load terminal/charger terminal and a drain of the current detection MOS transistor, a source of the current detection MOS transistor is connected to a second input terminal of a comparison unit, a first input terminal of the comparison unit is connected to a source of the field effect transistor, an output terminal of the comparison unit serves as a current detection output terminal, and an output terminal of the comparison unit and the second input terminal are connected to a first resistor.

28. A battery/battery management chip comprising an integrated device according to any one of claims 1 to 27.