CN214626468U

CN214626468U - Power device and battery management system

Info

Publication number: CN214626468U
Application number: CN202121075586.XU
Authority: CN
Inventors: 周号
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2021-11-05
Anticipated expiration: 2031-05-19

Abstract

The present disclosure provides a power device for detecting a charging current and a discharging current of a battery pack, the power device including: a discharge control transistor and a charge control transistor connected in series to constitute a control series circuit, and the series circuit is connected in a current loop between the battery pack side and the load/charger side; the drain electrode of the charging detection transistor is connected with the drain electrode of the charging control transistor, and the source electrode of the charging detection transistor is used as a charging current detection end; and the drain electrode of the discharge detection transistor is connected with the drain electrode of the discharge control transistor, and the source electrode of the discharge detection transistor is used as a discharge current detection end. The present disclosure also provides a battery management system.

Description

Power device and battery management system

Technical Field

The present disclosure provides a power device and a battery management system.

Background

Currently, a rechargeable battery is widely used in various fields, and a load is supplied with electric power through the rechargeable battery, and the rechargeable battery may also be charged by a charger.

During the charging and discharging process of the rechargeable battery, the charging current or the discharging current is too large, which may cause a safety accident, so the charging current and the discharging current of the rechargeable battery need to be detected to avoid the safety accident.

In the current detection process in the prior art, if a detection circuit for detecting a large current is adopted, a high requirement is put forward on a subsequent circuit, and if a small current is adopted for detection, the detection precision is not high.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides a power device and a battery management system.

According to an aspect of the present disclosure, a power device for detecting a charging current and a discharging current of a battery pack, the power device includes:

a discharge control transistor and a charge control transistor which are connected in series to constitute a control series circuit, and which are connected in a current loop between the battery pack side and the load/charger side;

the drain electrode of the charging detection transistor is connected with the drain electrode of the charging control transistor, and the source electrode of the charging detection transistor is used as a charging current detection end;

the drain electrode of the discharge detection transistor is connected with the drain electrode of the discharge control transistor, and the source electrode of the discharge detection transistor is used as a discharge current detection end; and

a sampling unit connected with the discharge current detection terminal and the charge current detection terminal respectively,

the sampling unit comprises a discharging sampling branch circuit connected with the discharging current detection end and a charging sampling branch circuit connected with the charging current detection end, the sampling unit comprises a sampling resistor, discharging current is collected according to voltage generated by the sampling resistor when discharging current sampling is carried out, and charging current is collected according to voltage generated by the sampling resistor when charging current sampling is carried out.

According to at least one embodiment of the present disclosure, the discharge sampling branch includes a first voltage fixing circuit and a first current mirror circuit,

the first voltage fixing circuit is connected to the discharge current detection terminal directly or indirectly, and the first voltage fixing circuit makes a source voltage of the discharge detection transistor equal to a source voltage of the discharge control transistor, and the first voltage fixing circuit allows a discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit for mirroring the discharge detection current to the sampling resistor.

According to at least one embodiment of the present disclosure, the first voltage fixing circuit includes a first operational amplifier and a first PMOS transistor, a source of the first PMOS transistor is connected to a source of the discharge detection transistor, an output terminal of the first operational amplifier is connected to a gate of the first PMOS transistor, a positive input terminal of the first operational amplifier is connected to a negative voltage terminal of the battery pack, a negative input terminal of the first operational amplifier is connected to a source of the first PMOS transistor, and a drain of the first PMOS transistor is connected to the first current mirror circuit inflow terminal.

According to at least one embodiment of the present disclosure, the charge sampling branch includes a second voltage fixing circuit, a second current mirror circuit, and a third current mirror circuit,

the second voltage fixing circuit is connected to the charging current detection terminal directly or indirectly, and the second voltage fixing circuit makes a source voltage of the charging detection transistor equal to a source voltage of the charging control transistor, and the second voltage fixing circuit allows a charging detection current detected by the charging detection transistor to flow into the second current mirror circuit for mirroring the charging detection current to the third current mirror circuit for mirroring the charging detection current to the sampling resistor.

According to at least one embodiment of the present disclosure, the second voltage fixing circuit includes a second operational amplifier and a second PMOS transistor, a source of the second PMOS transistor is connected to a source of the charge detection transistor, an output terminal of the second operational amplifier is connected to a gate of the second PMOS transistor, a positive input terminal of the second operational amplifier is connected to a negative voltage terminal of the load/charger side, a negative input terminal of the second operational amplifier is connected to a source of the second PMOS transistor, and a drain of the second PMOS transistor is connected to an inflow terminal of the second current mirror circuit.

According to at least one embodiment of the present disclosure, further comprising:

a first charge pump circuit that generates a voltage lower than a negative-voltage terminal voltage of the battery pack and supplies to an outflow terminal of the first current mirror circuit, and a second charge pump circuit that generates a voltage lower than a negative-voltage terminal voltage of the load/charger side and supplies to an outflow terminal of the second current mirror circuit; or

One charge pump circuit that generates a voltage lower than a negative-voltage terminal voltage of the battery pack and lower than a negative-voltage terminal voltage of the load/charger side, and that is supplied to outflow terminals of the first and second current mirror circuits.

According to at least one embodiment of the present disclosure, the first voltage fixing circuit includes a first operational amplifier and a first NMOS transistor, a source of the first NMOS transistor is connected with a source of the discharge detection transistor, an output terminal of the first operational amplifier is connected with a gate of the first NMOS transistor, and a positive input terminal of the first operational amplifier is connected with a negative voltage terminal of the battery pack, a negative input terminal of the first operational amplifier is connected with a source of the first NMOS transistor, and a drain of the first NMOS transistor is connected with an output terminal of the first current mirror circuit.

According to at least one embodiment of the present disclosure, the charging sampling branch includes a second voltage fixing circuit, the second voltage fixing circuit is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit allows the charging detection current detected by the charging detection transistor to flow to the sampling resistor.

According to at least one embodiment of the present disclosure, the second voltage fixing circuit includes a second operational amplifier and a second NMOS transistor, a source of the second NMOS transistor is connected to a source of the charge detection transistor, an output terminal of the second operational amplifier is connected to a gate of the second NMOS transistor, a positive input terminal of the second operational amplifier is connected to a negative voltage terminal of the load/charger, a negative input terminal of the second operational amplifier is connected to a source of the second NMOS transistor, and a drain of the second NMOS transistor is connected to the sampling resistor.

According to at least one embodiment of the present disclosure, the sampling circuit further includes a third operational amplifier, the sampling resistor is connected between one input end and the input end of the third operational amplifier, the other input end of the third operational amplifier is connected with a first voltage, and the voltage value of the first voltage is smaller than the power supply voltage and larger than the ground voltage.

According to at least one embodiment of the present disclosure, the first voltage is a common mode voltage; and/or the sampling resistor is connected with a filter capacitor in parallel.

According to at least one embodiment of the present disclosure, a channel length-to-width ratio of the charge detection transistor and a channel length-to-width ratio of the charge control transistor is 1: m, wherein M is greater than 1.

According to at least one embodiment of the present disclosure, the number of the charge detection transistors is N, where N is an integer equal to or greater than 1, and a channel aspect ratio of the nth charge detection transistor and a channel aspect ratio of the charge control transistor are 1: the power of M to the N-1.

According to at least one embodiment of the present disclosure, the charge control transistor and the charge detection transistor are NMOS transistors, and the value of M is 100.

According to at least one embodiment of the present disclosure, the number of the discharge detection transistors is N, where N is an integer of 1 or more, and a channel aspect ratio of the nth discharge detection transistor and a channel aspect ratio of the discharge control transistor are 1: the power of M to the N-1.

According to at least one embodiment of the present disclosure, the discharge control transistor and the discharge detection transistor are NMOS transistors, and the value of M is 100.

According to at least one embodiment of the present disclosure, a zener diode is connected between the gates and the sources of the charge control transistor, the charge detection transistor, the discharge control transistor, and the discharge detection transistor.

According to at least one embodiment of the present disclosure, gates of the charge control transistor and the charge detection transistor are respectively connected to a charge control signal and a charge detection control signal through a resistor, where the charge control signal and the charge detection control signal are the same control signal or different control signals, and/or charge detection control signals of the N charge detection transistors are the same control signal or different control signals; and

the grid electrodes of the discharge control transistor and the discharge detection transistor are respectively connected to the discharge control signal and the discharge detection control signal through resistors, the discharge control signal and the discharge detection control signal are the same control signal or different control signals, and/or the discharge detection control signals of the N discharge detection transistors are the same control signal or different control signals.

According to at least one embodiment of the present disclosure, the apparatus further includes a first gating unit and a second gating unit, the first gating unit being respectively connected with the N discharge detection transistors so as to switch the N discharge detection transistor connections through the first gating unit; the second gating unit is respectively connected with the N charging detection transistors, so that the connection of the N charging detection transistors is switched through the second gating unit.

According to another aspect of the present disclosure, a battery management system includes:

a power device as claimed in any one of the above;

the current acquisition unit is connected with the charging current detection end and the discharging current detection end of the power device so as to acquire the charging current and the discharging current of the battery pack.

a control unit that supplies the charge control signal, the charge detection control signal, the discharge control signal, and the discharge detection control signal to the power device so as to control charging and discharging of the battery pack.

According to at least one embodiment of the present disclosure, in a case where the power device includes N charge detection transistors and/or N discharge detection transistors, the battery management system further includes a gating unit, and the gating unit selects one charge detection transistor and/or one discharge detection transistor among the N charge detection transistors and/or N discharge detection transistors to obtain a current detection signal of a charge current and/or a discharge current.

According to at least one embodiment of the present disclosure, the apparatus further includes a detection current determination unit for determining a magnitude of the current detection signal, and the gate unit selects one of the N charge detection transistors and/or the N discharge detection transistors and/or one of the charge detection transistors and/or the discharge detection transistors based on the magnitude of the current detection signal.

According to at least one embodiment of the present disclosure, the current collection device further includes an analog-to-digital conversion unit that converts an output signal of the current collection unit into a digital signal.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 2 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

Fig. 3 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

Fig. 4 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

Fig. 5 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a power device according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of a powered device according to an embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of a power device according to one embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a power device according to one embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

According to one embodiment of the present disclosure, a power device is provided. The power device can be used for detecting the charging current and the discharging circuit of the battery pack.

Fig. 1 illustrates a power device according to one embodiment of the present disclosure. The power device may include a discharge control transistor 1000, a charge control transistor 2000, a discharge detection transistor 3000, a charge detection transistor 4000, and a sampling unit 5000.

Although a plurality of

discharge detection transistors

3010, 3020, …, 30n0 and

charge detection transistors

4010, 4020, …, 40n0 are shown in fig. 1. But one charge detection transistor and one discharge detection transistor may also be employed in the present disclosure. First, a charge detection transistor and a discharge detection transistor will be described as an example.

The discharge control transistor 1000 and the charge control transistor 2000 are connected in series to constitute a control series circuit, and the series circuit is connected in a current loop between the battery pack side and the load/charger side. For example, the discharge control transistor 1000 and the charge control transistor 2000 may be NMOS transistors in the present disclosure, although it will be understood by those skilled in the art that PMOS transistors may also be used. The discharge control transistor 1000 and the charge control transistor 2000 are connected in series to constitute a loop in which the control series circuit can be disposed on the low voltage side, and the discharge control transistor 1000 and the charge control transistor 2000 are connected in series to constitute a loop in which the control series circuit can be disposed on the high voltage side. The NMOS transistor and the low voltage side are used as an example for explanation, and the principle of the PMOS transistor or the PMOS transistor and the low voltage side are the same, and are not described again here.

The drain of the discharge detection transistor 3000 is connected to the drain (terminal D) of the discharge control transistor 1000, and the source of the discharge detection transistor 3000 serves as a discharge current detection terminal.

The drain of the charge detection transistor 4000 is connected to the drain (terminal D) of the charge control transistor 2000, and the source of the charge detection transistor 4000 serves as a charge current detection terminal.

The sampling unit 5000 is connected to the discharging current detecting terminal and the charging current detecting terminal, respectively, wherein the sampling unit 5000 includes a discharging sampling branch connected to the discharging current detecting terminal and a charging sampling branch connected to the charging current detecting terminal, and the sampling unit 5000 includes a sampling resistor, collects the discharging current according to a voltage generated by the sampling resistor when the discharging current sampling is performed, and collects the charging current according to a voltage generated by the sampling resistor when the charging current sampling is performed. The sampling resistor can be a built-in resistor of the device or an external resistor.

Fig. 2 and 3 show circuit diagrams of a sampling unit according to one embodiment of the present disclosure.

Where the discharge current detection case is shown in fig. 2 and the charge current detection case is shown in fig. 3.

The discharge sampling branch includes a first voltage fixing circuit 5010 and a first current mirror circuit 5020. The first voltage fixing circuit 5010 is directly or indirectly connected to a discharge current detecting terminal (source of the transistor 300), and the first voltage fixing circuit 5010 makes the source voltage of the discharge detecting transistor 3000 equal to the source voltage of the discharge controlling transistor 1000, and the first voltage fixing circuit 5010 allows the discharge detecting current I detected by the discharge detecting transistor 3000 to be detected_DSFlowing to the first current mirror circuit 5020, the first current mirror circuit 5020 is used to mirror the discharge detection current to the sampling resistor 5030.

The first voltage fixing circuit 5010 includes a first operational amplifier 5011 and a first PMOS transistor 5012, a source of the first PMOS transistor 5012 is connected to a source of the discharge detection transistor 3000, an output terminal of the first operational amplifier 5011 is connected to a gate of the first PMOS transistor 5012, a positive input terminal of the first operational amplifier 5011 is connected to a negative voltage terminal B of the battery pack, a negative input terminal of the first operational amplifier 511 is connected to a source of the first PMOS transistor 5012, and a drain of the first PMOS transistor 5012 is connected to a current input terminal of the first current mirror circuit 5020.

The first current mirror circuit includes an NMOS transistor 5021 and an NMOS transistor 5022, wherein the gates of the NMOS transistor 5021 and the NMOS transistor 5022 are connected, the drain of the NMOS transistor 5021 is connected to the output terminal of the first voltage fixing circuit 5010, the source of the NMOS transistor 5021 is connected to the-VDD terminal, the source of the NMOS transistor 5022 is connected to the-VDD terminal, the drain of the NMOS transistor 5022 is connected to one end of the sampling resistor 5030, and the other end of the sampling resistor 5030 can be grounded.

Thus, the voltage VSNS formed by the detected discharge current on the sampling resistor can be used to obtain the corresponding detected value of the discharge current.

As shown in fig. 3, the charge sampling branch includes a second voltage fixing circuit 5040, a second current mirror circuit 5050, and a third current mirror circuit 5060.

The second voltage fixing circuit 5040 is directly or indirectly connected to the charging current detection terminal (the source of the charge detection transistor 4000), and the second voltage fixing circuit 5040 makes the source voltage of the charge detection transistor 4000 equal to the source voltage of the charge control transistor, and the second voltage fixing circuit 5040 allows the charging detection current I detected by the charge detection transistor 4000_CSFlowing into the second current mirror circuit 5050, the second current mirror circuit 5050 is used to mirror the charge detection current to the third current mirror circuit 5060, and the third current mirror circuit 5060 is used to mirror the charge detection current to the sampling resistance.

The second voltage fixing circuit 5040 includes a second operational amplifier 5041 and a second PMOS transistor 5042, a source of the second PMOS transistor 5042 is connected to a source of the charge detection transistor, an output terminal of the second operational amplifier 5041 is connected to a gate of the second PMOS transistor 5042, and a positive input terminal of the second operational amplifier 5041 is connected to a negative voltage terminal on the load/charger side, a negative input terminal of the second operational amplifier 5041 is connected to a source of the second PMOS transistor 5042, and a drain of the second PMOS transistor 5042 is connected to a current inflow terminal of the second current mirror circuit 5050.

The second current mirror circuit 5050 includes an NMOS transistor 5051 and an NMOS transistor 5052, in which the gates of the NMOS transistor 5051 and the NMOS transistor 5052 are connected and connected to the drain of the NMOS transistor 5051, the drain of the NMOS transistor 5051 is connected to the output terminal of the second voltage fixing circuit 5040, the source of the NMOS transistor 5051 is connected to the-VDD terminal, the source of the NMOS transistor 5052 is connected to the-VDD terminal, and the drain of the NMOS transistor 5052 is connected to the third mirror circuit 5060.

The third current mirror circuit 5060 includes a PMOS transistor 5061 and a PMOS transistor 5062, with gates of the

PMOS transistors

5061 and 5062 connected, and a drain of the PMOS transistor 5061 connected. The sources of the

PMOS transistors

5061 and 5062 are connected to the supply voltage VDD. The drain of the PMOS transistor 5062 is connected to one end of the sampling resistor 5030, and the other end of the sampling resistor 5030 may be grounded.

Thus, the voltage VSNS formed by the detected charge detection current on the sampling resistor can be used to obtain the corresponding detected value of the discharge current.

According to a further embodiment of the present disclosure, further comprising: a first charge pump circuit CP1 and a second charge pump circuit CP2, the first charge pump circuit CP1 generates a voltage (-VDD) lower than the negative voltage terminal B-voltage of the battery pack and supplies to the outflow terminal of the first current mirror circuit 5020, the second charge pump circuit CP2 generates a voltage (-VDD) lower than the negative voltage terminal P-voltage on the load/charger side and supplies to the outflow terminal of the second current mirror circuit 5050. Although shown in the figure as a voltage (-VDD), the charge pump may generate voltages of other voltage values.

According to a further embodiment, the above two charge pump circuits may be implemented by one charge pump circuit that generates a voltage lower than the negative terminal voltage of the battery pack and lower than the negative terminal voltage on the load/charger side, and is supplied to the outflow terminals of the first current mirror circuit 5020 and the second current mirror circuit 5050.

A circuit diagram of another sampling unit is shown in fig. 4 and 5, according to another embodiment of the present disclosure. Fig. 4 shows a discharge detection case, and fig. 5 shows a charge detection case.

The discharge sampling branch includes a first voltage fixing circuit 5010 and a first current mirror circuit 5020,

the first voltage fixing circuit 5010 is connected directly or indirectly to the discharge current detecting terminal, and the first voltage fixing circuit 5010 makes the source voltage of the discharge detecting transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit 5010 allows the discharge detecting current detected by the discharge detecting transistor to flow into the first current mirror circuit 5020, the first current mirror circuit 5020 being for mirroring the discharge detecting current to the sampling resistor 5030.

The first voltage fixing circuit 5010 includes a first operational amplifier 5011 and a first NMOS transistor 5012, a source of the first NMOS transistor 5012 is connected to a source of the discharge detection transistor, an output terminal of the first operational amplifier 5011 is connected to a gate of the first NMOS transistor 5012, and a positive input terminal of the first operational amplifier 5011 is connected to a negative voltage terminal of the battery pack, a negative input terminal of the first operational amplifier 5011 is connected to a source of the first NMOS transistor 5012, and a drain of the first NMOS transistor 5012 is connected to an output terminal of the first current mirror circuit 5020.

The charge sampling branch circuit includes a second voltage fixing circuit 5040, the second voltage fixing circuit 5040 is directly or indirectly connected to the charge current detection terminal, and the second voltage fixing circuit 5040 makes the source voltage of the charge detection transistor equal to the source voltage of the charge control transistor, and the second voltage fixing circuit 5040 allows the charge detection current detected by the charge detection transistor to flow to the sampling resistor 5030.

The second voltage fixing circuit 5040 includes a second operational amplifier 5041 and a second NMOS transistor 5042, a source of the second NMOS transistor 5042 is connected to the source of the charge detection transistor 4000, an output of the second operational amplifier 5041 is connected to a gate of the second NMOS transistor 5042, a positive input of the second operational amplifier 5041 is connected to a negative voltage terminal of the load/charger, a negative input of the second operational amplifier 5041 is connected to a source of the second NMOS transistor 5042, and a drain of the second NMOS transistor 5042 is connected to the sampling resistor 5030.

The circuit further comprises a third operational amplifier 5070, wherein a sampling resistor 5030 is connected between one input end and the input end of the third operational amplifier 5070, and the other input end of the third operational amplifier 5070 is connected with a first voltage, wherein the voltage value of the first voltage is smaller than the power supply voltage and larger than the ground voltage. The first voltage may be a common-mode voltage V_CM。

In fig. 4 and 5, a filter capacitor 5080 may be connected in parallel to both ends of the sampling resistor as shown in fig. 4.

According to one embodiment of the present disclosure, a power device is provided.

Fig. 6 illustrates a power device 10 according to one embodiment of the present disclosure. The power device is used to control charging and discharging of the battery pack, and to detect a charging current and a discharging current of the battery pack.

As shown in fig. 6, the power device 10 may include: a charge control transistor 110 and a charge detection transistor 120. In the present disclosure, an NMOS transistor is taken as an example for illustration, but those skilled in the art should understand that it may also be a PMOS transistor.

The gate of the charge control transistor 110 is connected to a charge control signal GMA to control charging of the battery pack, wherein the source of the charge control transistor 110 is connected to one end SMA of the battery pack. When only the charge control transistor is included, the drain of the charge control transistor may be connected to the load/charger terminal. Wherein the charge control transistor may include a parasitic diode.

In addition, a zener diode 510 may be connected between the gate and the source of the charge control transistor 110 in order to prevent the gate of the charge control transistor 110 from being broken down. In fig. 6, a form of zener diode is shown, although other types of diodes may be selected. Which may include two zener diodes connected in series in opposite directions.

And the gate of the charge control transistor 110 may be connected to the charge control signal GMA through a resistor 111 to provide electrostatic protection, wherein the resistance of the resistor 111 may be 1K ohm.

The charge detection transistor 120 detects a charge current of the battery pack, a drain of the charge detection transistor 120 is connected to a drain of the charge control transistor 110, a gate of the charge detection transistor 120 is connected to a charge control signal GMA, and a source of the charge detection transistor serves as a charge current detection terminal SMA 1. The charge detection transistor 120 may include a parasitic diode, among others.

Further, a zener diode 411 may be connected between the gate and the source of the charge detection transistor 120 in order to prevent the gate of the charge detection transistor 120 from being broken down. In fig. 6, a form of zener diode is shown, although other types of diodes may be selected. Which may include two zener diodes connected in series in opposite directions.

And the gate of the charge detection transistor 120 may be connected to the charge control signal GMA through a resistor 311 to provide electrostatic protection, wherein the resistance of the resistor 111 may be 100K ohms.

The channel aspect ratio of the charge detection transistor 211 and the channel aspect ratio of the charge control transistor 110 are 1: m, wherein M is greater than 1. For example, the value of M may be 100, 1000, 10000, etc.

The number of the charge detection transistors 211 is N, where N is an integer greater than or equal to 1, and the channel aspect ratio of the nth charge detection transistor and the channel aspect ratio of the charge control transistor are 1: the power of N-1 of M, wherein i is an integer greater than or equal to 1, and the value of i changes along with the value of N. For example, it is shown that N

charge detection transistors

211, 212, …, 21N are included and have

respective resistors

311, 312, …, 31N and

respective diodes

411, 412, …, 41N. Each charge detection transistor is connected in the same manner, with the difference being in the ratio to the channel aspect ratio of the charge control transistor 110. The connection method is not described in detail herein.

The value of M is an integer multiple of 10, preferably 100. The channel length-width ratio of the nth charge detection transistor to the charge control transistor is 1: the power of M to the N-1.

For example, the length to width ratio of the channel of the transistor 211 to the transistor 110 is 1:100, the length to width ratio of the channel of the transistor 212 to the channel of the transistor 110 is 1:1000, the length to width ratio of the channel of the third transistor to the transistor 110 is 1:10000, and the length to width ratio of the channel of the Nth transistor 21N to the transistor 110 is N-1 power of 1: 100.

According to a further embodiment of the present disclosure, the power device 10 further comprises: and a discharge control transistor 120, wherein the gate of the discharge control transistor 120 is connected to a discharge control signal GMB to control the discharge of the battery pack, the drain of the discharge control transistor 120 is connected to the drain of the charge control transistor 110, and the source of the discharge control transistor 120 is connected to one terminal SMB of the load/charger. Wherein the discharge control transistor may include a parasitic diode.

In addition, a zener diode 520 may be connected between the gate and the source of the discharge control transistor 120 in order to prevent the gate of the discharge control transistor 120 from being broken down. In fig. 6, a form of zener diode is shown, although other types of diodes may be selected. Which may include two zener diodes connected in series in opposite directions.

And the gate of the discharge control transistor 120 may be connected to the discharge control signal GMB through a resistor 121 to provide electrostatic protection, wherein the resistance of the resistor 121 may be 1K ohm.

Further, a zener diode 421 may be connected between the gate and the source of the discharge detection transistor 221 in order to prevent the gate of the discharge detection transistor 221 from being broken down. In fig. 6, a form of zener diode is shown, although other types of diodes may be selected. Which may include two zener diodes connected in series in opposite directions.

And the gate of the discharge detection transistor 221 may be connected to the discharge control signal GMB through a resistor 321 to provide electrostatic protection, wherein the resistance of the resistor 321 may be 100K ohms.

The channel aspect ratio of the discharge detection transistor 221 and the channel aspect ratio of the discharge control transistor 120 are 1: m, wherein M is greater than 1. For example, the value of M may be 100, 1000, 10000, etc.

The number of the discharge detection transistors 221 is N, where N is an integer greater than or equal to 1, and the channel length-width ratio of the nth discharge detection transistor and the channel length-width ratio of the discharge control transistor are 1: the power of N-1 of M, wherein i is an integer greater than or equal to 1, and the value of i changes along with the value of N. For example, it is shown that N

discharge detection transistors

221, 222, …, 22N are included and have

respective resistors

321, 322, …, 32N and

respective diodes

421, 422, …, 42N. Each discharge detection transistor is connected in the same manner, with the difference being in the ratio to the channel aspect ratio of the discharge control transistor 120. The connection method is not described in detail herein.

The value of M is an integer multiple of 10, preferably 100. The length-to-width ratio of the channel of the Nth discharge detection transistor to the channel of the discharge control transistor is 1: the power of M to the N-1.

For example, the length to width ratio of the channel of the

transistors

221 and 120 is 1:100, the length to width ratio of the channel of the

transistors

222 and 120 is 1:1000, the length to width ratio of the channel of the third transistor and 120 is 1:10000, and the length to width ratio of the channel of the Nth transistor 22N and the transistor 120 is N-1 power of 1: 100.

A first temperature detection part 610 is connected to the source of the charge control transistor 110 and a second temperature detection part 620 is connected to the source of the discharge control transistor 120, the first and second temperature detection parts being used to detect the temperature of the battery pack. The first temperature detection part is a first diode, the second temperature detection part is a second diode, the cathode of the first diode is connected with the source electrode of the charging control transistor, the cathode of the second diode is connected with the source electrode of the discharging control transistor, and the anodes of the first diode and the second diode are used as temperature detection output ends. The temperature detection output end of the first temperature detection part is D1P, and the temperature detection output end of the second temperature detection part is D2P. The anode of the first diode may be connected to the resistor 611, and the other end of the resistor 611 may serve as the temperature detection output terminal D1P, the anode of the second diode may be connected to the resistor 612, and the other end of the resistor 612 may serve as the temperature detection output terminal D2P.

In the present disclosure, the charge control transistor and the charge detection transistor are the same type of transistor, and the discharge control transistor and the discharge detection transistor are the same type of transistor. Or all four are the same type of MOS transistors.

It will be appreciated by those skilled in the art that the larger the channel width to length ratio of a MOS transistor, the smaller the on-resistance and thus the greater the current flowing through it. In the present disclosure, the on-resistance of the charge and discharge control transistor is small by the large aspect ratio, so that the energy consumed in the charge and discharge circuit is small. When the current needs to be detected, the detection transistor with the small channel width and length ratio is used, so that the on-resistance of the detection transistor is large, the current flowing through the detection transistor is small, the detection can be convenient, and the requirements of large current resistance of a subsequent acquisition unit and the like are not needed. Meanwhile, the detection transistor is positioned in the detection branch circuit, so that the normal charge and discharge loop cannot be influenced, for example, the electric energy of a battery is consumed.

In the case where a plurality of charge detection transistors are included, which charge detection transistor is used for detection can be switched by a circuit external to the device depending on the magnitude of the detected charge current. For example, the transistor 211 can be used to obtain a detection current, and when the detection current is too large, the transistor 212 can be switched to obtain the detection current, and when the detection current is larger, the transistor can be switched to another transistor. When the detected charging current is too small, reverse sequential switching may also be performed. In addition, the charge detection transistor used to detect the charge current may be selected according to the specific value of the detected charge current.

In the case where a plurality of discharge detection transistors are included, it is possible to switch which discharge detection transistor is used for detection depending on the magnitude of the detected discharge current by an external circuit of the device. For example, the transistor 221 can obtain a detection current, and when the detection current is too large, the transistor 222 can be switched to obtain the detection current, and when the detection current is larger, the transistor can be switched to another transistor. When the detected discharge current is too small, switching may be performed in reverse order. In addition, the discharge detection transistor used to detect the discharge current may be selected according to the specific value of the detected discharge current.

Fig. 7 shows a schematic block diagram of a battery management system according to one embodiment of the present disclosure.

The power device 10 may be connected in series between the battery pack 20 and the charger/load to control charging and discharging, and also to detect charging and discharging currents, and also to detect temperature. Wherein the temperature detection end can be connected with an external acquisition unit.

The control unit 30 may provide control signals GMA and GMB to the power device 10.

Fig. 8 shows a schematic block diagram of a battery management system according to one embodiment of the present disclosure.

Wherein the battery management system may include the power device described above. The description of the above power devices is incorporated by reference in its entirety in this section.

The battery management system may include a current collection unit connected to the charging current detection terminal and the discharging current detection terminal of the power device so as to collect charging current and discharging current of the battery pack.

The battery management system may further include: and a control unit providing the charging control signal and the discharging control signal to the power device so as to control charging and discharging of the battery pack.

In the case where the power device includes N charge detection transistors and/or N discharge detection transistors, the battery management system may further include a gating unit, and the gating unit selects one of the N charge detection transistors and/or the N discharge detection transistors and/or one of the charge detection transistors and/or the discharge detection transistors to obtain a current detection signal of the charge current and/or the discharge current.

The battery management system may further include a detected current determination unit for determining a magnitude of the current detection signal, and the gating unit may select one of the N charge detection transistors and/or one of the N discharge detection transistors and/or one of the N charge detection transistors based on the magnitude of the current detection signal.

The battery management system can also comprise an analog-to-digital conversion unit, wherein the analog-to-digital conversion unit converts the output signal of the current acquisition unit into a digital signal.

For example, the current judging unit controls the gating unit to switch according to the charging current and the discharging current collected by the collecting unit so as to determine which charging detection transistor and/or discharging detection transistor is selected. Therefore, the current with proper size can be selected for collection, so that the device is prevented from being damaged when the current is too large, and the sampling precision is damaged when the current is too small.

In addition, the present disclosure may further include an adjusting unit after the analog-to-digital converting unit to adjust the detected value of the current according to a ratio of a channel width-to-length ratio between the charge controlling transistor and the charge detecting transistor so that the detected value of the current truly reflects the actual current.

For example, at one stage, such as the transistor 211 with the aspect ratio of the charge control transistor 110 being 100 times, and at another stage, such as the transistor 212 with the aspect ratio of the charge control transistor 110 being 1000 times, the ratio of the two values will not match if no adjustment is made at a later stage. Therefore, subsequent current detection values can be subsequently adjusted according to the setting of the width-to-length ratio in the present disclosure.

Further, although the description has been made above in the form of a power device, in the present disclosure, each transistor may not necessarily be made as a power device, but may take the form of a detection circuit. In the following, the detection circuit is briefly described, the entire content of the power device is introduced into this section, and the rest will not be described again.

The detection circuit is used for detecting the charging current and the discharging current of the battery pack, the charging control transistor controls the battery pack to discharge, the grid electrode of the charging control transistor is connected with the charging control signal to control the charging of the battery pack, the source electrode of the charging control transistor is connected with one end of the battery pack, the discharging control transistor controls the discharging of the battery pack, the grid electrode of the discharging control transistor is connected with the discharging control signal to control the discharging of the battery pack, the drain electrode of the discharging control transistor is connected with the drain electrode of the charging control transistor, the source electrode of the discharging control transistor is connected with one end of the load/charger, and the detection circuit comprises: the charging detection transistor detects the charging current of the battery pack, the drain electrode of the charging detection transistor is connected with the drain electrode of the charging control transistor, the grid electrode of the charging detection transistor is connected with a charging control signal, and the source electrode of the charging detection transistor is used as a charging current detection end; and

a discharge detection transistor, the discharge detection transistor detects a discharge current of the battery pack, a drain of the discharge detection transistor is connected with a drain of the discharge control transistor, a gate of the discharge detection transistor is connected with a discharge control signal, and a source of the discharge detection transistor is used as a discharge current detection terminal, wherein a channel length-width ratio of the charge detection transistor and a channel length-width ratio of the charge control transistor are 1: m, the length-width ratio of the channel of the discharge detection transistor to the length-width ratio of the channel of the discharge control transistor is 1: m, wherein M is greater than 1.

The number of the charge detection transistors is N, wherein N is an integer greater than or equal to 1, and the length-to-width ratio of the channel of the Nth discharge detection transistor to the length-to-width ratio of the channel of the discharge control transistor is 1: the power of M to the N-1 power; and the number of the discharge detection transistors is N, wherein N is an integer greater than or equal to 1, and the length-width ratio of the channel of the Nth discharge detection transistor to the length-width ratio of the channel of the discharge control transistor is 1: the power of M to the N-1.

The charge control transistor and the charge detection transistor are NMOS transistors, and the value of M is an integer multiple of 10, preferably 100; the discharge control transistor and the discharge detection transistor are NMOS transistors, and the value of M is an integer multiple of 10, preferably 100.

A first temperature detection section is connected to a source of the charge control transistor and a second temperature detection section is connected to a source of the discharge control transistor, the first temperature detection section and the second temperature detection section being for detecting a temperature of the battery pack.

The first temperature detection part is a first diode, the second temperature detection part is a second diode, the cathode of the first diode is connected with the source electrode of the charging control transistor, the cathode of the second diode is connected with the source electrode of the discharging control transistor, and the anodes of the first diode and the second diode are used as temperature detection output ends.

Zener diodes are connected between the grid electrodes and the source electrodes of the charging control transistor, the charging detection transistor, the discharging control transistor and the discharging detection transistor.

The gates of the charge control transistor and the charge detection transistor are respectively connected to the charge control signal through resistors, and the gates of the discharge control transistor and the discharge detection transistor are respectively connected to the discharge control signal through resistors.

The present disclosure also provides an electric device, such as a power tool, a portable terminal, an electric vehicle, and the like. As shown in fig. 9, the electric device may include the above-mentioned power device, battery management system, or detection circuit.

Additionally, fig. 10 and 11 illustrate alternative embodiments according to the present disclosure. Wherein fig. 6 differs from fig. 10 in that the charge control transistor is controlled by a single control signal GMA, while the plurality of charge detection transistors are controlled by the same control signal GMA 1; the discharge control transistor is controlled by a single control signal GMB, while the discharge detection transistors are controlled by the same control signal GMB 1. Fig. 11 differs from fig. 10 in that a plurality of charge detection transistors are controlled by a plurality of control signals GMA1, GMA2, …, GMAn, respectively; the plurality of discharge detection transistors are controlled by a plurality of control signals GMB1, GMB2, …, and GMBn, respectively.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. A power device for detecting a charging current and a discharging current of a battery pack, comprising:

2. The power device of claim 1 wherein the discharge sampling branch comprises a first voltage fixing circuit and a first current mirror circuit,

3. The power device according to claim 2, wherein the first voltage fixing circuit includes a first operational amplifier and a first PMOS transistor, a source of the first PMOS transistor is connected to a source of the discharge detection transistor, an output terminal of the first operational amplifier is connected to a gate of the first PMOS transistor, and a positive input terminal of the first operational amplifier is connected to a negative voltage terminal of the battery pack, a negative input terminal of the first operational amplifier is connected to a source of the first PMOS transistor, and a drain of the first PMOS transistor is connected to the first current mirror circuit inflow terminal.

4. The power device of claim 1, wherein the charge sampling branch comprises a second voltage fixing circuit, a second current mirror circuit, and a third current mirror circuit,

5. The power device according to claim 4, wherein the second voltage fixing circuit includes a second operational amplifier and a second PMOS transistor, a source of the second PMOS transistor is connected to a source of the charge detection transistor, an output terminal of the second operational amplifier is connected to a gate of the second PMOS transistor, and a positive input terminal of the second operational amplifier is connected to the negative voltage terminal on the load/charger side, a negative input terminal of the second operational amplifier is connected to a source of the second PMOS transistor, and a drain of the second PMOS transistor is connected to the inflow terminal of the second current mirror circuit.

6. The power device of claim 3 or 5, further comprising:

7. The power device of claim 1 wherein the discharge sampling branch comprises a first voltage fixing circuit and a first current mirror circuit,

8. The power device according to claim 7, wherein the first voltage fixing circuit includes a first operational amplifier and a first NMOS transistor, a source of the first NMOS transistor is connected to a source of the discharge detection transistor, an output terminal of the first operational amplifier is connected to a gate of the first NMOS transistor, and a positive input terminal of the first operational amplifier is connected to a negative voltage terminal of the battery pack, a negative input terminal of the first operational amplifier is connected to a source of the first NMOS transistor, and a drain of the first NMOS transistor is connected to an output terminal of the first current mirror circuit.

9. The power device according to claim 1, wherein the charge sampling branch includes a second voltage fixing circuit which is directly or indirectly connected to the charge current detection terminal and which makes a source voltage of the charge detection transistor equal to a source voltage of the charge control transistor and which allows the charge detection current detected by the charge detection transistor to flow to the sampling resistor.

10. The power device of claim 9, wherein the second voltage fixing circuit comprises a second operational amplifier and a second NMOS transistor, a source of the second NMOS transistor is connected to a source of the charge detection transistor, an output terminal of the second operational amplifier is connected to a gate of the second NMOS transistor, a positive input terminal of the second operational amplifier is connected to a negative voltage terminal of the load/charger, a negative input terminal of the second operational amplifier is connected to a source of the second NMOS transistor, and a drain of the second NMOS transistor is connected to the sampling resistor.

11. The power device according to any one of claims 7 to 10, further comprising a third operational amplifier, wherein the sampling resistor is connected between one input terminal and an input terminal of the third operational amplifier, and a first voltage is connected to the other input terminal of the third operational amplifier, and the voltage value of the first voltage is smaller than a supply voltage and larger than a ground voltage.

12. The power device of claim 11,

the first voltage is a common mode voltage; and/or

And the sampling resistor is connected with a filter capacitor in parallel.

13. The power device according to claim 1, wherein a channel length-to-width ratio of the charge detection transistor and a channel length-to-width ratio of the charge control transistor is 1: m, wherein M is greater than 1.

14. The power device according to claim 1, wherein the number of the charge detection transistors is N, where N is an integer of 1 or more, and a channel length-to-width ratio of the nth charge detection transistor and a channel length-to-width ratio of the charge control transistor are 1: the power of M to the N-1.

15. The power device of claim 14 wherein the charge control transistor and the charge detection transistor are NMOS transistors and the value of M is 100.

16. The power device according to claim 15, wherein the number of the discharge detection transistors is N, where N is an integer of 1 or more, and a channel length-to-width ratio of the nth discharge detection transistor and a channel length-to-width ratio of the discharge control transistor are 1: the power of M to the N-1.

17. The power device of claim 16 wherein said discharge control transistor and said discharge sense transistor are NMOS transistors and M has a value of 100.

18. The power device of claim 17 wherein zener diodes are connected between the gates and sources of the charge control transistor, the charge detection transistor, the discharge control transistor, and the discharge detection transistor.

19. The power device of claim 17,

the grid electrodes of the charging control transistor and the charging detection transistor are respectively connected to a charging control signal and a charging detection control signal through resistors, the charging control signal and the charging detection control signal are the same control signal or different control signals, and/or the charging detection control signals of the N charging detection transistors are the same control signal or different control signals; and

20. The power device according to claim 19, further comprising a first gating unit and a second gating unit, the first gating unit being respectively connected to the N discharge detection transistors so as to switch the N discharge detection transistor connections through the first gating unit; the second gating unit is respectively connected with the N charging detection transistors, so that the connection of the N charging detection transistors is switched through the second gating unit.

21. A battery management system, comprising:

the power device of any one of claims 1 to 20;

22. The battery management system of claim 21, further comprising:

23. The battery management system according to claim 22, wherein, in the case where the power device includes N charge detection transistors and/or N discharge detection transistors, the battery management system further includes a gating unit, and the gating unit selects one charge detection transistor and/or one discharge detection transistor among the N charge detection transistors and/or N discharge detection transistors to obtain a current detection signal of a charge current and/or a discharge current.

24. The battery management system according to claim 23, further comprising a detected current judging unit that judges a magnitude of a current detection signal, and the gating unit selects one charge detecting transistor and/or one discharge detecting transistor among the N charge detecting transistors and/or N discharge detecting transistors based on the magnitude of the current detection signal.

25. The battery management system according to any one of claims 21 to 24, further comprising an analog-to-digital conversion unit that converts an output signal of the current collection unit into a digital signal.