CN212381302U

CN212381302U - Video recorder

Info

Publication number: CN212381302U
Application number: CN202021131740.6U
Authority: CN
Inventors: 彭淼
Original assignee: Hunan Junwei Lianhang Technology Co ltd
Current assignee: Hunan Junwei Lianhang Technology Co ltd
Priority date: 2020-06-18
Filing date: 2020-06-18
Publication date: 2021-01-19
Anticipated expiration: 2030-06-18

Abstract

The utility model discloses a video recorder, which comprises an outer shell, be equipped with power module in the shell, video input output module and video coding and decoding module, be equipped with on the shell with video input output module assorted input/output interface, power module is connected with video input output module and video coding and decoding module power supply respectively, video input output module passes through PCIe interface connection with video coding and decoding module, video input output module includes the FPGA chip and input/output memory chip and the input/output nonvolatile memory who is connected with the FPGA chip respectively, including being equipped with two way Camera link signal input interfaces on the FPGA chip, DVI input interface all the way, PAL input interface all the way, Camera link signal output interface all the way and two way input/output redundant net gapes, video coding and decoding module includes image processor and the coding and decoding memory chip who is connected with image processor respectively, A coding and decoding nonvolatile memory and a solid state disk.

Description

Video recorder

Technical Field

The utility model belongs to the technical field of video recording, concretely relates to video recorder.

Background

The video recorder is electronic recording equipment widely applied in the current society, and can well restore the scenes because the video recorder can be connected with video acquisition equipment through an interface, the video information acquired by the video acquisition equipment is stored, and can be extracted through an output interface to be played back by display equipment.

In the prior art, most of input and output of a video recorder and compression, coding and decoding of video information are completed by a core processor, and for input and output of multi-channel video information, the real-time processing efficiency of the input and output information is inevitably reduced while the storage and reading speed of the video information is ensured, and when the video recorder is applied to important fields such as military and the like, the video information is ensured not to be lost under the condition of unexpected power failure.

SUMMERY OF THE UTILITY MODEL

In order to solve at least one of the above technical problems, the utility model provides a video recorder.

The purpose of the utility model is realized through the following technical scheme:

the utility model provides a video recorder, which comprises an outer shell, be equipped with power module, video input/output module and video coding and decoding module in the shell, be equipped with on the shell with video input/output module assorted input/output interface, power module is connected with video input/output module and video coding and decoding module power supply respectively, video input/output module passes through PCIe interface connection with video coding and decoding module, video input/output module includes the FPGA chip and respectively with the input/output memory chip and the input/output nonvolatile memory that the FPGA chip is connected, including being equipped with two way Camera link signal input interface on the FPGA chip, DVI input interface all the way, one way the PAL input interface, one way the Camera link signal output interface and two way input/output redundant net gapes, video coding and decoding module includes image processor and codes and decodes memory chip that is connected with image processor respectively, A coding and decoding nonvolatile memory and a solid state disk.

As a further improvement, the video encoding and decoding module includes two gigabit ethernet ports, one RS232 interface, one RS422 interface, one debugging network port, and one SATA interface, and the solid state disk is connected to the image processor through the SATA interface.

As a further improvement, the input-output nonvolatile memory is a NOR FLASH chip, and the codec nonvolatile memory includes a NOR FLASH chip and an NAND FLASH chip.

As a further improvement, a self-destruction button is arranged on the shell and connected with an image processor, and the image processor is connected with pins of the solid state disk.

As a further improvement, a level shifter is arranged between the power module and the video input and output module, and a level shifter is arranged between the power module and the video encoding and decoding module.

As a further improvement, a video decoder is arranged between the PAL input interface and the FPGA chip.

As a further improvement, the PAL input interface employs a four-channel analog video decoder TW9984 chip.

As a further improvement, the image processor is a Hi3531D chip.

As a further improvement, the input-output memory chip and the codec memory chip are DDR 3.

As a further improvement, the Camera Link signal input interface adopts a DS90CR288A chip, the DVI input interface adopts a TFP401 chip, and the Camera Link signal output interface adopts a DS90CR287 chip.

The utility model provides a pair of video recorder, which comprises an outer shell, be equipped with power module, video input/output module and video coding and decoding module in the shell, be equipped with on the shell with video input/output module assorted input/output interface, power module is connected with video input/output module and video coding and decoding module power supply respectively, video input/output module passes through PCIe interface connection with video coding and decoding module, video input/output module includes the FPGA chip and respectively with the input/output memory chip and the input/output nonvolatile memory that the FPGA chip is connected, including being equipped with two way Camera link signal input interfaces on the FPGA chip, DVI input interface all the way, one way PAL input interface, one way Camera link signal output interface and two way input/output redundant net gapes, video coding and decoding module includes image processor and codes and decodes memory chip that is connected with image processor respectively, A coding and decoding nonvolatile memory and a solid state disk.

The utility model discloses owing to adopted above-mentioned structure, have following advantage:

1. the FPGA chip and the image processor are combined, the FPGA chip realizes input and output processing of video information, the image processor realizes compression, coding and storage of the video information, and the storage and reading speed of the video information is not influenced while the input and output real-time processing of multi-path video information is ensured;

2, an input/output nonvolatile memory is connected to the FPGA chip, and an encoding/decoding nonvolatile memory is connected to the image processor, so that video information is ensured not to be lost under the condition of sudden power failure or shutdown;

3. the multi-channel video information input interface supports the input of multi-channel digital video signals and analog video signals, and two channels of input and output redundant network ports ensure the real-time performance of network transmission and the smoothness of network transmission.

4. Compared with TF cards, the solid state disk has the advantages of large capacity, stable data transmission, high access speed, and no delay or pause in pictures when the stored video is checked.

Drawings

The present invention is further explained by using the drawings, but the embodiments in the drawings do not constitute any limitation to the present invention, and for those skilled in the art, other drawings can be obtained according to the following drawings without any inventive work.

Fig. 1 is a schematic structural diagram of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the following detailed description of the present invention is provided with reference to the accompanying drawings and specific embodiments, and it should be noted that the embodiments and features of the embodiments of the present invention can be combined with each other without conflict.

With reference to fig. 1, an embodiment of the present invention provides a video recorder, which includes a housing, and a power module, a video input/output module and a video encoding/decoding module are disposed in the housing. The video input and output module comprises an FPGA chip, an input and output storage chip and an input and output nonvolatile memory, wherein the input and output storage chip and the input and output nonvolatile memory are respectively connected with the FPGA chip. The model of the FPGA chip of the embodiment is XC7K325T-2FFG900I, the number of available input and output interfaces of the chip can reach 500, and the design requirements of multiple input and output interfaces are met. The input and output memory chip is DDR3, and DDR3 selects 2 pieces of magnesium light MT41K256M16 HA. The input and output nonvolatile memory is a NOR FLASH chip, and a small amount of video information can be directly processed in the NOR FLASH chip without reading the video information into an FPGA chip during the input and output processing of the video information, so that the operation burden of the FPGA chip can be reduced.

The video coding and decoding module comprises an image processor, a coding and decoding storage chip, a coding and decoding nonvolatile memory and a solid state disk, wherein the coding and decoding storage chip, the coding and decoding nonvolatile memory and the solid state disk are respectively connected with the image processor. The image processor of this embodiment is a Hi3531D chip, which has a video encoder, is a multi-protocol encoder supporting h.265/h.264/JPEG/MJPEG, and includes two parts, a VEDU encoder and a JPGE encoder, wherein the VEDU encoder implements encoding of h.265 and h.264 protocols, the JPGE encoder implements encoding of JPEG/MJPEG protocols, and the chip also has a video decoder and a video capture unit, and can receive video data through bt.656 and bt.1120 interfaces. The encoding and decoding memory chip is DDR3, and DDR3 selects 2 pieces of magnesium light MT41K256M16 HA. The encoding and decoding nonvolatile memory comprises a NOR FLASH chip and an NAND FLASH chip, and the NOR FLASH chip has high information reading speed, so that a small amount of video information can be directly processed, the NAND FLASH chip can achieve high storage density, the writing and erasing speeds are high, and the encoding and decoding nonvolatile memory is suitable for storing a large amount of data. Because the video coding and decoding module is mainly used for storing compressed video information, in order to ensure that video data which is being processed and is not written into the solid state disk can be well stored under the condition of no current supply, the NOR FLASH chip and the NAND FLASH chip are arranged and used interchangeably at the same time.

The video input and output module is connected with the video coding and decoding module through a PCIe interface and used for high-speed storage and reading of video information between the video input and output module and the video coding and decoding module. The FPGA chip comprises two Camera link signal input interfaces, a DVI input interface, a PAL input interface, a Camera link signal output interface and two input/output redundant network ports, wherein a video decoder is arranged between the PAL input interface and the FPGA chip. In this embodiment, the Camera Link signal input interface uses a DS90CR288A chip, the DVI input interface uses a TFP401 chip, converts the digital signal of the video information into an LVTTL signal and inputs the LVTTL signal into the FPGA chip, the PAL input interface uses a four-channel analog video decoder TW9984 chip, the chip has a built-in analog video encoder, the analog video encoder can re-encode the video information into a CVBS format, the video information can output different formats to match the display device, at most four PAL inputs and one PAL output are supported, and the Camera Link signal output interface uses a DS90CR287 chip. And video information input from the four input interfaces is converted into data in the formats of two BT.1120 and two BT.656 interfaces by the FPGA chip and is transmitted to the video coding and decoding module. A Camera link signal output interface is connectable to a display device for playback of video information. The two paths of input and output redundant network ports are connected with an FPGA chip through an RTL8211E chip, the chip belongs to a physical layer in network communication and is used for data communication between an MAC and a PHY, and real-time switching of the network can be guaranteed when data report is wrong in the network receiving process.

The video coding and decoding module comprises two kilomega Ethernet ports, one RS232 interface, one RS422 interface, one debugging network port and one SATA3.0 interface, and the solid state disk is connected with the image processor through the SATA3.0 interface. Two kilomega Ethernet ports can be used for transmitting local area network data, one RS422 interface can be used for transmitting control instructions, configuring the mirror image function of video information, sending data of characters and target frames superimposed on the video information and the like, one RS232 interface serves as a standby interface, and the other debugging network port is used for debugging the video coding and decoding module.

The power supply module is respectively connected with the video input and output module and the video coding and decoding module in a power supply mode. The input power supply of the power supply module is direct current 12V, and the chips connected with the video input and output module and the video coding and decoding module and the devices in the video input and output module and the video coding and decoding module are converted into different power supply voltages through the level converter, so that the safe and stable working power supply of the whole equipment is provided. In this embodiment, the level shifter is mainly implemented by the TPS54820 and the TPS54320, and both have functions of OVP, OCP, OTP, SS, PG, and the like, thereby facilitating power-on timing control.

The shell is provided with an input/output interface matched with the video input/output module, so that the shell is conveniently connected with video acquisition equipment and video display equipment. The shell is provided with a self-destruction button connected with the image processor, the image processor is connected with pins of the solid state disk, and after the self-destruction button is triggered, the image processor sends low-level pulses to the pins of the solid state disk to start the self-destruction of the solid state disk, so that the leakage of important video information on the solid state disk is avoided.

In the description above, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore should not be construed as limiting the scope of the invention.

In conclusion, although the present invention has been described with reference to the preferred embodiments, it should be noted that, although various changes and modifications can be made by those skilled in the art, unless such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.

Claims

1. The video recorder is characterized by comprising a shell, wherein a power supply module, a video input/output module and a video coding/decoding module are arranged in the shell, an input/output interface matched with the video input/output module is arranged on the shell, the power supply module is respectively in power supply connection with the video input/output module and the video coding/decoding module, the video input/output module is connected with the video coding/decoding module through a PCIe interface, the video input/output module comprises an FPGA chip, an input/output storage chip and an input/output nonvolatile memory, the input/output storage chip and the input/output nonvolatile memory are respectively connected with the FPGA chip, the FPGA chip comprises two Camera link signal input interfaces, one DVI input interface, one PAL input interface, one Camera link signal output interface and two input/output redundant network ports, and the video coding/decoding module comprises an image processor and a coding/decoding storage chip, a PAL input/output interface, a PAL input/, A coding and decoding nonvolatile memory and a solid state disk.

2. The video recorder of claim 1, wherein the video codec module includes two gigabit ethernet ports, one RS232 interface, one RS422 interface, one debugging network port, and one SATA interface, and the solid state disk is connected to the image processor through the SATA interface.

3. The video recorder of claim 1, wherein said input-output nonvolatile memory is a NOR FLASH chip and said codec nonvolatile memory includes a NOR FLASH chip and an NAND FLASH chip.

4. The video recorder according to claim 2, wherein the housing has a self-destruct button and is connected to an image processor, the image processor being connected to a pin of the solid state drive.

5. The video recorder of claim 1, wherein a level shifter is disposed between the power module and the video input/output module, and a level shifter is disposed between the power module and the video codec module.

6. The video recorder of claim 1, wherein a video decoder is provided between the PAL input interface and the FPGA chip.

7. The video recorder of claim 6, wherein said PAL input interface employs a four-channel analog video decoder TW9984 chip.

8. A video recorder as claimed in claim 1, wherein the image processor is a Hi3531D chip.

9. The video recorder of claim 1, wherein the input-output memory chip and the codec memory chip are DDR 3.

10. The video recorder of claim 1, wherein said Camera Link signal input interface uses a DS90CR288A chip, said DVI input interface uses a TFP401 chip, and said Camera Link signal output interface uses a DS90CR287 chip.