CN101222600A

CN101222600A - High-speed image recording method based on memory bank array

Info

Publication number: CN101222600A
Application number: CNA2008100567897A
Authority: CN
Inventors: 陈强; 徐启明; 张启衡; 彭先蓉
Original assignee: Institute of Optics and Electronics of CAS
Current assignee: Institute of Optics and Electronics of CAS
Priority date: 2008-01-24
Filing date: 2008-01-24
Publication date: 2008-07-16

Abstract

A recording device adopted based on the recording method consists of a programmable logic device FPGA, a hundred mega network module, a DDR1 memory bank array module and a high-speed camera interface module, wherein the DDR1 memory bank array module comprises N DDR1 memory banks; the method is characterized in that: the FPGA is used for controlling the cooperative operation of N DDR1 memory banks in the DDR1 memory bank array module, the high-speed and high-capacity image data recording is realized by using a high-speed burst read-write mode, and meanwhile, the hundred-megabyte network module is used for communicating with a remote computer host, so that a scheme of remote off-line recording is realized; the recording method of the invention is used for recording high-speed image data, is convenient to operate, greatly improves the recording speed and breaks through the rate bottleneck of the traditional recording scheme.

Description

A kind of high speed image recording method based on memory array

Technical field

The present invention relates to a kind of recording method of high speed image data, particularly a kind of high speed image recording method based on memory array.

Background technology

Measure in the application in some modern high speed, for the instantaneous high speed variation characteristic of the physical message of Measuring Object, need to adopt video acquisition means at a high speed, as high-speed CCD, the cmos digital camera carries out IMAQ, and the thing followed is the storage problem of high-speed figure image data stream, and digital image acquisition at a high speed needs digital image recording apparatus at a high speed as guarantee, the high speed image recording technology has a wide range of applications in the experiment of microcosmic biological respinse at vehicle crash test.

From storage medium, present recording medium is mainly hard disc, and it adopts the mechanical type addressing system, has that the read-write clock frequency is low, the concurrent reading and concurrent writing figure place is few, produce shortcoming such as bad track immediately, has greatly limited read-write speed.The lasting read-write speed of single-deck can only reach several megabyte per seconds to tens megabyte per seconds, and the writing speed that finish the hundreds of megabyte per second needs a large amount of hard disks to carry out cascade, and bulky, the capacity extension difficulty is big, the complexity height; Portability is not strong, and operation easier is big, is difficult to realize high-speed record.

Divide from the scheme of record, common record scheme is Host Based record at present; View data enters main frame by the image pick-up card that is inserted on the main frame pci bus, enters the host computer system internal memory by pci bus under the scheduling of computer operating system, deposits the hard disk storage medium of host computer system at last in; Because high speed image data stream is subjected to the restriction of pci bus bandwidth (133 megabyte per second) and host performance greatly by way of pci bus event writing speed; Because operating system has redundancy overhead to increase the efficient that the stability event has reduced the disk read-write operation, make writing speed not high, inconvenient operation simultaneously.

Summary of the invention

The technical problem to be solved in the present invention: in order to overcome the deficiencies in the prior art, the present invention utilizes the N root DDR1 memory bar in the programmable logic device FPGA control DDR1 memory array module to carry out co-operation, programmable logic device FPGA pin is abundant, the holding wire of the required interpolation of the little and every interpolation one root memory bar of memory bar volume seldom, add the inner abundant programmable logic resource of FPGA and make that the capacity extension of this array is very easy; Utilize the read-write mode of bursting at a high speed to realize the Imagery Data Recording of high speed high power capacity, controlling 100,000,000 mixed-media network modules mixed-medias by programmable logic cells FPGA simultaneously comes and the remote computer main-machine communication, carry out the transmission of order and the remote backup of reception and data, thereby realized the scheme of long-range off line record, improved ease of use.

The technical solution adopted for the present invention to solve the technical problems is: a kind of high speed image recording method based on memory array, be made up of programmable logic device FPGA, 100,000,000 mixed-media network modules mixed-medias, DDR1 memory array module, high speed camera interface module four parts based on the tape deck that this recording method is adopted, wherein DDR1 memory array module includes N root DDR1 memory bar; This recording method is characterised in that: utilize the N root DDR1 memory bar co-operation in the programmable logic device FPGA control DDR1 memory array module, utilize the read-write mode of bursting at a high speed to realize the Imagery Data Recording of high speed high power capacity simultaneously, utilize 100,000,000 mixed-media network modules mixed-medias to come and the remote computer main-machine communication, thereby realized the scheme of long-range off line record.

Described memory array co-operation refers to: synchronization can only have a memory bar in running order, carries out the high speed read-write, and the memory bar of all the other non operating states is in the self-refresh state is waited until work order with the state of low-power consumption arrival; Programmable logic device FPGA places operating state in system initialisation phase with the first root memory bar, and all the other memory bars are placed non operating state; Programmable logic device FPGA activates next root memory bar and places the state maintenance data of self-refresh state with low-power consumption to operating state and with the memory bar that work finishes behind the first root memory bar end of operation; The rest may be inferred, all is changed to non operating state to wait for order next time behind the complete operation up to all memory bars.

The read-write mode that described high speed is burst refers to: for the efficient that improves the memory bar operation promptly improves memory bar average read-write speed, adopt the method for the data volume that improves a read-write operation; Utilize programmable logic device FPGA in read-write operation of memory bar, to travel through the data of 1024 memory cell of all row (column) in inner certain delegation of this memory bar (row), in read-write operation next time, travel through the data of 1024 memory cell of all row (column) in another row (row) then, because each unit storage bit wide is 64bit, thereby finished the high-speed data operation that the length of bursting is 8K (1024*64bit) byte.

The present invention compared with prior art has following advantage:

1, the present invention utilizes the two-forty read write attribute of dynamic memory medium DDR1 memory bar, and promptly operating frequency is more than 100MHZ, and Double Data Rate is operated, concurrent reading and concurrent writing bit wide 64bit; Adopt programmable logic device FPGA directly to control DDR1 memory bar read-write operation; Adopt the read-write mode of bursting at a high speed simultaneously, make the lasting writing speed of peak value arrive 1.46G byte per second, broken through the speed bottleneck of traditional record scheme, improved writing speed greatly thereby improved read-write efficiency greatly;

2, the invention provides and a kind ofly realized the high-speed record scheme of a highly integrated constant volume on the veneer, have the good advantage of capacity extension in the mode of utilizing programmable logic device FPGA to control the collaborative work of many DDR1 memory bars on the hardware platform.

3, thereby the present invention utilizes programmable logic device FPGA to control 100,000,000 mixed-media network modules mixed-medias to have realized and the remote computer main-machine communication, greatly facilitated the transmission of order and data, and has realized the scheme of long-range off line record, and remote operation is more convenient.

Description of drawings

Fig. 1 is the structural representation based on the high speed image recording device of memory array;

Fig. 2 is the internal structure schematic diagram based on the DDR1 memory array module of the high speed image recording device of memory array;

Fig. 3 be based on the high speed image recording device of memory array programmable logic device FPGA internal structure schematic diagram.

Embodiment

Introduce the present invention in detail below in conjunction with the drawings and specific embodiments.

A kind of based on the involved tape deck of the high speed image recording method of memory array by programmable logic device FPGA, DDR1 memory array module, 100,000,000 mixed-media network modules mixed-medias, the high speed camera interface module is formed; Shown in the frame of broken lines of Fig. 1; Wherein DDR1 memory array module adopts N DDR1 memory bar to form the memory array module, as the storage medium of high speed image, chooses the memory array module of being made up of 4 DDR1 memory bars here, as shown in Figure 2;

Wherein programmable logic device FPGA inside comprises again: DDR1 memory array control module, 100,000,000 network control modules, image interface module are as shown in Figure 3.

A kind of high speed image recording method based on memory array adopts said apparatus, and utilize 4 DDR1 memory bars co-operation in the programmable logic device FPGA control DDR1 memory array module, utilize the read-write mode of bursting at a high speed to realize the Imagery Data Recording of high speed high power capacity simultaneously, utilize 100,000,000 mixed-media network modules mixed-medias to come and the remote computer main-machine communication, thereby realized the scheme of long-range off line record.

Its physical record process is as follows: main frame remotely sends record order to 100,000,000 mixed-media network modules mixed-medias by netting twine, so 100,000,000 network control modules of programmable logic device FPGA inside receive this 100,000,000 mixed-media network modules mixed-media data and resolve command; Produce control signal then and inform that the DDR1 memory array control module preparation of programmable logic device FPGA inside enters operating state, meanwhile 100,000,000 network control modules inform that according to the order of resolving the image interface module of programmable logic device FPGA inside receives view data that the high speed camera interface module brings to prepare to carry out recording operation, the image interface module of programmable logic device FPGA inside is responsible at first the high speed image data buffer memory being entered this inside modules and view data being pieced together from a new two field picture becoming the operating data for the treatment of that width is 64bit, and the DDR1 memory array control module of notice programmable logic device FPGA inside prepares to receive high-speed data; When data cached the reaching of the image interface module of programmable logic device FPGA inside promptly begins data record when a DDR1 memory array control module is burst the data volume 8K byte of writing (data volume 1024 * 8 bytes of memory bar one row), thereby the DDR1 memory array control module of programmable logic device FPGA inside constantly judges the image buffer storage data volume in the image interface module of programmable logic device FPGA inside and constantly carries out the high speed record of bursting, and endlessly high speed image data recorded the memory bar in running order in the DDR1 memory array module in the mode of bursting; When this memory bar is write full data, thereby the DDR1 memory array control module of programmable logic device FPGA inside activates an other memory bar and the memory bar of closing in the work at present is finished handover operation; The memory bar that activates is proceeded the high-speed data write operation, and remaining memory bar then is in the self-refresh state; The DDR1 memory array control module of programmable logic device FPGA inside is then controlled these 4 DDR1 memory bars and is carried out co-ordination; When 4 DDR1 memory bars all write down full or all read empty back main frame long-range send cease and desist order after, stop record this moment and the wait main frame sends backup command or sends record order again by 100,000,000 mixed-media network modules mixed-medias are long-range; After backup command arrived, the DDR1 memory array control module of programmable logic device FPGA inside will be sent to the data in the DDR1 memory array module 100,000,000 mixed-media network modules mixed-medias and be transferred to long-range main frame by netting twine carried out data backup; Realized and the communicating by letter of telecomputing machine host by 100,000,000 mixed-media network modules mixed-medias, greatly facilitated the transmission of order and data, realized the scheme of long-range off line record, and the method has been easy to operate.

Claims

1. high speed image recording method based on memory array, be made up of programmable logic device FPGA, 100,000,000 mixed-media network modules mixed-medias, DDR1 memory array module, high speed camera interface module four parts based on the tape deck that this recording method is adopted, wherein DDR1 memory array module includes N root DDR1 memory bar; This recording method is characterised in that: utilize the N root DDR1 memory bar co-operation in the programmable logic device FPGA control DDR1 memory array module, utilize the read-write mode of bursting at a high speed to realize the Imagery Data Recording of high speed high power capacity simultaneously, utilize 100,000,000 mixed-media network modules mixed-medias to come and the remote computer main-machine communication, thereby realized the scheme of long-range off line record.

2. a kind of high speed image recording method according to claim 1 based on memory array, it is characterized in that: the described N root DDR1 memory bar co-operation that utilizes programmable logic device FPGA to control in the DDR1 memory array module refers to: synchronization can only have a memory bar in running order, carry out the high speed reads write operation, the memory bar of all the other inoperatives is in the self-refresh state is waited until work order with the state of low-power consumption arrival; Programmable logic device FPGA places operating state in system initialisation phase with the first root memory bar, and all the other memory bars are placed non operating state; Programmable logic device FPGA activates next root memory bar and places the state maintenance data of self-refresh state with low-power consumption to operating state and with the memory bar that work finishes after first root memory bar record is expired or read sky; The rest may be inferred, all is set to non operating state to wait for the arrival of order next time behind the complete operation up to all memory bars.

3. a kind of high speed image recording method according to claim 1 based on memory array, it is characterized in that: the read-write mode that described high speed is burst refers to: for the efficient that improves the memory bar operation promptly improves memory bar average read-write speed, adopt the method for the data volume that improves a read-write operation; Utilize programmable logic device FPGA in read-write operation of memory bar, to travel through the data of 1024 memory cell of all row (column) in inner certain delegation of this memory bar (row), in read-write operation next time, travel through the data of 1024 memory cell of all row (column) in another row (row) then, because each unit storage bit wide is 64bit, thereby finished the high-speed data operation that the length of bursting is 8K (1024*64bit) byte.