CN212381218U - Half-duplex data transmission circuit and electronic device - Google Patents
Half-duplex data transmission circuit and electronic device Download PDFInfo
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- CN212381218U CN212381218U CN202020736470.5U CN202020736470U CN212381218U CN 212381218 U CN212381218 U CN 212381218U CN 202020736470 U CN202020736470 U CN 202020736470U CN 212381218 U CN212381218 U CN 212381218U
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Abstract
The utility model relates to a half-duplex data transmission circuit and electron device, include: the power supply unit comprises a data input end and a first data interface of a data output end; a second data interface for connecting the lower terminal; the timing trigger unit is connected with the data output end and is respectively connected with the data input end, the data output end, the timing trigger unit and the data conversion unit of the second data interface; the timing trigger unit outputs a first trigger level when the data output end outputs a first level, outputs a second trigger level when the data output end outputs a second level and times the duration time of the second trigger level to output the first trigger level; when the data conversion unit receives the first triggering level, the data input end is in communication connection with the second data interface, and when the data conversion unit receives the second triggering level, the data output end is in communication connection with the second data interface. Implement the utility model discloses reduce software system resource consumption, improve system job stabilization nature.
Description
Technical Field
The utility model relates to an electronic circuit technical field, more specifically say, relate to a half-duplex data transmission circuit and electron device.
Background
The data transmission process in the existing half-duplex communication generally adopts the switching of the transceiving channels to realize the data receiving and transmitting process. When the existing upper computer uses software to control the asynchronous serial transceiver to communicate with the RS485 terminal, under the condition of heavy load of system software of the upper computer, the asynchronous serial transceiver has frequent transceiving, which causes frequent transceiving switching of half duplex and half duplex, and causes excessive occupation of system resources including memory, CPU occupancy rate and the like, thereby causing abnormal software system. When an upper computer with limited performance is encountered, for example, a low-cost single chip microcomputer or an embedded system which consumes a large amount of system resources due to excessive demands, asynchronous serial communication may occupy excessive resources to cause system memory overflow to cause system downtime, and thus system working stability is affected.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to prior art's above-mentioned technical defect, a half-duplex data transmission circuit and electron device are provided.
The utility model provides a technical scheme that its technical problem adopted is: a half-duplex data transmission circuit is constructed comprising: the power supply unit is used for connecting a first data interface of the upper computer, wherein the first data interface comprises a data input end and a data output end; a second data interface for connecting the lower terminal; the timing trigger unit is connected with the data output end, and the data conversion unit is respectively connected with the data input end, the data output end, the timing trigger unit and the second data interface;
the timing trigger unit outputs a first trigger level when the data output end outputs a first level, outputs a second trigger level when the data output end outputs a second level, times the duration of the second trigger level, and outputs the first trigger level when the timing exceeds a preset time length;
when the data conversion unit receives the first trigger level, the data input end is in communication connection with the second data interface, and when the data conversion unit receives the second trigger level, the data output end is in communication connection with the second data interface.
Preferably, the timing trigger unit comprises a monostable trigger U1 and a preset duration setting unit connected with the monostable trigger U1;
the preset duration setting unit comprises a capacitor C2 and a resistor R5, a first end of the resistor R5 is connected with the power supply unit, a second end of the resistor R5 is respectively connected with a fifteenth pin of the monostable flip-flop U1 and a first end of the capacitor C2, and a second end of the capacitor C2 is connected with a fourteenth pin of the monostable flip-flop U1.
Preferably, the monostable flip-flop U1 has a device model number of 74HCT 123.
Preferably, the data conversion unit includes an RS485 transceiver U2, the fourth pin and the fifth pin of the RS485 transceiver U2 are connected to each other and then connected to the timing trigger unit, the third pin of the RS485 transceiver U2 is connected to the data input terminal, the sixth pin of the RS485 transceiver U2 is connected to the data output terminal, the twelfth pin and the thirteenth pin of the RS485 transceiver U2 are respectively connected to the second data interface, the second pin and the eighth pin of the RS485 transceiver U2 are respectively connected to the first power ground and are grounded to the timing trigger unit, and the ninth pin and the fifteenth pin of the RS485 transceiver U2 are respectively connected to the second power ground and are grounded to the second data interface.
Preferably, the RS485 transceiver U2 has a device model number ADM2483 BRWZ.
Preferably, the second data interface includes a first data transmission end and a second data transmission end, and a protection circuit respectively connected to the first data transmission end and the second data transmission end;
the protection circuit includes an EMI protection circuit, an ESD protection circuit, and/or a surge protection circuit.
Preferably, the EMI protection circuit includes an EMI inductor L1, a first pin and a fourth pin of the EMI inductor L1 are respectively connected to the data conversion unit, a third pin of the EMI inductor L1 is connected to the first data transmission terminal, and a second pin of the EMI inductor L1 is connected to the second data transmission terminal; and/or
The ESD protection circuit comprises a first bidirectional TVS transistor D1 and a second bidirectional TVS transistor D2, wherein a first terminal of the first bidirectional TVS transistor D1 is connected to the first data transmission terminal, a second terminal of the first bidirectional TVS transistor D1 is connected to ground, a first terminal of the second bidirectional TVS transistor D2 is connected to the second data transmission terminal, and a second terminal of the second bidirectional TVS transistor D2 is connected to ground; and/or
The surge protection circuit comprises a gas discharge tube GDT1, a first pin of the gas discharge tube GDT1 is connected with the second data transmission end, a second pin of the gas discharge tube GDT1 is connected with the first data transmission end, and a third pin of the gas liner tube GDT1 is grounded.
Preferably, the first data transmission terminal is an RS485A signal terminal, and the second data transmission terminal is an RS485B signal terminal.
Preferably, the second data interface further includes one or more connectors correspondingly connected to the first data transmission terminal and the second data transmission terminal.
In addition, the present invention also provides an electronic device including the half-duplex data transmission circuit according to any one of the above aspects.
Implement the utility model discloses a half-duplex data transmission circuit and electron device has following beneficial effect: the resource consumption of a software system is reduced, and the working stability of the system is improved.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a logic block diagram of a half-duplex data transmission circuit according to the present invention;
fig. 2 is a schematic circuit diagram of an embodiment of a half-duplex data transmission circuit according to the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, in an embodiment of the present invention, a half-duplex data transmission circuit includes: the power supply unit is used for connecting a first data interface 110 of an upper computer, wherein the first data interface 110 comprises a data input end 112 and a data output end 111; a second data interface 140 for connecting the lower terminal; the timing trigger unit 120 is connected with the data output end 111, and the data conversion unit 130 is respectively connected with the data input end 112, the data output end 111, the timing trigger unit 120 and the second data interface 140; the timing trigger unit 120 outputs a first trigger level when the data output end 111 outputs a first level, outputs a second trigger level when the data output end 111 outputs a second level, times the duration of the second trigger level, and outputs the first trigger level when the time exceeds a preset time; the data input terminal 112 is communicatively coupled to the second data interface 140 when the data conversion unit 130 receives the first trigger level, and the data output terminal 111 is communicatively coupled to the second data interface 140 when the data conversion unit 130 receives the second trigger level. Specifically, the power supply unit is connected with the working modules and used for providing working power supplies for the working modules in the transmission circuit. The first data interface 110 is used to connect an upper computer, which may be a system or a device supporting half-duplex communication, and the output communication data may be output through a data output end 111 and sent to a corresponding data receiving device after being processed, and may also receive the communication data output by a data transmitting device communicatively connected thereto through a data input end 112. The corresponding data receiving device and data transmitting device may be lower terminals, and the lower terminals transmit communication data through the second data interface 140 to the upper computer through the first data input end 112, and receive the communication data transmitted from the upper computer through the second data interface 140 and the data output end 111, so as to transmit the communication data between the upper computer and the lower terminals. The transmission process of the communication data between the upper computer and the lower terminal triggers the data conversion unit 130 through the timing trigger unit 120 to realize the switching of the receiving path and the transmitting path. The specific process is that when the upper computer is in a state of not sending data, that is, the data output end 111 does not output a signal, and the output signal corresponds to a low level, at this time, the timing trigger unit 120 outputs a first trigger level, that is, the timing trigger unit corresponds to the low level, and the data conversion unit 130 works in a first working state after receiving the low level, that is, the data input end 112 is in communication connection with the second data interface 140 through the data conversion unit 130 to form a receiving channel of the data of the upper computer, and in addition, the communication data of the terminal can be sent to the upper computer through the receiving channel to be received. When the upper computer is in a state of sending data, the data output end 111 of the upper computer has an output signal which is correspondingly high level, at this time, the timing trigger unit 120 outputs a second trigger level which is correspondingly high level, the data conversion unit 130 works in a second working state after receiving the high level, namely, the data output end 111 is in communication connection with the second data interface 140 through the data conversion unit 130 to form a sending channel of the data of the upper computer, and in addition, the terminal can receive the sending data from the upper computer through the sending channel. The first operating state and the second operating state of the data conversion unit 130 may correspond to two conducting states, that is, one way conduction is formed in the first operating state to conduct the data input terminal 112 and the second data interface 140, and the other way conduction is formed in the second operating state to conduct the data output terminal 111 and the second data interface 140. In addition, when the timing trigger unit 120 internally counts the duration of the second trigger level when outputting the second trigger level, and switches to output the first trigger level, i.e., switches to output a low level when the timing exceeds a preset value, so that the data conversion unit 130 is in a receiving state.
As shown in fig. 2, in an embodiment, the timing trigger unit 120 includes a monostable trigger U1 and a preset duration setting unit 121 connected to the monostable trigger U1; the preset duration setting unit 121 includes a capacitor C2 and a resistor R5, a first end of the resistor R5 is connected to the power supply unit, a second end of the resistor R5 is connected to a fifteenth pin of the monostable flip-flop U1 and a first end of the capacitor C2, respectively, and a second end of the capacitor C2 is connected to a fourteenth pin of the monostable flip-flop U1. Specifically, the timing trigger unit 120 implements output of the trigger signal and timing switching of the trigger signal through the monostable flip-flop U1. The timing switching process may set the switching duration of the monostable flip-flop U1 through the preset duration setting unit 121, specifically, the switching duration is matched through the capacitor C2 and the resistor R5, the monostable timer function of the monostable flip-flop U1 is triggered, and the preset duration of the timer is set, and the acquisition of the timing duration is tw (ns) ═ 0.45 × R5(k Ω) × C2 (pF). I.e., the monostable flip-flop U1 returns to a low output after the high output exceeds Tw.
Optionally, the data conversion unit 130 includes an RS485 transceiver U2, the timing trigger unit 120 is connected after the fourth pin and the fifth pin of the RS485 transceiver U2 are connected to each other, the third pin of the RS485 transceiver U2 is connected to the data input terminal 112, the sixth pin of the RS485 transceiver U2 is connected to the data output terminal 111, the twelfth pin and the thirteenth pin of the RS485 transceiver U2 are respectively connected to the second data interface 140, the second pin and the eighth pin of the RS485 transceiver U2 are connected to the first power ground 151 and are grounded to the timing trigger unit 120, and the ninth pin and the fifteenth pin of the RS485 transceiver U2 are connected to the second power ground 152 and are grounded to the second data interface 140. Specifically, the data conversion unit 130 may use the RS485 transceiver U2 to perform data conversion and transmission, and receive the first trigger signal or the second trigger signal of the timing trigger unit 120 through the fourth pin and the fifth pin, and switch the third pin to be conducted with the twelfth pin and the thirteenth pin thereof when receiving the first trigger signal, and switch the sixth pin to be conducted with the twelfth pin and the thirteenth pin thereof when receiving the second trigger signal. The RS485 transceiver U2 is isolated at one end connected to the upper computer from one end connected to the lower terminal. One end of the upper computer is connected with the timing trigger unit 120 in common, namely, connected with the first power ground 151, and one end of the lower terminal is connected with the second data interface 140 in common, namely, connected with the second power ground 152, and the two power grounds are isolated from each other. To ensure that the transmitting and receiving signals do not interfere with each other.
Optionally, the second data interface 140 includes a first data transmission terminal 141 and a second data transmission terminal 142, and a guard circuit respectively connected to the first data transmission terminal 141 and the second data transmission terminal 142; the protection circuitry includes EMI protection circuitry 143, ESD protection circuitry 144, and/or surge protection circuitry 145. The second data interface 140 may adopt a differential data transmission interface formed by a first data transmission terminal 141 and a second data transmission terminal 142, and is provided with a protection circuit for protecting the data transmission interface, and the specific protection circuit may include one or more of an EMI protection circuit 143, an ESD protection circuit 144, and a surge protection circuit 145.
Optionally, the EMI protection circuit 143 includes an EMI inductor L1, a first pin and a fourth pin of the EMI inductor L1 are respectively connected to the data conversion unit 130, a third pin of the EMI inductor L1 is connected to the first data transmission terminal 141, and a second pin of the EMI inductor L1 is connected to the second data transmission terminal 142; i.e., the differential data transmission interface may be EMI-suppressed by the EMI inductor L1.
Optionally, the ESD protection circuit 144 includes a first bidirectional TVS transistor D1 and a second bidirectional TVS transistor D2, a first terminal of the first bidirectional TVS transistor D1 is connected to the first data transmission terminal 141, a second terminal of the first bidirectional TVS transistor D1 is grounded, a first terminal of the second bidirectional TVS transistor D2 is connected to the second data transmission terminal 142, and a second terminal of the second bidirectional TVS transistor D2 is grounded; that is, the differential data transmission interface may be ESD-suppressed by the first and second bidirectional TVS transistors D1 and D2 that connect the first and second data transmission terminals 141 and 142. It is to be understood that the ground of the first and second bidirectional TVS tubes D1 and D2 are both the second power ground.
Optionally, the surge protection circuit 145 includes a gas discharge tube GDT1, a first pin of the gas discharge tube GDT1 is connected to the second data transmission terminal 142, a second pin of the gas discharge tube GDT1 is connected to the first data transmission terminal 141, and a third pin of the gas discharge tube GDT1 is grounded. That is, the differential data transmission interface can be protected from surge or lightning through the gas discharge tube GDT 1.
Optionally, the first data transmission terminal 141 is an RS485A signal terminal, and the second data transmission terminal 142 is an RS485B signal terminal. It is understood that the differential data transmission interface may be an RS485 communication interface, wherein the first data transmission terminal 141 is an RS485A signal terminal, and the second data transmission terminal 142 is an RS485B signal terminal.
Optionally, the second data interface 140 further includes one or more connectors correspondingly connected to the first data transmission terminal 141 and the second data transmission terminal 142. Specifically, the first data transmission terminal 141 and the second data transmission terminal 142 may be connected to corresponding lower terminals through one or more connectors, so as to implement data communication between an upper computer and one or more terminal devices.
In one specific circuit shown in fig. 2, the monostable flip-flop U1 has a device model number 74HCT123 and the RS485 transceiver U2 has a device model number ADM2483 BRWZ. The differential data transmission interface may be an RS485 communication interface. A sending signal GPIO14 of the upper computer is respectively connected with a first pin of a monostable trigger U1 and a sixth pin of an RS485 transceiver U2; a receiving signal GPIO15 of the upper computer is connected with a third pin of an RS485 transceiver U2; the thirteenth pin of the monostable flip-flop U1 is connected with the fourth pin and the fifth pin of the RS485 transceiver U2. When the upper computer GPIO14 is in a non-signal-sending state, i.e., at a low level, the thirteenth pin of the monostable flip-flop U1 outputs a low level, i.e., the fourth pin and the fifth pin of the RS485 transceiver U2 are in a low level state, the RS485 transceiver U2 is in a receiving state, and then RS485 receiving data of the twelfth pin and the thirteenth pin are sent to the upper computer GPIO15 through the third pin. When the upper computer GPIO14 starts to send a signal state, namely a high level, the first pin of the monostable flip-flop U1 detects the signal conversion from a low level to a high level of the GPIO14, the thirteenth pin of the monostable flip-flop U1 is controlled to output at a high level, the fourth pin and the fifth pin of the RS485 transceiver U2 are in a high level state, the RS485 transceiver U2 is in a sending state, and then a signal of the upper computer GPIO14 is sent to the RS-485 equipment through the RS485 transceiver U2. Meanwhile, the high level output time of the thirteenth pin is controlled by the resistor R5 and the flashlight C2, and when the timing time is over, the 1Q pin of the thirteenth pin of the monostable flip-flop U1 is recovered to be low level output. And the system is recovered until the upper computer has data sent out through the GPIO14, and the monostable trigger U1 and the RS485 transceiver U2 are triggered, so that the data communication between the upper computer and one or more RS485 terminals is completed through the cyclic switching. The thirteenth pin of the RS485 transceiver U2 is connected to the first pin of the EMI inductor L1, and the twelfth pin of the RS485 transceiver U2 is connected to the fourth pin of the EMI inductor L1, so as to perform EMI suppression on RS485 data.
In the limited host computer of performance, if low-cost singlechip or because the demand has consumeed too much system resource's embedded system, can pass through the utility model discloses realized the simple half-duplex data communication at host computer and RS-485 terminal with hardware configuration's mode, effectively reduced software system resource consumption, can avoid because asynchronous serial communication probably causes the problem that the system memory spills over and leads to the machine of dying, improve the stability of system work.
In addition, an electronic device of the present application includes any one of the above half-duplex data transmission circuits, and the half-duplex data transmission circuit and the data processing system are disposed in the electronic device, and the duplex data transmission circuit is connected to the data processing system, so as to realize stable data transmission between the electronic device and a lower terminal.
It is to be understood that the foregoing examples merely represent preferred embodiments of the present invention, and that the description thereof is more specific and detailed, but not intended to limit the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. A half-duplex data transmission circuit, comprising: the power supply unit is used for connecting a first data interface of the upper computer, wherein the first data interface comprises a data input end and a data output end; a second data interface for connecting the lower terminal; the timing trigger unit is connected with the data output end, and the data conversion unit is respectively connected with the data input end, the data output end, the timing trigger unit and the second data interface;
the timing trigger unit outputs a first trigger level when the data output end outputs a first level, outputs a second trigger level when the data output end outputs a second level, times the duration of the second trigger level, and outputs the first trigger level when the timing exceeds a preset time length;
when the data conversion unit receives the first trigger level, the data input end is in communication connection with the second data interface, and when the data conversion unit receives the second trigger level, the data output end is in communication connection with the second data interface.
2. The half-duplex data transmission circuit according to claim 1, wherein the timing trigger unit comprises a monostable trigger U1 and a preset duration setting unit connected to the monostable trigger U1;
the preset duration setting unit comprises a capacitor C2 and a resistor R5, a first end of the resistor R5 is connected with the power supply unit, a second end of the resistor R5 is respectively connected with a fifteenth pin of the monostable flip-flop U1 and a first end of the capacitor C2, and a second end of the capacitor C2 is connected with a fourteenth pin of the monostable flip-flop U1.
3. The half-duplex data transmission circuit of claim 2 wherein the monostable flip-flop U1 has a device model number of 74HCT 123.
4. The half-duplex data transmission circuit as claimed in claim 1, wherein the data conversion unit comprises an RS485 transceiver U2, the timing trigger unit is connected after the fourth pin and the fifth pin of the RS485 transceiver U2 are connected to each other, the third pin of the RS485 transceiver U2 is connected to the data input terminal, the sixth pin of the RS485 transceiver U2 is connected to the data output terminal, the twelfth pin and the thirteenth pin of the RS485 transceiver U2 are respectively connected to the second data interface, the second pin and the eighth pin of the RS485 transceiver U2 are respectively connected to the first power ground and are grounded to the timing trigger unit, and the ninth pin and the fifteenth pin of the RS485 transceiver U2 are respectively connected to the second power ground and are grounded to the second data interface.
5. The half-duplex data transmission circuit of claim 4 wherein the RS485 transceiver U2 has a device model number ADM2483 BRWZ.
6. The half-duplex data transmission circuit according to claim 1, wherein the second data interface comprises a first data transmission terminal and a second data transmission terminal, and a guard circuit respectively connected to the first data transmission terminal and the second data transmission terminal;
the protection circuit includes an EMI protection circuit, an ESD protection circuit, and/or a surge protection circuit.
7. The half-duplex data transmission circuit of claim 6,
the EMI protection circuit comprises an EMI inductor L1, a first pin and a fourth pin of the EMI inductor L1 are respectively connected with the data conversion unit, a third pin of the EMI inductor L1 is connected with the first data transmission terminal, and a second pin of the EMI inductor L1 is connected with the second data transmission terminal; and/or
The ESD protection circuit comprises a first bidirectional TVS transistor D1 and a second bidirectional TVS transistor D2, wherein a first terminal of the first bidirectional TVS transistor D1 is connected to the first data transmission terminal, a second terminal of the first bidirectional TVS transistor D1 is connected to ground, a first terminal of the second bidirectional TVS transistor D2 is connected to the second data transmission terminal, and a second terminal of the second bidirectional TVS transistor D2 is connected to ground; and/or
The surge protection circuit comprises a gas discharge tube GDT1, a first pin of the gas discharge tube GDT1 is connected with the second data transmission end, a second pin of the gas discharge tube GDT1 is connected with the first data transmission end, and a third pin of the gas liner tube GDT1 is grounded.
8. The half-duplex data transmission circuit as claimed in claim 6, wherein the first data transmission terminal is an RS485A signal terminal, and the second data transmission terminal is an RS485B signal terminal.
9. The half-duplex data transmission circuit of claim 6 wherein the second data interface further comprises one or more connectors correspondingly connected to the first data transmission port and the second data transmission port.
10. An electronic device comprising a half-duplex data transmission circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020736470.5U CN212381218U (en) | 2020-05-07 | 2020-05-07 | Half-duplex data transmission circuit and electronic device |
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| CN202020736470.5U CN212381218U (en) | 2020-05-07 | 2020-05-07 | Half-duplex data transmission circuit and electronic device |
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Effective date of registration: 20220414 Address after: 518000 zone 3, mezzanine, Jiali Fubao warehouse building, No. 15, Taohua Road, Fubao street, Futian District, Shenzhen, Guangdong Province Patentee after: Anfuli Electronic Technology (Shenzhen) Co.,Ltd. Address before: 4 / F, block B, Nanshan cloud Valley Innovation Industrial Park, 4093 Liuxian Avenue, Taoyuan Street, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN EMBEST TECHNOLOGY Co.,Ltd. |
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