CN207612059U - Chip interface circuit - Google Patents
Chip interface circuit Download PDFInfo
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- CN207612059U CN207612059U CN201721287279.1U CN201721287279U CN207612059U CN 207612059 U CN207612059 U CN 207612059U CN 201721287279 U CN201721287279 U CN 201721287279U CN 207612059 U CN207612059 U CN 207612059U
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Abstract
The utility model provides a kind of chip interface circuit,Including signal transmitting and receiving module,Identification module,Voltage protection module,Carrying out surge protection module and switch module,The data transmit-receive pin of signal transmitting and receiving module and chip is electrically connected,The data transmission pin of identification module and chip is electrically connected,One end of voltage protection module and the output end of power supply are electrically connected,The voltage input pin of the other end and chip is electrically connected,Carrying out surge protection module is electrically connected with identification module,Switch module is electrically connected with carrying out surge protection module,The design that the utility model passes through identification module,Improve the identified ability of data transmission pin,And by the pull-up level of generation and drop-down level the circuit structure of chip interface circuit is more stablized,Improve the protective value of chip interface circuit,Pass through the design of voltage protection module,Prevent that the voltage fluctuation sent due to power supply is larger or input voltage it is excessive caused by the chip damage so that improve the protective value of chip interface circuit.
Description
Technical field
The utility model is related to electronic circuit technology field, more particularly to a kind of chip interface circuit.
Background technology
People's living standards continue to improve with the development of the times, also more and more frequently, chip refers to for the use of chip
The silicon chip of integrated circuit is included, volume very little, often a part for computer or other electronic equipments, chip are also referred to as micro-
The type of circuit, microchip and integrated circuit, chip is very extensive, and function is also various, such as has responsible supply voltage
Output control, there is responsible audio frequency and video processing, is also responsible for the chip of the functions such as complex calculation processing, in the use of chip
In the process, it needs by chip interface circuit chip to be electrically connected with other electronic devices or equipment, it is each to obtain executing
The effect of kind function.
It is relatively low to the protective value of chip during existing chip interface circuit use, between power supply and chip often
Cause chip impaired since voltage fluctuation is larger, and then the service life of chip is caused to reduce, in existing chip interface circuit
Over-pressed voltage cannot be timely eliminated when surge phenomenon occurs, and then is easy to cause the damage of chip.
Utility model content
Based on this, the purpose of this utility model is to provide a kind of chip interface electricity that can be effectively protected to chip
Road.
A kind of chip interface circuit is set between power supply and chip, including：
Signal transmitting and receiving module, the signal transmitting and receiving module and the data transmit-receive pin of the chip are electrically connected, the letter
Number transceiver module is used to send and receive the data of the chip；
The data transmission pin of identification module, the identification module and the chip is electrically connected, and the identification module is used
In when the signal for receiving the chip when, a level margin is generated on the data transmission pin；
Voltage protection module, one end of the voltage protection module and the output end of the power supply are electrically connected, the other end
It is electrically connected with the voltage input pin of the chip, the voltage protection module is defeated to the chip for filtering the power supply
The Kopin voltage sent；
Carrying out surge protection module, the carrying out surge protection module are electrically connected with the identification module, the carrying out surge protection module
For when surge phenomenon occurs on the chip interface circuit, absorbing the over-pressed voltage on the chip interface circuit；
Switch module, the switch module are electrically connected with the carrying out surge protection module, and the switch module is for controlling
The on off state of the chip interface circuit.
Said chip interface circuit, by the design of the signal transmitting and receiving module, to have ensured that the chip and outside are set
Data between standby send and receive, by the design of the identification module, when the data transmission on the chip is drawn
A pull-up level and a drop-down level are generated when foot carries out the transmission of data, inside the identification module and one positive one is negative, due to
It is equipped with testing mechanism (being used for detection data) in the chip, therefore pulls up and generates a level difference between level and drop-down level
Degree, and then the identified ability of the data transmission pin is improved, enhance load driving capability, and the pull-up for passing through generation
Level and drop-down level make the circuit structure of the chip interface circuit more stablize, and improve the chip interface circuit pair
The protective value of the chip passes through the design of the voltage protection module, it is therefore prevented that the voltage wave sent due to the power supply
The damage of the excessive caused chip of larger or input voltage is moved, and then improves the chip interface circuit to the chip
Protective value, can all generate electrostatic at work due to working as electronic component, pass through the surge in the utility model
The design of protection module, to prevent the damage due to surge phenomenon to the chip and other electronic components, and then further
Protective value of the chip interface circuit to the chip is improved, by the design of the switch module, so that effectively
Control the working condition of the chip interface circuit.
Further, the signal transmitting and receiving module include the first resistor being electrically connected with the R pins of the chip and with
The concatenated reception data port of first resistor, respectively with the RE pins of the chip be electrically connected communications protocol port and
3rd resistor, the second resistance being electrically connected with the D pins of the chip and with the concatenated transmission data end of the second resistance
Mouthful；
By the design for receiving data port and the transmission data port, to have ensured that the data of the chip are received
Function is sent out, and passes through the design of the first resistor and the 3rd resistor, the respectively described reception data port and the hair
It send data port to provide stable operating voltage, ensure that the normal work of the signal transmitting and receiving module.
Further, the identification module include respectively the VDD pins with the chip and A pins be electrically connected the 8th
The 4th resistance and be electrically connected respectively with the B pins and the A pins that the B pins of resistance and the chip are electrically connected
The 5th resistance, the output end of the 4th resistance is connected to the ground；
By the design of the 8th resistance and the 4th resistance, so as to generate a pull-up electricity in the identification module
A gentle drop-down level and one positive one negative, improves the identified ability of the data transmission pin, enhances load driving energy
Power, and by the pull-up level of generation and drop-down level the circuit structure of the chip interface circuit is more stablized.
Further, the voltage protection module include the magnetic bead being electrically connected with the system power port of the power supply and
Respectively with concatenated first capacitance of the magnetic bead and the second capacitance, output end and the ground of first capacitance and second capacitance
It is connected, the magnetic bead is electrically connected with the VDD pins and the 8th resistance respectively；
By the design of the magnetic bead, the high-frequency signal between the power supply and the chip is effectively inhibited, and drop
High-frequency noise and the spike interference generated in low voltage transmission process, and then the chip interface circuit is improved to the core
The protective value of piece, by the design of first capacitance and second capacitance, so that effectively to the power supply to described
The signal that chip is sent is filtered.
Further, the carrying out surge protection module includes and the 6th resistance of the B pin serial connections and the A pins string
7th resistance of connection, the first bi-directional voltage stabilizing diode for being connected between the B pins and the 6th resistance and it is connected on institute
State the second bi-directional voltage stabilizing diode between A pins and the 7th resistance；
By the design of the first bi-directional voltage stabilizing diode and the second bi-directional voltage stabilizing diode, so as to work as the knowledge
Between other module and the switch module when middle generation surge phenomenon, quickly to the identification module and the switch module it
Between over-pressed voltage absorbed, and then prevent surge phenomenon to the damage of the chip, improve the chip interface electricity
Protective value of the road to the chip.
Further, the resistance value of the 6th resistance and the 7th resistance is 75 ohm.
Further, the switch module includes the be electrically connected respectively with the 6th resistance and the 7th resistance
One socket and the second socket, the lightning-protection module being electrically connected respectively with first socket and second socket；
By the design of the lightning-protection module, to the damage of the chip interface circuit phenomena such as to prevent electrostatic or lightning stroke
It is bad, and then improve the service life of the chip.
Further, the lightning-protection module includes electric with the second interface of first socket and second socket respectively
Property connection first gas discharge tube, be electrically connected respectively with the first interface of first socket and second socket the
The third gas that two gas-discharge tubes and series connection are set between the first gas discharge tube and the second gas discharge tube is put
Fulgurite；
By the design of the first gas discharge tube, the second gas discharge tube and the third gas discharge tube,
So that caused by thunder-strike phenomenon or electrostatic occurs when over-pressed phenomenon, the rising of the voltage value of the effective over-pressed voltage of control, into
And overvoltage protection is carried out to other electronics member devices on the chip and the chip interface circuit.
Further, the first gas discharge tube, the second gas discharge tube and the third gas discharge tube are equal
Using two-stage discharge pipe.
Further, concatenated third bi-directional voltage stabilizing diode is equipped between the first resistor and the R pins, it is described
Concatenated 4th bi-directional voltage stabilizing diode is equipped between second resistance and the D pins；
By the design of the third bi-directional voltage stabilizing diode and the 4th bi-directional voltage stabilizing diode, so as to work as the letter
When surge phenomenon occurring number between transceiver module and the chip, quickly between the signal transmitting and receiving module and the chip
Over-pressed voltage absorbed, and then surge phenomenon is prevented to improve the chip interface circuit to the damage of the chip
To the protective value of the chip.
Description of the drawings
Fig. 1 is the modular structure schematic diagram for the chip interface circuit that the utility model first embodiment provides；
Fig. 2 is the electrical block diagram for the chip interface circuit that the utility model first embodiment provides；
Fig. 3 is the electrical block diagram between signal transmitting and receiving module and chip in Fig. 2；
Fig. 4 is the electrical block diagram between carrying out surge protection module and switch module in Fig. 2；
Fig. 5 is the modular structure schematic diagram for the chip interface circuit that the utility model second embodiment provides；
Essential element symbol description
Following specific implementation mode will further illustrate the utility model in conjunction with above-mentioned attached drawing.
Specific implementation mode
For the ease of more fully understanding the utility model, the utility model is carried out below in conjunction with related embodiment attached drawing
It is further explained.Give the embodiments of the present invention in attached drawing, but the utility model be not limited in it is above-mentioned preferred
Embodiment.On the contrary, purpose of providing these embodiments is in order to make the open face of the utility model more fully.
With the use of various smart machine so that the use of chip is more and more frequent, and chip passes through circuit and its
After its electronic component realizes electric connection, by sending and receiving signal so as to execute different function, but in existing chip
During use, chip interface circuit is relatively low to the protective value of chip, can not preferably be protected to chip, such as when
When phenomena such as surge, lightning stroke, overvoltage occurs, it is often easy to cause the damage of chip, thereby reduces the service life of chip, because
This utility model is by providing a kind of chip interface circuit that protective value is high, so as to improve the protection to chip, improves core
The service life of piece.
Referring to Fig. 1, the modular structure signal of the chip interface circuit 100 provided for the utility model first embodiment
Figure, the chip interface circuit 100 are set between power supply 106 and chip 101, including：
Signal transmitting and receiving module 10, the signal transmitting and receiving module 10 and the data transmit-receive pin of the chip 101 are electrically connected,
Data receiver and transmission of the signal transmitting and receiving module 10 for realizing the chip 101, the signal transmitting and receiving module 10 have
Data send and receive function, for sending data to institute when receiving the external data sent to the chip 101
Chip 101 is stated, when receiving the data that the chip 101 is sent, sends data to corresponding electronic equipment.
Identification module 20, the identification module 20 and the data transmission pin of the chip 101 are electrically connected, the identification
Module 20 be used for when the signal for receiving the chip 101 when, a level margin is generated on the data transmission pin, with
The identified ability of the chip 101 is improved, identification module 20 described in the present embodiment generates on the data transmission pin
Level quantity be two, one for positive one be negative, by the level difference of generation to improve the identified energy of the chip 101
Power, such as can be used between 485 circuits and doorway machine internal circuit, doorway machine internal circuit is facilitated to the chip
101 identification.
Voltage protection module 30, one end of the voltage protection module 30 and the output end of the power supply 106 are electrically connected,
The voltage input pin of the other end and the chip 101 is electrically connected, and the voltage protection module 30 is for filtering the power supply
106 Kopin voltages conveyed to the chip 101, so as to reduce the voltage that the power supply 106 transmits the chip 101
Fluctuation, and then improve the defencive function to the chip 101, it is therefore prevented that due to the larger caused core of input voltage fluctuation
The damage of piece 101.
Carrying out surge protection module 40, the carrying out surge protection module 40 are electrically connected with the identification module 20, and the surge is anti-
Module 40 is protected to be used to, when surge phenomenon occurs on the chip interface circuit 100, absorb on the chip interface circuit 100
Over-pressed voltage, with prevent due to over-pressed voltage it is larger caused by the chip 101 breakdown, improve to the chip 101
Protective value.
Switch module 50, the switch module 50 are electrically connected with the carrying out surge protection module 40, the switch module 50
On off state for controlling the chip interface circuit 100 improves the operating body of user so as to facilitate the operation of user
It tests.
Please see Fig. 2 to Fig. 4, the signal transmitting and receiving module 10 includes be electrically connected with the R pins of the chip 101
One resistance R1 and with the concatenated reception data port 103 of the first resistor R1, the reception data port 103 is for realizing institute
The data receiver function of signal transmitting and receiving module 10 is stated, the communications protocol end being electrically connected respectively with the RE pins of the chip 101
Mouthful 102 and 3rd resistor R3, the communications protocol port 102 for realizing the chip 101 to the protocol of external equipment,
The output end of the 3rd resistor R3 is connected to the ground, and then is prevented since electric current is excessive to the communications protocol port in circuit
102 damage, the second resistance R2 being electrically connected with the D pins of the chip 101 and with the concatenated hairs of second resistance R2
Send data port 104, the transmission data port 104 for realizing the signal transmitting and receiving module 10 data sending function.
By the design for receiving data port 103 and the transmission data port 104, to have ensured the chip
101 data transmit-receive function, and pass through the design of the first resistor R1 and the 3rd resistor R3, the respectively described reception number
Stable operating voltage is provided according to port 103 and the transmission data port 104, ensure that the signal transmitting and receiving module 10
Normal work.
The identification module 20 includes the 8th resistance being electrically connected respectively with the VDD pins of the chip 101 and A pins
R8, the 4th resistance R4 being electrically connected with the B pins of the chip 101 and electrically connect with the B pins and the A pins respectively
The output end of the 5th resistance R5 connect, the 4th resistance R4 are connected to the ground, and pass through the 8th resistance R8 and the 4th electricity
The design of R4 is hindered, so that generation one pulls up level and a drop-down level in the identification module 20 and one positive one is negative, is improved
The identified ability of the data transmission pin enhances load driving capability, and passes through the pull-up level of generation and drop-down electricity
It is flat that the circuit structure of the chip interface circuit 100 is more stablized.
The voltage protection module 30 includes the magnetic bead FB being electrically connected with the system power port of the power supply 106 105
Respectively with the concatenated first capacitance C1 of the magnetic bead FB and the second capacitance C2, the first capacitance C1 and the second capacitance C2
Output end be connected to the ground, the magnetic bead FB is electrically connected with the VDD pins and the 8th resistance R8 respectively, by described
The design of magnetic bead FB effectively inhibits the high-frequency signal between the power supply 106 and the chip 101, and reduces voltage
High-frequency noise and the spike interference generated in transmission process, and then the chip interface circuit 100 is improved to the chip 101
Protective value, by the design of the first capacitance C1 and the second capacitance C2 so that effectively to the power supply 106 to
The signal that the chip 101 is sent is filtered.
The carrying out surge protection module 40 includes the with the 6th resistance R6 of the B pin serial connections, with the A pin serial connections
It seven resistance R7, the first bi-directional voltage stabilizing diode ESD1 being connected between the B pins and the 6th resistance R6 and is connected on
The second bi-directional voltage stabilizing diode ESD2 between the A pins and the 7th resistance R7, passes through first bi-directional voltage stabilizing two
The design of pole pipe ESD1 and the second bi-directional voltage stabilizing diode ESD2, so that when the identification module 20 and the switching molding
Between block 50 when middle generation surge phenomenon, the quick over-pressed voltage between the identification module 20 and the switch module 50
It is absorbed, and then prevents surge phenomenon to the damage of the chip 101, improve the chip interface circuit 100 to institute
State the protective value of chip 101.
Preferably, the resistance value of the 6th resistance R6 described in the present embodiment and the 7th resistance R7 is 75 ohm, in turn
More than the resistance value (bulky encapsulation is more than 0.25 watt) of 0805 encapsulation, and then further improve the carrying out surge protection module
40 protective value, the switch module 50 include being electrically connected respectively with the 6th resistance R6 and the 7th resistance R7
First socket J1 and the second socket J2, the lightning protection mould being electrically connected respectively with the first socket J1 and the second socket J2
Block.
By the design of the lightning-protection module, to the chip interface circuit 100 phenomena such as to prevent electrostatic or lightning stroke
Damage, and then improves the service life of the chip 101, the lightning-protection module include respectively with the first socket J1 and institute
State first gas discharge tube T1 that the second interface of the second socket J2 is electrically connected, respectively with the first socket J1 and described the
The second gas discharge tube T2 and series connection that the first interface of two socket J2 is electrically connected be set to the first gas discharge tube T1 and
Third gas discharge tube T3 between the second gas discharge tube T2, the first gas discharge tube T1, the second gas
Discharge tube T2 and the third gas discharge tube T3 are all made of two-stage discharge pipe, thereby reduce the chip interface circuit 100
Production cost and improve the stability of the chip interface circuit 100
Pass through the first gas discharge tube T1, the second gas discharge tube T2 and the third gas discharge tube T3
Design, so that caused by thunder-strike phenomenon or electrostatic occurs when over-pressed phenomenon, effectively the voltage value of the over-pressed voltage of control is upper
It rises, and then overvoltage protection is carried out to other electronics member devices on the chip 101 and the chip interface circuit 100, it is preferred that
The T1 of first gas discharge tube described in the present embodiment, the second gas discharge tube T2 and the third gas discharge tube T3 are adopted
With the discharge tube of model UN1812-90CSMD.
The present embodiment by the design of the signal transmitting and receiving module 10, with ensured the chip 101 and external equipment it
Between data send and receive, by the design of the identification module 20, when the data transmission on the chip 101
When pin carries out the transmission of data, 20 inside of the identification module generates a pull-up level and a drop-down level and one positive one is negative,
Due to being equipped with testing mechanism (being used for detection data) in the chip 101, pulls up and generate one between level and drop-down level
Level margin, and then the identified ability of the data transmission pin is improved, load driving capability is enhanced, and pass through generation
Pull-up level and drop-down level the circuit structure of the chip interface circuit 100 is more stablized, improve the chip
Interface circuit 100 passes through the design of the voltage protection module 30 to the protective value of the chip 101, it is therefore prevented that by institute
State the transmission of power supply 106 voltage fluctuation is larger or input voltage it is excessive caused by the chip 101 damage, and then improve institute
Protective value of the chip interface circuit 100 to the chip 101 is stated, can all be generated due to working as electronic component at work quiet
Electricity, therefore by the design of the carrying out surge protection module 40 in the utility model, to prevent since surge phenomenon is to the chip
101 and other electronic components damage, and then further improve the chip interface circuit 100 to the chip 101
Protective value, by the design of the switch module 50, so as to effectively control the work shape of the chip interface circuit 100
State improves the operating experience of user.
Referring to Fig. 5, the structural schematic diagram of the chip interface circuit 100 provided for the utility model second embodiment, it should
The structure of second embodiment and first embodiment is more or less the same, and difference lies in first resistor R1 described in the present embodiment and institutes
It states and is equipped with concatenated third bi-directional voltage stabilizing diode ESD3 between R pins, be equipped between the second resistance R2 and the D pins
Concatenated 4th bi-directional voltage stabilizing diode ESD4, the third bi-directional voltage stabilizing diode ESD3 and the 4th zener diode
The output end of ESD4 is connected to the ground, and third bi-directional voltage stabilizing diode ESD3 described in preferred the present embodiment and the described 4th is surely
Pressure diode ESD4 is using the TPS pipes for being DO214AA models.
Pass through the third bi-directional voltage stabilizing diode ESD3 and the 4th bi-directional voltage stabilizing diode ESD4 in the present embodiment
Design so that when between the signal transmitting and receiving module 10 and the chip 101 occur surge phenomenon when, quickly to the letter
Over-pressed voltage number between transceiver module 10 and the chip 101 is absorbed, and then prevents surge phenomenon to the chip
101 damage improves protective value of the chip interface circuit 100 to the chip 101.
Above embodiment described the technical principle of the utility model, these descriptions are intended merely to explain the utility model
Principle, and it cannot be construed to the limitation of scope of protection of the utility model in any way.Based on the explanation herein, the skill of this field
Art personnel would not require any inventive effort other specific implementation modes that can associate the utility model, these modes are all
It will fall into the scope of protection of the utility model.
Claims (10)
1. a kind of chip interface circuit is set between power supply and chip, which is characterized in that including：
Signal transmitting and receiving module, the signal transmitting and receiving module and the data transmit-receive pin of the chip are electrically connected, and the signal is received
Hair module is used to send and receive the data of the chip；
The data transmission pin of identification module, the identification module and the chip is electrically connected, and the identification module is for working as
When receiving the signal of the chip, a level margin is generated on the data transmission pin；
Voltage protection module, one end of the voltage protection module and the output end of the power supply are electrically connected, the other end and institute
The voltage input pin for stating chip is electrically connected, and the voltage protection module is for filtering what the power supply was conveyed to the chip
Kopin voltage；
Carrying out surge protection module, the carrying out surge protection module are electrically connected with the identification module, and the carrying out surge protection module is used for
When surge phenomenon occurs on the chip interface circuit, the over-pressed voltage on the chip interface circuit is absorbed；
Switch module, the switch module are electrically connected with the carrying out surge protection module, and the switch module is described for controlling
The on off state of chip interface circuit.
2. chip interface circuit according to claim 1, which is characterized in that the signal transmitting and receiving module includes and the core
First resistor that the R pins of piece are electrically connected and with the concatenated reception data port of the first resistor, respectively with the chip
The communications protocol port that is electrically connected of RE pins and 3rd resistor, the second resistance being electrically connected with the D pins of the chip
With with the concatenated transmission data port of the second resistance.
3. chip interface circuit according to claim 1, which is characterized in that the identification module include respectively with the core
The 4th resistance and divide that the B pins of the 8th resistance and the chip that the VDD pins and A pins of piece are electrically connected are electrically connected
The 5th resistance not being electrically connected with the B pins and the A pins, the output end of the 4th resistance are connected to the ground.
4. chip interface circuit according to claim 3, which is characterized in that the voltage protection module includes and the electricity
Magnetic bead that the system power port in source is electrically connected and respectively with concatenated first capacitance of the magnetic bead and the second capacitance, described the
The output end of one capacitance and second capacitance is connected to the ground, the magnetic bead respectively with the VDD pins and the 8th resistance
It is electrically connected.
5. chip interface circuit according to claim 3, which is characterized in that the carrying out surge protection module includes and the B
6th resistance of pin serial connection, with the 7th resistance of the A pin serial connections, be connected on the B pins and the 6th resistance it
Between the first bi-directional voltage stabilizing diode and two pole of the second bi-directional voltage stabilizing that is connected between the A pins and the 7th resistance
Pipe.
6. chip interface circuit according to claim 5, which is characterized in that the 6th resistance and the 7th resistance
Resistance value is 75 ohm.
7. chip interface circuit according to claim 5, which is characterized in that the switch module includes respectively with described the
The first socket and the second socket that six resistance and the 7th resistance are electrically connected, respectively with first socket and described second
The lightning-protection module that socket is electrically connected.
8. chip interface circuit according to claim 7, which is characterized in that the lightning-protection module includes respectively with described the
The second interface of one socket and second socket be electrically connected first gas discharge tube, respectively with first socket and institute
The second gas discharge tube and series connection for stating the first interface electric connection of the second socket are set to the first gas discharge tube and institute
State the third gas discharge tube between second gas discharge tube.
9. chip interface circuit according to claim 8, which is characterized in that the first gas discharge tube, described second
Gas-discharge tube and the third gas discharge tube are all made of two-stage discharge pipe.
10. chip interface circuit according to claim 2, which is characterized in that between the first resistor and the R pins
It is two-way steady that the concatenated 4th is equipped with equipped with concatenated third bi-directional voltage stabilizing diode, between the second resistance and the D pins
Press diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721287279.1U CN207612059U (en) | 2017-09-30 | 2017-09-30 | Chip interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721287279.1U CN207612059U (en) | 2017-09-30 | 2017-09-30 | Chip interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207612059U true CN207612059U (en) | 2018-07-13 |
Family
ID=62793115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721287279.1U Active CN207612059U (en) | 2017-09-30 | 2017-09-30 | Chip interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207612059U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634510A (en) * | 2017-09-30 | 2018-01-26 | 深圳市艾特智能科技有限公司 | Chip interface circuit |
-
2017
- 2017-09-30 CN CN201721287279.1U patent/CN207612059U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634510A (en) * | 2017-09-30 | 2018-01-26 | 深圳市艾特智能科技有限公司 | Chip interface circuit |
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