CN212256306U - Bottom plate for embedded development board and embedded development board - Google Patents

Abstract

The application provides a bottom plate for an embedded development board and the embedded development board. The bottom plate includes: a first set of core board interfaces; a second set of core board interfaces at least partially overlapping the first set of core board interfaces; and the peripheral module is arranged around the first group of core board interfaces and/or the second group of core board interfaces and connected with the first group of core board interfaces and the second group of core board interfaces. The bottom plate that this application provided includes two sets of nuclear core plate interfaces, can satisfy the great condition of IO quantity demand, also can save the cost of nuclear core plate when IO quantity demand is less.

Description

Bottom plate for embedded development board and embedded development board

Technical Field

The application relates to the field of FPGA (field programmable gate array) embedded development boards, in particular to a bottom board for an embedded development board and the embedded development board.

Background

The Field Programmable Gate Array (FPGA) is an important tool widely used in modern communication technology, electronic technology, computer technology, and automation technology. Many embedded chips or FPGA development boards exist in the market, and are suitable for various application fields.

The traditional embedded or FPGA development board usually only uses an embedded chip or an FPGA chip of a certain specific model, and a developer often encounters the situation that the resources on the chip are insufficient and the whole development board needs to be replaced when the developer uses the board. For example, some development boards have complete peripheral functions, but often employ a specific type of chip.

SUMMERY OF THE UTILITY MODEL

The embedded development board bottom board can replace core boards with different specifications and comprises various common bus types and peripheral equipment, so that different development and learning requirements are met.

According to an aspect of the present application, there is provided a chassis for an embedded development board, including:

a first set of core board interfaces;

a second set of core board interfaces at least partially overlapping the first set of core board interfaces;

and the peripheral module is arranged around the first group of core board interfaces and/or the second group of core board interfaces and connected with the first group of core board interfaces and the second group of core board interfaces.

Further, the specification of the first set of core board interfaces comprises 120 x 2 pins; the specification of the second set of core board interfaces comprises 100 x 2 pins.

According to some embodiments of the present application, the peripheral module comprises:

and the control chip of the first peripheral module is directly connected with the first group of core board interfaces and the second group of core board interfaces.

Further, the first peripheral module includes:

the device comprises one or more of a bus transceiver module, an Ethernet module, an OLED module, a Micro SD card interface module, a USB transceiver module, an audio coding and decoding module, a FLASH module, an ADC module and a USB signal switching module.

According to some embodiments of the present application, the peripheral module further comprises:

and the second external module is directly connected with the first group of core board interfaces and the second group of core board interfaces.

Further, the second peripheral module includes:

one or more of JTAG interface module, toggle switch, touch key, user jumper, light emitting diode, general I/O and expansion interface.

According to some embodiments of the present application, the second peripheral module further comprises:

and the passive buzzer is connected with the first group of core board interfaces and the second group of core board interfaces through a jumper wire serving as a switch.

According to some embodiments of the present application, the peripheral module further comprises:

and the power supply module is connected with the first peripheral module, the second peripheral module, the first group of core board interfaces and the second group of core board interfaces to provide voltage for the first peripheral module, the second peripheral module, the first group of core board interfaces and the second group of core board interfaces.

Further, the power module includes:

a power supply voltage transformation module;

the power supply protection circuit is connected with the power supply transformation module;

and the power supply input port is connected with the power supply protection circuit.

According to some embodiments of the present application, the bottom plate comprises 4 plates, respectively:

a top layer;

the bottom layer is in signal connection with the top layer;

the power supply layer is arranged between the top layer and the bottom layer;

a formation disposed between the top layer and the bottom layer.

According to another aspect of the present application, there is provided an embedded development board, including:

a base plate as described above;

a core board connected to the first set of core board interfaces or the second set of core board interfaces of the backplane.

The development board bottom plate that this application provided provides two sets of nuclear core plate interfaces, can satisfy the great condition of IO quantity demand, also can save the cost of nuclear core plate when IO quantity demand is less. In addition, the bottom plate carries more various peripheral resources, the cost of purchasing an independent peripheral module is saved in the development process, and the development convenience degree is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present application.

Fig. 1 shows a schematic view of a backplane structure according to an exemplary embodiment of the present application.

Fig. 2 shows a schematic view of a backplane structure according to another example embodiment of the present application.

Fig. 3 shows a development board structure schematic according to an example embodiment of the present application.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

Those skilled in the art will appreciate that the drawings are merely schematic representations of exemplary embodiments, which may not be to scale. The blocks or flows in the drawings are not necessarily required to practice the present application and therefore should not be used to limit the scope of the present application.

In the design scheme of the embedded development board or the FPGA development board, only a certain type of embedded chip or FPGA chip is often used, and a developer often encounters the situation that resources on a chip are insufficient and the whole development board needs to be replaced when the developer uses the embedded development board or the FPGA chip. For example, in a design scheme of an interface-extensible FPGA development board, the development board is composed of a separable bottom board and a core board, the bottom board includes a power supply module, an active crystal oscillator, a light emitting diode, a dial switch, a key, a passive buzzer and an I/O expansion interface, the core board includes an FPGA chip, a JTAG programming download interface, a configuration memory and a dial switch, and the bottom board and the core board are interconnected through a board-to-board connector.

In one aspect, the core board in the development board design is separate from the backplane, but the specifications are fixed. On the other hand, the development board design only includes simple peripherals such as light emitting diodes, switches, buttons, buzzers, and the like. In the learning and developing process, various common peripherals such as a memory, an audio/video module and the like are often required to be purchased additionally and connected to the upper part of the I/O expansion interface through a DuPont wire for use. Even if the FPGA chip on the core board has strong functions, the bottom board is difficult to fully utilize the computing resources of the FPGA chip.

In view of the above problems, the present inventors provide a backplane for an embedded development board and an embedded development board, which include various peripherals of common bus types, and can replace core boards of different specifications, thereby meeting the requirements of more extensive development and learning.

The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic view of a backplane structure according to an exemplary embodiment of the present application.

As shown in fig. 1, according to an example embodiment of the present application, a backplane 100 for an embedded development board provided by the present application includes a first set of core board interfaces 110, a second set of core board interfaces 120, and a peripheral module 130.

The backplane 100 is generally centered on a first set of core board interfaces 110 and a second set of core board interfaces 120. The peripheral modules 130 are disposed around the first and second sets of core board interfaces in a radial manner. Each of the peripheral modules 130 is coupled to the first set of core board interfaces 110 and the second set of core board interfaces 120. The first set of core board interfaces 110 are connected to the second set of core board interfaces 120 via interconnect lines, at least partially overlapping. Thus, both sets of interfaces can access all peripheral devices on the board. When the development board is used, the core board may be connected to the backplane 100, and the core board may receive input and output of all peripheral modules on the backplane and perform operations such as control.

The first set of core board interfaces 110 and the second set of core board interfaces 120 are of different specifications. For example, the first set of core board interfaces may be 120 x 2 pins in size. The specification of the second set of core board interfaces comprises 100 x 2 pins. Both sets of interfaces can communicate to all peripheral modules on the backplane with the difference being how many of the backplane's general purpose I/O numbers can be utilized. Therefore, in the practical application process, embedded or FPGA core boards with different specifications can be connected according to the number of universal IO required in the development process, so that chips can be conveniently screened, and the development time can be saved.

The peripheral modules 130 on the base board 100 include a plurality of peripherals, specifically, a first peripheral module and a second peripheral module.

The first peripheral module is a common peripheral, and includes one or more of a bus transceiver module 11, an ethernet module 12, an OLED module 13, a Micro SD card interface module 14, a USB transceiver module 15, an audio codec module 16, a FLASH module 17, an ADC module 18, and a USB signal switching module 20. Wherein the bus transceiver module 11 may be a CAN bus receiver module. The ethernet module 12 may be an ethernet PHY module. The OLED module 13 mayIs a 128 x 64SPI OLED module. The USB transceiver module 15 may be a USB1.1 transceiver module. The audio codec module 16 may be a stereo audio digital signal codec module with speaker drivers. The FLASH module 17 may be an QSPI FLASH module. The ADC block 18 may be I²And C, an ADC module. The USB signal switching module 20 may be a USB to JTAG/UART module.

The first peripheral module is a peripheral module containing a controller chip. The controller chips of these modules are connected directly to the first set of core board interfaces 110 and the second set of core board interfaces 120 by wires. After the core board is connected, the control can be performed by the core board. The peripheral modules CAN be used as input and output of the core board and receive control of the core board, so that rich functions of CAN bus data transmission, Ethernet data transmission, USB data transmission, image/video display, audio coding and decoding, data storage and the like are realized.

The second peripheral module is a simple peripheral module, and includes a JTAG interface module 19, a toggle switch 31, a tact switch 32, a user jumper 33, a light emitting diode 34, a passive buzzer 35, a general user I/O36, an expansion interface module 37, and the like. In the peripheral module of the second peripheral module, the passive buzzer 35 is wired to the first set of core board interfaces 110 and the second set of core board interfaces 120 by a jumper as a switch. The other peripheral modules are all directly wired to the first set of core board interfaces 110 and the second set of core board interfaces 120.

After the core board is connected, the toggle switch 31, the tact switch 32 and the user jumper 33 provide input signals for the core board. The light emitting diode 34 and the passive buzzer 35 receive output signals from the core board. The general user I/O36 and the expansion interface module 37 may provide input and output signals, or may be externally connected to other hardware modules in a dupont or pin header bus manner to expand the functions of the backplane.

The USB to JTAG/UART module 20 and the JTAG interface module 19 are core board configuration modules. Both modules may be used for JTAG programming download to the core board. The USB to JTAG/UART module 20 can also provide UART signals to the core board, which can perform UART debugging through the interface module.

As shown in fig. 1, the peripheral module 130 further includes a power module 40, which is connected to the first peripheral module, the second peripheral module, the first set of core board interfaces, the second set of core board interfaces, and the like, and provides voltage for the first peripheral module, the second peripheral module, the first set of core board interfaces, the second set of core board interfaces, and the like. The power module comprises a power supply module, a protection module and a voltage transformation module. The power supply input port of the bottom plate is connected with the power supply protection circuit and then connected to the power supply transformation module to provide proper power supply voltage for each peripheral and the core board. The part of the circuit is collectively called as a power supply module.

Additionally, the backplane 100 is a 4-layer board design with top and bottom layers for signal routing. And a large number of copper wires are respectively paved on the two layers in the inner part to form a power supply layer and a ground layer. The power layer is divided and isolated according to different power voltages required by different modules. The structural design can reduce crosstalk between signals and is beneficial to heat dissipation.

Fig. 2 shows a schematic view of a backplane structure according to another example embodiment of the present application.

As shown in fig. 2, according to another embodiment of the present application, a base plate 200 of another structure is provided. The structural composition of the backplane 200 is the same as that of the backplane 100 in fig. 1, except that the arrangement directions of the first set of core interfaces 110 and the second set of core board interfaces 120 are different, and will not be described herein again.

Fig. 3 shows a schematic diagram of an embedded development board structure according to an example embodiment of the present application.

The present application also provides an embedded development board 1000. As shown in fig. 3, the embedded development board 1000 includes a core board 200 and a backplane 100 as shown in fig. 1. The core board 200 is connected to either the first set of core board interfaces 110 or the second set of core board interfaces 120 of the backplane 100.

Because the first set of core board interfaces 110 and the second set of core board interfaces 120 have different specifications, the core board specifications meeting the requirements can be selected according to actual requirements in the development and learning processes. The first set of core board interfaces 110 and the second set of core board interfaces 120 are connected to each other and are all connected to the peripheral modules, so that the core board 200 can access the abundant peripheral modules regardless of whether the core board interfaces 110 and 120 are connected to the first set of core board interfaces or the second set of core board interfaces.

The development board bottom plate that this application provided provides two sets of nuclear core plate interfaces, can satisfy the great condition of IO quantity demand, also can save the cost of nuclear core plate when IO quantity demand is less. In addition, the bottom plate carries more various peripheral resources, the cost of purchasing an independent peripheral module is saved in the development process, and the development convenience degree is improved.

It should be noted that each of the embodiments described above with reference to the drawings is only for illustrating the present application and not for limiting the scope of the present application, and those skilled in the art should understand that modifications or equivalent substitutions made on the present application without departing from the spirit and scope of the present application should be covered by the present application. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.

Claims (11)

1. A backplane for embedded development boards, comprising:

a first set of core board interfaces;

a second set of core board interfaces at least partially overlapping the first set of core board interfaces;

and the peripheral module is arranged around the first group of core board interfaces and/or the second group of core board interfaces and connected with the first group of core board interfaces and the second group of core board interfaces.

2. The backplane according to claim 1,

the specification of the first set of core board interfaces comprises 120 x 2 pins;

the specification of the second set of core board interfaces comprises 100 x 2 pins.

3. The backplane of claim 1, wherein the peripheral module comprises:

and the control chip of the first peripheral module is directly connected with the first group of core board interfaces and the second group of core board interfaces.

4. The backplane of claim 3, wherein the first peripheral module comprises:

the device comprises one or more of a bus transceiver module, an Ethernet module, an OLED module, a Micro SD card interface module, a USB transceiver module, an audio coding and decoding module, a FLASH module, an ADC module and a USB signal switching module.

5. The backplane of claim 3, wherein the peripheral module further comprises:

and the second external module is directly connected with the first group of core board interfaces and the second group of core board interfaces.

6. The backplane of claim 5, wherein the second peripheral module comprises:

one or more of JTAG interface module, toggle switch, touch key, user jumper, light emitting diode, general I/O and expansion interface.

7. The backplane of claim 6, wherein the second peripheral module further comprises:

and the passive buzzer is connected with the first group of core board interfaces and the second group of core board interfaces through a jumper wire serving as a switch.

8. The backplane according to any of claims 3-7, wherein the peripheral module further comprises:

and the power supply module is connected with the first peripheral module, the second peripheral module, the first group of core board interfaces and the second group of core board interfaces to provide voltage for the first peripheral module, the second peripheral module, the first group of core board interfaces and the second group of core board interfaces.

9. The backplane of claim 8, wherein the power module comprises:

a power supply voltage transformation module;

the power supply protection circuit is connected with the power supply transformation module;

and the power supply input port is connected with the power supply protection circuit.

10. A backplane according to claim 1, characterized in that the backplane comprises 4 layers, respectively:

a top layer;

the bottom layer is in signal connection with the top layer;

the power supply layer is arranged between the top layer and the bottom layer;

a formation disposed between the top layer and the bottom layer.

11. An embedded development board, comprising:

the base plate of any one of claims 1-10;

a core board connected to the first set of core board interfaces or the second set of core board interfaces of the backplane.

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