CN114722754A

CN114722754A - FPGA prototype verification equipment

Info

Publication number: CN114722754A
Application number: CN202210275164.XA
Authority: CN
Inventors: 刘兴茂; 刘丹; 暴宇; 马婧; 李俊华; 张佩文; 徐国超
Original assignee: Jiangsu Tanggu Intelligent Technology Co ltd; Beijing Tanggu Software Technology Co ltd
Current assignee: Jiangsu Tanggu Intelligent Technology Co ltd; Beijing Tanggu Software Technology Co ltd
Priority date: 2022-03-19
Filing date: 2022-03-19
Publication date: 2022-07-08

Abstract

Provided is FPGA prototype verification equipment. The invention discloses FPGA prototype verification equipment, which comprises the following modules: the system comprises a main control card, a service card and a case; the master control card is used for processing and controlling FPGA prototype verification; the business card comprises an FPGA chip and is used for executing prototype verification; the master control card is connected with the business card in a pluggable mode; the business card is connected with the business card in a pluggable mode. According to the FPGA prototype verification device provided by the invention, the main control card and the business cards are connected in a pluggable manner, the business cards are also connected in a pluggable manner, the modularized and open extensible framework of the FPGA prototype verification device is realized, the flexible connection between the main control card and the business cards can be realized in a pluggable manner according to needs, the business cards are flexibly extended, and the FPGA prototype verification device is quickly built according to different needs, so that the device which is easy to flexibly extend the number of FPGA chips required by prototype verification is realized, the cost is saved, and the flexibility is increased.

Description

FPGA prototype verification device

Technical Field

The invention relates to the technical field of FPGA prototype verification, in particular to FPGA prototype verification equipment.

Background

With the increasing performance and complexity of the current chip, various defects which do not appear before present new challenges for the traditional test method, and it is imperative to develop a serialized test verification device suitable for chip development, integrating and classifying the requirements of multiple IC-type projects on the verification device, and the same series can be applied in multiple similar projects, thereby avoiding resource waste and progress delay caused by independently developing the verification device for each project; the test verification device has strong expandability and universality, can be quickly built according to different project requirements, is compatible with a plurality of projects, and is a trend of the development of prototype verification technology of Programmable logic devices (such as Field-Programmable Gate Array (FPGA) devices).

The FPGA prototype verification equipment provided by the prior art is fixedly connected with the FPGA, and when the number of FPGA chips required by prototype verification is insufficient, the traditional FPGA prototype verification equipment cannot easily and flexibly expand the number of the FPGA chips required by prototype verification. In addition, the traditional FPGA prototype verification device only has one main control card, and only can use a fixed number of FPGA chips for one user, so that the verification resource utilization rate is low, the waste is large, and the cost is high.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defect that the traditional FPGA prototype verification apparatus in the prior art is not easy to flexibly expand the number of FPGA chips required for prototype verification, so as to provide an FPGA prototype verification apparatus, including: the system comprises a main control card, a service card and a chassis; the master control card is used for processing and controlling FPGA prototype verification; the business card comprises an FPGA chip and is used for executing prototype verification; the main control card is connected with the business card in a pluggable mode; the business cards are connected in a pluggable mode; the main control card and the service card are detachably connected to the chassis.

Furthermore, the main control card comprises a main control chip, a memory, a clock generation area, a first clock output interface and a first debugging interface;

the business card comprises two FPGA chips, a second CPLD chip, a JTAG, a plurality of second input and output interfaces, a first clock input interface and a second debugging interface;

the first clock output interface is connected with the first clock input interface; the second input/output interface connection is connected with the second input/output interfaces on other service cards to realize interconnection or cascade of a plurality of FPGA chips; the first debugging interface is connected with the second debugging interface; the second CPLD chip is used for configuring the second input/output interface and the clock input interface on the service card; the two FPGA chips can be identified through the JTAG; the clock signal generated by the clock generation area is connected to the first clock input interface through the first clock output interface.

Furthermore, the main control chip calls the memory data, and the data are configured for the FPGA chip through the second CPLD chip.

Furthermore, through the scanning identification of the JTAG, the main control chip can selectively configure or upgrade two FPGA chips.

Further, the clock generation area comprises a crystal oscillator, a first CPLD chip and a PLL chip; the first CPLD chip configures the first clock output interface; and the crystal oscillator is matched with the PLL chip to generate a clock signal which is output from the first clock output interface.

Furthermore, the number of the master control cards is N, and the number of the service cards is M.

Furthermore, the master control card further comprises a second clock input interface which can be connected with the first clock output interfaces of other master control cards and receive synchronous clock information.

Furthermore, one master control card can control 1-M service cards simultaneously.

Further, the number of N is 1-4, the number of M is 1-4, and M is larger than or equal to N.

Further, the master control card may control 2 or more service cards in the FPGA prototype verification device.

Furthermore, the PCB of the component is characterized in that power sockets are correspondingly and respectively arranged on the upper surface and the lower surface of the PCB of the component so as to be connected with a power supply.

The technical scheme of the invention has the following beneficial effects: according to the FPGA prototype verification device provided by the invention, the main control card and the business card are connected in a pluggable manner, the modular and open extensible framework of the FPGA prototype verification device is realized, the flexible connection between the main control card and the business card and between the business card and the business card can be realized in a pluggable manner according to needs, and the FPGA prototype verification device is quickly built according to different needs, so that a device which is easy to flexibly expand the number of FPGA chips required by prototype verification is realized, the cost is saved, and the flexibility is increased.

The technical scheme of the invention has the following advantages:

1. the FPGA prototype verification equipment provided by the invention adopts pluggable connection between the service cards, realizes the modularized and open extensible framework of the FPGA prototype verification equipment, and can realize flexible connection between the master control card and the service cards and between the service cards according to the pluggable connection.

2. The FPGA prototype verification equipment provided by the invention can be provided with at least one master control card, and the master control card can control a single service card or a plurality of service cards according to the needs of customers, namely, the master control card can support 1 user to use and at least more than 2 users to use simultaneously, and is completely independent and not influenced mutually, so that the concurrent use of multiple users can be realized, and the use efficiency of system resources is optimized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of the FPGA prototype verification device connection of the present application;

FIG. 2 is a schematic diagram of a master control card layout of the present application;

FIG. 3 is a schematic diagram of a service card layout of the present application;

FIG. 4 is a schematic diagram of a control relationship between a master control card and a service card according to the present application;

fig. 5 is a schematic connection diagram of two master control card control service cards of the FPGA prototype verification device of the present application;

fig. 6 is a schematic diagram of a physical connection of the FPGA prototype verification apparatus of the present application.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Examples

Referring to fig. 1, the FPGA prototype verification apparatus according to the present invention includes: a main control card 001, a service card 002 and a case 007; the main control card 001 is used for processing and controlling FPGA prototype verification; the service card 002 includes an FPGA chip for performing prototype verification; the main control card 001 and the service card 002 are connected in a pluggable manner; the business cards 002 are connected in a pluggable manner, the main control card 001 and the business cards 002 are detachably connected to the case 007, in this embodiment, the main control card and the business cards can be specifically connected with each other through a connecting wire 003, for example, through a flat cable, as shown in fig. 6.

According to the FPGA prototype verification device, the business cards 002 are connected in a pluggable mode, specifically can be connected through the connecting wires 003, and can be connected through the flat cables, so that a modularized and open extensible framework of the FPGA prototype verification device is achieved, the main control card 001, the business cards 002 and the business cards 002 can be flexibly connected through the connecting wires as required, the main control card 001 can be conveniently added, one user correspondingly uses one main control card 001, 2 or more users can concurrently use the FPGA prototype verification device, an FPGA prototype verification system can be rapidly built according to different requirements, and therefore a device capable of flexibly extending the number of FPGA chips needed by prototype verification is achieved easily, cost is saved, and flexibility is improved.

As shown in fig. 2-3, the main control card 001 includes a main control chip 101, a memory 102, a first clock input interface 103, a clock generation area 104, a first clock output interface 108, and a first debug interface 109; the service card 002 comprises an FPGA chip 201, an FPGA chip 202, a second CPLD chip 203, a JTAG 204, a plurality of second input/output interfaces 205, first clock input interfaces 2061 and 2062, and a second debug interface 208; the first clock output interface 108 is connected to the first clock input interfaces 2061 and 2062; the second input/output interface 205 is connected with the second input/output interface 205 on the other service card 002 to realize interconnection or cascade of a plurality of FPGA chips; the first debug interface 109 is connected with the second debug interface 208; the second CPLD chip 203 is used to configure the second input/output interface 205 and the first clock input interface 2061, 2062 on the service card 002; two

FPGA chips

201 and 202 can be identified through the JTAG 204; the clock signal generated by the clock generation region 104 is coupled to the first clock input interfaces 2061 and 2062 through the first clock output interface 103. The second input/output interface 205 may adopt an FMC interface, and multiple FPGA chips are interconnected or cascaded through a standard connection line at the FMC interface. In addition, the FMC interface which is not interconnected can be used for connecting verification of other peripheral daughter cards, such as connection of PCIE and/or verification of 10G optical interface daughter cards.

The main control chip 101 shown in FIG. 2 can use Xilinx system-on-chip ZYNQ (ZYNQ-7000All Programmable Soc).

The

FPGA chips

201 and 202 shown in fig. 3 can provide two types of selected FPGA chips, VU440 chips and VU19P chips, where the FPGA chips have a size of Xilinx, the VU440 chips adopt a 7nm technology and have 2500 ten thousand equivalent logic gates, and can complete design verification of about 2500 ten thousand ASIC gates, each expansion of one-stage verification device resources is doubled, the VU19P chips adopt a 7nm technology and have 5000 ten thousand equivalent logic gates, and can complete design verification of about 5000 ten thousand ASIC gates, each expansion of one-stage verification device resources is doubled, 2 VU19P chips can complete design verification of about 1 ASIC gate for 1 service card 001, and 8 VU19P chips can complete design verification of about 4 hundred million ASIC gates for 4 service cards 001.

As shown in fig. 4, the main control chip 101 on the main control card 001 calls the data of the memory 102, and configures data for the FPGA chip 201 and the FPGA chip 202 through the second CPLD chip 203.

As shown in fig. 4, through the scanning and identification of the JTAG 204, the main control chip 101 can selectively configure or upgrade the FPGA chip 201 and the FPGA chip 202, that is, the FPGA chip 201 can be configured or upgraded separately, the FPGA chip 202 can be configured or upgraded separately, or the FPGA chip 201 and the FPGA chip 202 can be configured or upgraded simultaneously.

The clock generation area 104 comprises a crystal oscillator 106, a first CPLD chip 105, a PLL chip 107; the first CPLD chip 105 configures the first clock output interface 108; the crystal oscillator 106 generates a clock signal in cooperation with the PLL chip 108, and outputs the clock signal from the first clock output interface 108.

The main control card 001 and the service card 002 are powered by the connectors between the boards.

The number of the main control cards 001 is N, and the number of the service cards 002 is M. One master control card 001 may control 1 to M service cards 002 at the same time. As shown in fig. 5, 2 main control chips may control 3 service cards with one main control chip and 1 service card with another main control chip.

N is 1-4, M is 1-4, and M is more than or equal to N. If 4 main control chip 001, when single user uses, can 1 ~ 4 business card 002 of arbitrary one main control chip 001 control, when 2 at least users use, a main control chip 001 corresponds a user and uses, can control at least one business card 002 respectively, realizes nimble collocation and uses. In addition, the main control chip 001 is not limited to control the service card 002 of the FPGA prototype verification device, and may also control the service cards 002 in other cases of the FPGA prototype verification device, that is, the main control chip may control 2 or more service cards in the FPGA prototype verification device, so as to implement large-scale ASIC gate verification.

The FPGA prototype verification apparatus provided in this embodiment may be provided with a plurality of master control cards, one master control card is provided for one user to use, and the master control card may control a single service card or a plurality of service cards according to a customer requirement, support 1-4 users to use simultaneously, and completely independent and do not affect each other, thereby realizing concurrent use of multiple users, and optimizing the use efficiency of system resources.

The upper and lower surfaces of the PCB board of the main control card 001 are respectively provided with a first power socket 110 for connecting a power supply, and the upper and lower surfaces of the PCB board of the service card 002 are respectively provided with a second power socket 207 for connecting a power supply.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims

1. An FPGA prototype validation apparatus, comprising: the system comprises a main control card, a service card and a chassis; wherein, the first and the second end of the pipe are connected with each other,

the main control card is used for processing and controlling the FPGA prototype verification;

the business card comprises an FPGA chip and is used for executing prototype verification;

the main control card is connected with the business card in a pluggable mode; the business cards are connected in a pluggable mode; the main control card and the service card are detachably connected to the chassis.

2. The FPGA prototype verification apparatus of claim 1, wherein said master card comprises a master chip, a memory, a clock generation area, a first clock output interface, a first debug interface;

the first clock output interface is connected with the first clock input interface; the second input/output interface connection is connected with the second input/output interfaces on other service cards to realize interconnection or cascade of a plurality of FPGA chips; the first debugging interface is connected with the second debugging interface; the second CPLD chip is used for configuring the second input/output interface and the clock input interface on the service card; the two FPGA chips can be identified through the JTAG; the clock signal generated by the clock generation area is accessed to the first clock input interface through the first clock output interface.

3. The FPGA prototype verification device of claim 2, wherein said master control chip invokes said memory data to configure data for said FPGA chip via said second CPLD chip.

4. The FPGA prototype verification device of claim 2, wherein said master control chip selectively configures or upgrades both of said FPGA chips through JTAG scan recognition.

5. The FPGA proto-verification device of claim 2, wherein the clock generation region comprises a crystal oscillator, a first CPLD chip, a PLL chip; the first CPLD chip configures the first clock output interface; and the crystal oscillator is matched with the PLL chip to generate a clock signal which is output from the first clock output interface.

6. The FPGA prototype verification apparatus of claim 2, wherein there are N master cards and M service cards.

7. The FPGA prototype verification device according to claim 6, wherein one master card can control 1-M of the service cards simultaneously.

8. The FPGA prototype verification apparatus according to claim 6, wherein N is 1-4 and M is 1-4.

9. The FPGA prototype verification apparatus of any of claims 1 to 8, wherein power sockets are correspondingly disposed on the upper and lower surfaces of the PCB of the main control card and the service card, respectively, for connecting to a power supply.