CN212208083U - Startup forbidding circuit and notebook computer device - Google Patents
Startup forbidding circuit and notebook computer device Download PDFInfo
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- CN212208083U CN212208083U CN202020855730.0U CN202020855730U CN212208083U CN 212208083 U CN212208083 U CN 212208083U CN 202020855730 U CN202020855730 U CN 202020855730U CN 212208083 U CN212208083 U CN 212208083U
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Abstract
The application relates to a startup forbidding circuit and a notebook computer device, wherein the startup forbidding circuit comprises: the notebook computer comprises a starting signal output module, a system power supply module, a buffer module, a Hall sensor, a low-level output prevention module and an integrated power supply management circuit, wherein after the notebook computer is closed, the low-level output prevention module does not output a signal for starting the notebook computer, the Hall sensor outputs a low-level signal for preventing the low-level output prevention module from outputting the low-level signal to a control signal input end of the low-level output prevention module, so that the integrated power supply management circuit cannot work and cannot control the starting of the notebook computer, and the problem that the temperature of a mainboard of the notebook computer is too high and important data is lost due to the fact that the notebook computer is always in a starting state due to mistaken pressing of a power-on key in an environment with poor heat dissipation performance of the notebook computer is effectively solved.
Description
Technical Field
The present disclosure relates to electronic circuits, and particularly to a power-on prohibition circuit and a notebook computer device.
Background
After the notebook computer is used, a user usually closes the computer and puts the computer into a computer bag for carrying. However, in this process, the user often mistakenly presses the power-on key, so that the notebook computer is still in a power-on state after the cover is closed, and the notebook computer is in a closed environment with poor heat dissipation performance for a long time.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a power-on disable circuit and a notebook computer device, which can effectively solve the problem that important data is lost due to an excessive temperature of a motherboard of a notebook computer caused by a mistaken pressing of a power-on key to keep the notebook computer in a power-on state in an environment with poor heat dissipation performance of the notebook computer.
Mainly comprises the following aspects:
in a first aspect, the utility model provides a power-on forbidding circuit, power-on forbidding circuit includes: the power-on signal output module comprises a power-on signal output module, a system power supply module, a buffer module, a Hall sensor, a low-level-resistant output module and an integrated power supply management circuit, wherein the signal output end of the power-on signal output module is connected with the input end of the buffer, the power supply input end of the buffer module is connected with the power supply output end of the system power supply module, the output end of the buffer module is connected with the power-on signal input end of the low-level-resistant output module, the control signal input end of the low-level-resistant output module is connected with the output end of the Hall sensor, the output end of the low-level-resistant output module is connected with the signal input end of the integrated power supply management circuit, the power supply input end of the Hall sensor is connected with the power supply output end of the system power supply module, the grounding end of the, the startup forbidding circuit is in a startup forbidding state, so that the low-level output stopping module does not output a low-level signal for starting the notebook computer, and meanwhile, the Hall sensor outputs a low-level signal for stopping the output of the low-level output stopping module to the control signal input end of the low-level output stopping module.
In one possible implementation, the first circuit configuration of the low-level output blocking module includes: the gate of the first MOS transistor is connected to the output terminal of the hall sensor, the source of the first MOS transistor is connected to the output terminal of the buffer module, the drain of the first MOS transistor is connected to the signal input terminal of the integrated power management circuit, and the low-level output preventing module is the first circuit composition structure, the start-up prohibiting circuit further includes: the power-on signal output module comprises a capacitor, a first resistor, a second resistor, a third resistor and a diode, wherein the signal output end of the power-on signal output module is connected with the first end of the first resistor, the second end of the first resistor is connected with the power output end of the system power module, the power input end of the buffer module is connected with the first polar plate of the capacitor, the second polar plate of the capacitor is grounded, the grid electrode of the first MOS tube is connected with the first end of the second resistor, the second end of the second resistor is connected with the power output end of the system power module, the drain electrode of the first MOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the negative electrode of the diode, the positive electrode of the diode is connected with the signal input end of the integrated power management circuit, and when the grid electrode of the first MOS tube receives a low-level signal output by the Hall sensor, the first MOS tube is cut off, and when the grid electrode of the first MOS tube receives a high-level signal output by the Hall sensor, the first MOS tube is conducted.
In a possible implementation manner, the first MOS transistor is an NMOS transistor.
In a possible implementation manner, a gate of the first MOS transistor is an input terminal that controls the first MOS transistor to be in an on-off state, a source of the first MOS transistor is a power-on signal input terminal, and a drain of the first MOS transistor is a power-on signal output terminal of the first MOS transistor.
In a possible implementation manner, the second circuit composition structure of the low-level output blocking module includes: the gate of second MOS pipe and OR gate, the grid of second MOS pipe with the output of hall inductor is connected, the source electrode of second MOS pipe with the second input of OR gate is connected, the drain electrode of second MOS pipe with the body ground connection of second MOS pipe, the first input of OR gate with the output of buffer module is connected, the output of OR gate with integrated power management circuit's signal input part is connected, and the first end of fourth resistance is connected, the second end of fourth resistance with the negative pole of diode is connected, prevent low level output module for during second kind of circuit component structure, forbid start circuit still includes: the power-on signal output module comprises a capacitor, a first resistor, a second resistor, a fourth resistor and a diode, wherein the signal output end of the power-on signal output module is connected with the first end of the first resistor, the second end of the first resistor is connected with the power output end of the system power module, the power input end of the buffer module is connected with the first polar plate of the capacitor, the second polar plate of the capacitor is grounded, the grid electrode of the second MOS tube is connected with the first end of the second resistor, the grid electrode of the second MOS tube is connected with the output end of the Hall sensor, the second end of the second resistor is connected with the power output end of the system power module, the output end of the OR gate is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the negative electrode of the diode, and the positive electrode of the diode is connected with the signal input end of the integrated power management circuit, the circuit formed by the second MOS tube and the OR gate comprises a first state and a second state, wherein the first state is a state when the grid electrode of the second MOS tube receives a low level signal output by the Hall sensor, the second MOS tube is in a cut-off state when the grid electrode of the second MOS tube receives the low level signal output by the Hall sensor, the OR gate outputs a high level signal, the second state is a state when the grid electrode of the second MOS tube receives the high level signal output by the Hall sensor and the first input end of the OR gate is in a low level, the second MOS tube is in a conducting state when the grid electrode of the second MOS tube receives the high level signal output by the Hall sensor, and the OR gate outputs a low level signal.
In a possible implementation manner, the second MOS transistor is an NMOS transistor.
In a second aspect, the utility model provides a notebook computer device, notebook computer device includes magnet and foretell forbidding start circuit, notebook computer device closes the lid back, magnet with hall sensor's interval is less than after notebook computer device expandes magnet with hall sensor's interval after notebook computer device closes the lid back, hall sensor output is used for stopping the low level signal of prevention low level output module output after notebook computer device expandes, hall sensor output is used for switching on the high level signal of preventing low level output module output. In one possible embodiment, the notebook computer device includes: the power-on forbidding circuit is placed in the first shell.
In one possible embodiment, the notebook computer device includes: a second housing, the magnet being disposed within the second housing.
In one possible embodiment, the power-on key of the notebook computer device is outside the casing.
An object of the present application is to provide a power-on prohibition circuit and a notebook computer apparatus, wherein the power-on prohibition circuit includes: the system power supply module supplies power to the startup forbidding circuit, the startup signal output module generates a low-level startup signal and sends the low-level startup signal to the buffer module, the buffer module outputs a low-level startup signal after receiving the low-level startup signal and sends the output low-level startup signal to the low-level stopping output module, the low-level stopping output module receives the low-level startup signal and simultaneously receives a control signal output by the Hall sensor, the control signal output by the Hall sensor controls the low-level stopping output module to be switched on or switched off, and after the notebook computer is closed, the output end of the Hall sensor outputs the low-level signal, the control signal input end of the low-level output preventing module receives a low-level signal, the low-level output preventing module is cut off, when a power-on key is pressed down in a state that the notebook computer is closed, the power-on signal output module outputs the low-level signal to the input end of the buffer module, because the output signal of the buffer module is the same as the input signal, the output end of the buffer module outputs the low-level signal to the power-on signal input end of the low-level output preventing module, and because the low-level output preventing module is in the cut-off state, the power-on signal received by the power-on signal input end of the low-level output preventing module cannot be transmitted to the integrated power management circuit, the notebook computer cannot be started up when the power-on key is pressed in the state that the notebook computer is closed, no matter whether the signal received by the power-on signal input end of the low-level output preventing module is a high-level signal or a low-level signal, therefore, the startup forbidding circuit can effectively solve the problem that important data is lost due to overhigh temperature of a mainboard of the notebook computer because the notebook computer is always in a startup state under the environment with poor heat dissipation performance of the notebook computer because a startup key is pressed by mistake.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram illustrating a power-on disable circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating a startup prohibition circuit when the low-level output block according to the embodiment of the present application has a first structure;
fig. 3 is a schematic diagram illustrating a startup prohibition circuit when the low-level output block according to the embodiment of the present application has a second structure.
Reference numerals:
100: a starting signal output module; 110: a system power supply module; 120: a buffer module; 130: a Hall sensor; 140: a capacitor; 150: a first resistor; 151: a second resistor; 152: a third resistor; 153: a fourth resistor; 160: a block low level output module; 161: a first MOS transistor; 162: a second MOS transistor; 163: an OR gate; 170: a diode; 180: an integrated power management circuit.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the drawings in the embodiments of the present invention are combined below to clearly and completely describe the technical solutions in the embodiments of the present invention, and obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a power-on disable circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the power-on disable circuit includes: a power-on signal output module 100, a system power supply module 110, a buffer module 120, a hall sensor 130, a low-level-resistant output module 160, and an integrated power management circuit 180, wherein a signal output terminal of the power-on signal output module 100 is connected to an input terminal of the buffer module 120, a power input terminal of the buffer module 120 is connected to a power output terminal of the system power supply module 110, a ground terminal of the buffer module 120 is grounded, an output terminal of the buffer module 120 is connected to a power-on signal input terminal of the low-level-resistant output module 160, a control signal input terminal of the low-level-resistant output module 160 is connected to an output terminal of the hall sensor 130, an output terminal of the low-level-resistant output module 160 is connected to a signal input terminal of the integrated power management circuit 180, and a power input terminal of the hall sensor 130 is connected to a power output terminal of the system power supply module 110, the ground terminal of the hall sensor 130 is grounded, and when the notebook computer is closed, the power-on prohibition circuit is in the power-on prohibition state, so that the low-level output module 160 does not output the low-level power-on signal for turning on the notebook computer, and meanwhile, the hall sensor 130 outputs the low-level signal for prohibiting the low-level output module 160 from outputting to the control signal input terminal of the low-level output module 160.
Specifically, after the notebook computer is closed, the output end of the hall sensor 130 outputs a low level signal to the control signal input end of the low level output preventing module 160, and the control signal input end of the low level output preventing module 160 can switch on the low level output preventing module 160 only by receiving a high level control signal, and outputs a low level power-on signal for starting the notebook computer, so that after the notebook computer is closed, the low level output preventing module 160 cannot output a signal for starting the notebook computer, and therefore, even if the power-on key of the notebook computer is pressed after the notebook computer is closed, the integrated power management circuit 180 cannot receive the power-on signal output by the power-on signal output module 100, and the notebook computer cannot be started in the closed state.
Referring to fig. 2, fig. 2 is a schematic diagram of a power-on prohibition circuit when the low-level output block provided in the embodiment of the present application is in a first constituent structure, and as shown in fig. 2, the first circuit constituent structure of the low-level output block 160 includes: a first MOS transistor 161, a gate of the first MOS transistor 161 is connected to an output terminal of the hall sensor 130, a source of the first MOS transistor 161 is connected to an output terminal of the buffer module 120, a drain of the first MOS transistor 161 is connected to a signal input terminal of the integrated power management circuit 180, and when the low-level output block 160 is the first circuit composition structure, the power-on prohibition circuit further includes: a capacitor 140, a first resistor 150, a second resistor 151, a third resistor 152, and a diode 170, wherein a signal output terminal of the power-on signal output module 100 is connected to a first terminal of the first resistor 150, a second terminal of the first resistor 150 is connected to a power output terminal of the system power supply module 110, a power input terminal of the buffer module 120 is connected to a first plate of the capacitor 140, a second plate of the capacitor 140 is grounded, a gate of the first MOS transistor 161 is connected to a first terminal of the second resistor 151, a second terminal of the second resistor 151 is connected to a power output terminal of the system power supply module 110, a drain of the first MOS transistor 161 is connected to a first terminal of the third resistor 152, a second terminal of the third resistor 152 is connected to a negative terminal of the diode 170, and an anode of the diode 170 is connected to a signal input terminal of the integrated power management circuit 180, when the gate of the first MOS transistor 161 receives a low level signal output by the hall sensor 130, the first MOS transistor 161 is turned off, and when the gate of the first MOS transistor 161 receives a high level signal output by the hall sensor 130, the first MOS transistor 161 is turned on.
Specifically, after the notebook computer is closed, the output terminal of the hall sensor 130 outputs a low level, the voltage at the two ends of the second resistor 151 is pulled down, the gate of the first MOS transistor 161 receives a low level signal, the first MOS transistor 161 is turned off, when the power key is pressed down in the state that the notebook computer is closed, the output terminal of the power signal output module 100 outputs a low level to pull down the voltage at the two ends of the first resistor 150, the input terminal of the buffer module 120 receives a low level signal, because the output level of the buffer module 120 is the same as the input level, the output terminal of the buffer module 120 outputs a low level signal to the source of the first MOS transistor 161, but the first MOS transistor 161 is in the off state, and therefore the power signal cannot be transmitted to the integrated power management circuit 180 through the first MOS transistor 161, and the notebook computer cannot realize the power function in the closed state, when the notebook computer is unfolded, the hall sensor 130 outputs a high level, the gate of the first MOS transistor 161 receives a high level signal, the first MOS transistor 161 is turned on, when the notebook computer is in an unfolded state and the power key is pressed down, the output end of the power signal output module 100 outputs a low level to pull down the voltages at the two ends of the first resistor 150, the input end of the buffer module 120 receives a low level signal, because the output level of the buffer module 120 is the same as the input level, the output end of the buffer module 120 outputs a low level signal to the source electrode of the first MOS transistor 161, and because the first MOS transistor 161 is in a turned-on state, the output end of the first MOS transistor 161 outputs a low level signal to pull down the voltages at the two ends of the third resistor 152, and the input end of the integrated power management circuit 180 receives a low level signal to control the notebook computer to be turned on.
Referring to fig. 3, fig. 3 is a schematic diagram of a power-on prohibition circuit when the low-level output block provided by the embodiment of the present application is in a second configuration, and as shown in fig. 3, the second configuration of the low-level output block 160 includes: the second MOS transistor 162 and the or gate 163, a gate of the second MOS transistor 162 is connected to an output terminal of the hall sensor 130, a source of the second MOS transistor 162 is connected to a second input terminal of the or gate 163, a drain of the second MOS transistor 162 is grounded, a first input terminal of the or gate 163 is connected to an output terminal of the buffer module 120, an output terminal of the or gate 163 is connected to a signal input terminal of the integrated power management circuit 180, and when the low-level output block 160 is the second circuit composition structure, the power-on prohibition circuit further includes: a capacitor 140, a first resistor 150, a second resistor 151, a fourth resistor 153, and a diode 170, wherein a signal output terminal of the power-on signal output module 100 is connected to a first terminal of the first resistor 150, a second terminal of the first resistor 150 is connected to a power output terminal of the system power module 110, a power input terminal of the buffer module 120 is connected to a first plate of the capacitor 140, a second plate of the capacitor 140 is grounded, a gate of the second MOS transistor 162 is connected to a first terminal of the second resistor 151, a gate of the second MOS transistor 162 is connected to an output terminal of the hall inductor 130, a second terminal of the second resistor 151 is connected to a power output terminal of the system power module 110, an output terminal of the or gate 163 is connected to a first terminal of the fourth resistor 153, and a second terminal of the fourth resistor 153 is connected to a negative terminal of the diode 170, the anode of the diode 170 is connected to a signal input end of the integrated power management circuit 180, when the gate of the second MOS transistor 162 receives the low level signal output by the hall sensor 130, the second MOS transistor 162 is turned off, the or gate 163 outputs a high level signal, and when the gate of the second MOS transistor 162 receives the high level signal output by the hall sensor 130, the second MOS transistor 162 is turned on, and the or gate 163 outputs a low level signal.
Specifically, after the notebook computer is closed, the output end of the hall sensor 130 outputs a low level, the voltage at two ends of the second resistor 151 is pulled low, the gate of the second MOS transistor 162 receives a low level signal, the source of the second MOS transistor 162 is a high level, and therefore the second input end of the or gate 163 receives a high level signal, no matter the signal received by the first input end of the or gate 163 is a high level signal or a low level signal, the or gate 163 outputs a high level signal, and the integrated power management circuit 180 is triggered by a low level signal, so that the notebook computer cannot be started up when the start key is not pressed in a state that the notebook computer is closed, after the notebook computer is unfolded, the output end of the hall sensor 130 outputs a high level, and after the gate of the second MOS transistor 162 receives a high level signal, the source of the second MOS transistor 162 is a low level signal, and therefore the second input end of the or gate 163 receives a low level signal, when the power key is pressed down in the unfolded state of the notebook computer, the output end of the power signal output module 100 outputs a low level to pull down the voltages at the two ends of the first resistor 150, the input end of the buffer module 120 receives a low level signal, and since the output level of the buffer module 120 is the same as the input level, the output end of the buffer module 120 outputs a low level signal to the first output end of the or gate 163, so that the first input end of the or gate 163 inputs a low level signal, the second input end inputs a low level signal, the output end of the or gate 163 outputs a low level signal, the voltages at the two ends of the fourth resistor 153 are pulled down, the input end of the integrated power management circuit 180 receives a low level signal, and the notebook computer is turned on.
In one embodiment of the present application, the first MOS transistor 161 is an NMOS transistor.
Specifically, the first MOS transistor 161 is an NMOS transistor, a gate of the NMOS transistor is an input end of a control signal, when the notebook computer is closed or unfolded, a low level or high level signal output by an output end of the hall sensor 130 is received by the NMOS transistor, when the control signal is a low level signal, the NMOS transistor is turned off, when the NMOS transistor is turned off, a low level power-on signal received by a source of the NMOS transistor cannot be output to the integrated power management circuit 180, when the control signal is received by the NMOS transistor as a high level signal, the NMOS transistor is turned on, a low level power-on signal received by a source of the NMOS transistor is output to the integrated power management circuit 180, and the integrated power management circuit 180 controls the notebook computer to be powered on.
In an embodiment of the present application, the second MOS transistor 162 is an NMOS transistor.
Specifically, the second MOS transistor 162 is an NMOS transistor, a gate of the NMOS transistor is an input end of the control signal, when the notebook computer is closed or unfolded, a low level or a high level signal is output from an output end of the hall sensor 130, when the NMOS transistor receives the control signal, a source of the NMOS transistor is a high level signal, and when the gate of the NMOS transistor receives the high level signal, the source of the NMOS transistor is a low level signal, so that an output signal of the or gate 163 is controlled by a signal output from the source of the NMOS transistor.
In an embodiment of the present application, a gate of the first MOS transistor 161 is an input end for controlling the first MOS transistor 161 to be in an on-off state, a source of the first MOS transistor is an input end for a power-on signal, and a drain of the first MOS transistor is an output end for the power-on signal of the first MOS transistor.
Specifically, the first MOS transistor 161 is an NMOS transistor, the on or off of the NMOS transistor is controlled by a signal received by a gate of the NMOS transistor, and when the NMOS transistor is turned on, an output signal of the NMOS transistor is determined by a signal received by a source of the NMOS transistor.
In an embodiment of the present application, the power-on prohibition circuit shown in fig. 1 may be disposed on a notebook computer device, the notebook computer device further includes a magnet, after the notebook computer device is closed, a distance between the magnet and the hall sensor 130 is smaller than a distance between the magnet and the hall sensor 130 after the notebook computer device is unfolded, after the notebook computer device is covered by the cover, the hall sensor 130 outputs a low-level signal for preventing the low-level output module 160 from outputting, and after the notebook computer device is unfolded, the hall sensor 130 outputs a high-level signal for turning on and preventing the low-level output module 160 from outputting.
Specifically, after the notebook computer is closed, the distance between the magnet and the hall sensor 130 is smaller than the distance between the magnet and the hall sensor 130 before closing, when the distance between the magnet and the hall sensor 130 reaches a certain distance, the magnet can change the magnetic field around the hall sensor 130, so that the output end of the hall sensor 130 outputs a low level to the control signal input end of the low level prevention output module 160, so that the power-on signal of the low level prevention output module 160 cannot be output to the integrated power management circuit 180, after the notebook computer is unfolded, the hall sensor 130 is far away from the magnet, and at this time, the output end of the hall sensor 130 outputs a high level to the control signal input end of the low level prevention output module 160, so that the low level output module 160 is prevented from being turned on, and a low level power-on signal for starting the notebook computer is output.
In one embodiment of the present application, the notebook computer device includes: the power-on forbidding circuit is placed in the first shell.
Specifically, the startup forbidding circuit is a part of a notebook computer mainboard circuit.
In one embodiment of the present application, the notebook computer device includes: a second housing, the magnet being disposed within the second housing.
Specifically, the magnet is installed in the screen surface of the notebook computer, and the magnetic field around the hall sensor 130 is changed by changing the distance between the magnet and the hall sensor 130 in the power-on prohibition circuit, so that the output end of the hall sensor 130 outputs a control signal to control the on or off of the NMOS transistor, after the notebook computer is closed, the distance between the hall sensor 130 and the magnet is reduced, the output end of the hall sensor 130 outputs a low level, when the notebook computer is unfolded, the distance between the hall sensor 130 and the magnet is increased, and the output end of the hall sensor 130 outputs a high level.
In one embodiment of the present application, the power-on key of the notebook computer device is outside the housing.
Specifically, some notebook computers have a power-on key exposed outside the housing, and the power-on key is located on the side or top of the notebook computer.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention. Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims above, any of the claimed embodiments may be used in any combination. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.
Claims (10)
1. A power-on disable circuit, comprising: the power-on signal output module, the system power supply module, the buffer module, the Hall sensor, the low-level-resistant output module and the integrated power supply management circuit, wherein the signal output end of the power-on signal output module is connected with the input end of the buffer module, the power supply input end of the buffer module is connected with the power supply output end of the system power supply module, the output end of the buffer module is connected with the power-on signal input end of the low-level-resistant output module, the control signal input end of the low-level-resistant output module is connected with the output end of the Hall sensor, the output end of the low-level-resistant output module is connected with the signal input end of the integrated power supply management circuit, the power supply input end of the Hall sensor is connected with the power supply output end of the system power supply module, the grounding end of the Hall sensor is grounded, after the notebook, the startup forbidding circuit is in a startup forbidding state, so that the low-level output stopping module does not output a low-level signal for starting the notebook computer, and meanwhile, the Hall sensor outputs a low-level signal for stopping the output of the low-level output stopping module to the control signal input end of the low-level output stopping module.
2. The power-on disable circuit of claim 1, wherein the first circuit configuration of the low-level output block comprises: the gate of the first MOS transistor is connected to the output terminal of the hall sensor, the source of the first MOS transistor is connected to the output terminal of the buffer module, the drain of the first MOS transistor is connected to the signal input terminal of the integrated power management circuit, and the low-level output preventing module is the first circuit composition structure, the start-up prohibiting circuit further includes: the power-on signal output module comprises a capacitor, a first resistor, a second resistor, a third resistor and a diode, wherein the signal output end of the power-on signal output module is connected with the first end of the first resistor, the second end of the first resistor is connected with the power output end of the system power module, the power input end of the buffer module is connected with the first polar plate of the capacitor, the second polar plate of the capacitor is grounded, the grid electrode of the first MOS tube is connected with the first end of the second resistor, the second end of the second resistor is connected with the power output end of the system power module, the drain electrode of the first MOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the negative electrode of the diode, the positive electrode of the diode is connected with the signal input end of the integrated power management circuit, and when the grid electrode of the first MOS tube receives a low-level signal output by the Hall sensor, the first MOS tube is cut off, and when the grid electrode of the first MOS tube receives a high-level signal output by the Hall sensor, the first MOS tube is conducted.
3. The power-on disable circuit of claim 2, wherein the first MOS transistor is an NMOS transistor.
4. The power-on prohibition circuit of claim 2, wherein a gate of the first MOS transistor is an input terminal for controlling the first MOS transistor to be in an on-off state, a source of the first MOS transistor is a power-on signal input terminal, and a drain of the first MOS transistor is a power-on signal output terminal of the first MOS transistor.
5. The power-on disable circuit of claim 1, wherein the second circuit configuration for preventing the low-level output module comprises: the gate of the second MOS transistor is connected to the output terminal of the hall sensor, the source of the second MOS transistor is connected to the second input terminal of the or gate, the drain of the second MOS transistor is grounded, the first input terminal of the or gate is connected to the output terminal of the buffer module, the output terminal of the or gate is connected to the signal input terminal of the integrated power management circuit, and when the low-level output preventing module is the second circuit composition structure, the start-up prohibiting circuit further includes: the power-on signal output module comprises a capacitor, a first resistor, a second resistor, a fourth resistor and a diode, wherein the signal output end of the power-on signal output module is connected with the first end of the first resistor, the second end of the first resistor is connected with the power output end of the system power module, the power input end of the buffer module is connected with the first polar plate of the capacitor, the second polar plate of the capacitor is grounded, the grid electrode of the second MOS tube is connected with the first end of the second resistor, the grid electrode of the second MOS tube is connected with the output end of the Hall sensor, the second end of the second resistor is connected with the power output end of the system power module, the output end of the OR gate is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the negative electrode of the diode, and the positive electrode of the diode is connected with the signal input end of the integrated power management circuit, when the grid electrode of the second MOS tube receives the low level signal output by the Hall sensor, the second MOS tube is cut off, the OR gate outputs a high level signal, and when the grid electrode of the second MOS tube receives the high level signal output by the Hall sensor, the second MOS tube is conducted, and the OR gate outputs a low level signal.
6. The power-on disable circuit of claim 5, wherein the second MOS transistor is an NMOS transistor.
7. A notebook computer device, characterized in that, the notebook computer device includes a magnet and the power-on prohibition circuit of any one of claims 1 to 6, after the notebook computer device is covered, the distance between the magnet and the Hall sensor is smaller than the distance between the magnet and the Hall sensor after the notebook computer device is unfolded, after the notebook computer device is covered, the Hall sensor outputs a low level signal for preventing the low level output module from outputting, and after the notebook computer device is unfolded, the Hall sensor outputs a high level signal for conducting and preventing the low level output module from outputting.
8. The notebook computer device of claim 7, wherein the notebook computer device comprises: the power-on forbidding circuit is placed in the first shell.
9. The notebook computer device of claim 7, wherein the notebook computer device comprises: a second housing, the magnet being disposed within the second housing.
10. The notebook computer device of claim 7, wherein a power-on key of the notebook computer device is outside the housing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020855730.0U CN212208083U (en) | 2020-05-20 | 2020-05-20 | Startup forbidding circuit and notebook computer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020855730.0U CN212208083U (en) | 2020-05-20 | 2020-05-20 | Startup forbidding circuit and notebook computer device |
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| Publication Number | Publication Date |
|---|---|
| CN212208083U true CN212208083U (en) | 2020-12-22 |
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|---|---|---|---|
| CN202020855730.0U Expired - Fee Related CN212208083U (en) | 2020-05-20 | 2020-05-20 | Startup forbidding circuit and notebook computer device |
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| CN (1) | CN212208083U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699477A (en) * | 2022-12-23 | 2023-09-05 | 荣耀终端有限公司 | Spring needle interface connection state detection method, combined device and electronic equipment |
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2020
- 2020-05-20 CN CN202020855730.0U patent/CN212208083U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699477A (en) * | 2022-12-23 | 2023-09-05 | 荣耀终端有限公司 | Spring needle interface connection state detection method, combined device and electronic equipment |
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Effective date of registration: 20211027 Address after: 518011 floor 1, block B, Yinfeng building, No. 5097, Luosha Road, Xinxiu community, Huangbei street, Luohu District, Shenzhen, Guangdong Patentee after: Wentai Technology (Shenzhen) Co.,Ltd. Address before: Room 912-49, block B, 666 Beijing East Road, Huangpu District, Shanghai Patentee before: SHANGHAI WINGTECH ELECTRONICS TECHNOLOGY Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20201222 |