CN114243885A

CN114243885A - Power supply switching control circuit, integrated circuit with multiple power supplies and electronic equipment

Info

Publication number: CN114243885A
Application number: CN202111546980.1A
Authority: CN
Inventors: 顾艺; 刘勇江; 张阳
Original assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Current assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-03-25

Abstract

The application relates to a power supply switching control circuit, an integrated circuit powered by multiple power supplies and electronic equipment, and belongs to the technical field of electronic circuits. The power supply switching control circuit comprises a switching circuit and a control signal generating circuit; the switching circuit is used for selectively accessing the first power supply or the second power supply as an input power supply according to a control signal and outputting an internal power supply, wherein the control signal is a first control signal or a second control signal; the control signal generating circuit is used for receiving a detection signal representing the power-on condition of the first power supply and outputting the first control signal and the second control signal according to the detection signal, wherein the first control signal, the second control signal and the internal power supply are control signals of the same power domain, and only one of the first control signal and the second control signal is valid at the same time. The power-on in any sequence can be supported, and no leakage path is generated among multiple power supplies.

Description

Power supply switching control circuit, integrated circuit with multiple power supplies and electronic equipment

Technical Field

The application belongs to the technical field of electronic circuits, and particularly relates to a power supply switching control circuit, an integrated circuit powered by multiple power supplies and electronic equipment.

Background

With the development of integrated circuits, SOC (System on Chip) chips such as a CPU (Central Processing Unit), an MCU (Micro Controller Unit), and the like are increasingly used. The chips often have a plurality of power supplies, in order to meet various application scenarios, the power-on sequence among the power supplies cannot be fixed, and the power supplies need to be supported to be powered on arbitrarily, which requires a reliable power supply switching control circuit to be designed. If the power supply switching control circuit of the multi-power supply power-on system is unstable, a leakage path is easily formed between the powered power supply and the unpowered power supply, so that the voltage of the unpowered power supply is increased, and finally misjudgment of the chip system is caused to cause abnormal work.

Fig. 1 shows a commonly used power switching control circuit, in which transistors MP3 and MP4 are power switches, VDD18 and VDD33 are two different system power voltages, LV18 is an internal power voltage of a chip, PWROK is a detection signal for detecting power-on of VDD18, when VDD18 is powered on, PWROK is 1, and when VDD18 is not powered on, PWROK is 0.

The power switching control circuit appears to support in theory any power-up sequence, however, in practice only VDD18 is powered up first, followed by VDD 33. If VDD33 is powered on first and VDD18 is powered on later, a leakage path is formed between the powered power supply and the unpowered power supply, so that the voltage of the unpowered power supply is increased, and finally misjudgment of the chip system is caused to cause abnormal operation. Further, when only VDD33 is powered on, PWROK is 0, transistor MN0 is turned off, transistor MP4 is turned on, LV18 is local18, at this time, since VDD18 is in floating state, during the power-on process of VDD33, the floating voltage of VDD18 may cause transistor MP2 to be turned off, and at this time, pg _ ct voltage is also in floating state, transistor MP3 may be turned on, which may cause the voltage at VDD18 to rise, and finally, a stable state is maintained, and if the system detects that the voltage at VDD18 is high enough, PWROK is 1, which may cause a system malfunction.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a power switching control circuit, an integrated circuit powered by multiple power supplies, and an electronic device, so as to solve the problem that the conventional power switching control circuit may cause a leakage path between multiple power supplies in a specific power-on sequence, which may pull up a power voltage of an unpowered power supply, and finally cause a misjudgment of a chip system to cause an abnormal operation.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a power switching control circuit, including: a switching circuit and a control signal generating circuit; the switching circuit is used for connecting a first power supply and a second power supply, selectively accessing the first power supply or the second power supply as an input power supply according to a control signal, and outputting an internal power supply, wherein the control signal is a first control signal or a second control signal; the control signal generating circuit is used for receiving a detection signal representing the power-on condition of the first power supply and outputting the first control signal and the second control signal according to the detection signal, wherein the first control signal, the second control signal and the internal power supply are control signals of the same power domain, and only one of the first control signal and the second control signal is valid at the same time. In the embodiment of the application, because the first control signal and the second control signal are control signals of the same power domain and are both controlled by the detection signal, only one control signal in the first control signal and the second control signal is valid at the same time, and the influence of a VDD18 floating (floating) state on the control signals is eliminated, so that a conduction path between a powered power supply and a non-powered power supply can be avoided, and any sequence of power-on can be supported.

With reference to one possible implementation manner of the embodiment of the first aspect, the control signal generating circuit includes: a level conversion circuit and an inverter circuit; the level conversion circuit is connected with the switching circuit and is used for receiving the detection signal of the same power domain as the first power supply and converting the detection signal into the first control signal which is the same power domain as the internal power supply and is opposite to the detection signal; the inverting circuit is connected with the level conversion circuit and the switching circuit and is used for inverting the first control signal to obtain the second control signal. In the embodiment of the application, the level conversion circuit is adopted to convert the detection signal into the first control signal which is in the same power domain as the internal power supply and is opposite to the detection signal, and then the phase inversion circuit is utilized to invert the first control signal, so that two control signals of the same power domain can be obtained, and only one control signal is effective at the same time.

With reference to one possible implementation manner of the embodiment of the first aspect, the level shift circuit includes a first transistor and a first impedance device; the control end of the first transistor is used for receiving the detection signal, the first end of the first transistor is connected with the output end of the switching circuit, which is used for outputting the internal power supply, through the first impedance device, the second end of the first transistor is grounded, the first end of the first transistor is also connected with the inverter circuit and the first control end of the switching circuit, and the first control end is used for receiving the first control signal; or, the control end of the first transistor is configured to receive the detection signal, the second end of the first transistor is connected to the output end of the switching circuit, which is configured to output the internal power supply, the first end of the first transistor is grounded through the first impedance device, and the first end of the first transistor is further connected to the inverting circuit and the first control end of the switching circuit. In the embodiment of the application, the common devices such as the transistor and the impedance device are adopted to form the level conversion circuit, so that the invention aims are achieved, the cost can be saved, and more importantly, the volume of the circuit can be reduced.

With reference to a possible implementation manner of the embodiment of the first aspect, if the first transistor is an NMOS transistor, a first end of the first transistor is connected to the output end of the switching circuit, which is used for outputting the internal power supply, through the first impedance device, a second end of the first transistor is grounded, and the first end of the first transistor is further connected to the inverter circuit and a first control end of the switching circuit; if the first transistor is a PMOS transistor, the second end of the first transistor is connected to the output end of the switching circuit, which is used for outputting the internal power supply, the first end of the first transistor is grounded through the first impedance device, and the first end of the first transistor is further connected to the inverter circuit and the first control end of the switching circuit. In the embodiment of the application, when the first transistor is an MOS transistor of different types, the same function can be realized by changing the connection mode in the circuit, and the flexibility and the applicability of the scheme are further improved.

With reference to one possible implementation manner of the embodiment of the first aspect, the inverter circuit includes: PMOS tube and NMOS tube; the control end of the PMOS tube is connected with the first end of the first transistor, and the second end of the PMOS tube is connected with the output end of the switching circuit, which is used for outputting the internal power supply; the control end of the NMOS tube is connected with the first end of the first transistor, the first end of the NMOS tube is connected with the first end of the PMOS tube, and the second end of the NMOS tube is grounded. In the embodiment of the application, because the PMOS tube and the NMOS tube are common devices, the inverter circuit with the structure can solve the cost, reduce the circuit volume and be beneficial to circuit integration.

With reference to one possible implementation manner of the embodiment of the first aspect, the inverter circuit includes: the control end of the second transistor is connected with the first end of the first transistor; if the first end of the first transistor is connected with the output end of the switching circuit for outputting the internal power supply through the first impedance device, the first end of the second transistor is connected with the output end of the switching circuit for outputting the internal power supply through the second impedance device, and the second end of the second transistor is grounded; if the second end of the first transistor is connected to the output end of the switching circuit for outputting the internal power supply, the second end of the second transistor is connected to the output end of the switching circuit for outputting the internal power supply, and the first end of the second transistor is grounded via the second impedance device. In the embodiment of the application, the inverter circuit can be formed by adopting a transistor and an impedance device, so that the applicability of the scheme is further enhanced.

With reference to one possible implementation manner of the embodiment of the first aspect, the first impedance device and the second impedance device include at least one of a resistor device and a transistor. In the embodiment of the present application, the impedance device may be a resistor device or a transistor, which further enhances the applicability of the scheme.

In a second aspect, an embodiment of the present application further provides an integrated circuit powered by multiple power supplies, including a chip circuit and a power supply switching control circuit provided as in the foregoing first aspect and/or in combination with any one of the possible implementations of the first aspect, where the power supply switching control circuit is configured to provide different internal power supplies for the chip circuit.

In combination with one possible implementation manner of the embodiment of the second aspect, the integrated circuit is a processor.

In a third aspect, an embodiment of the present application further provides an electronic device, including: a first power supply, a second power supply, and an integrated circuit as provided in the above-mentioned embodiment of the second aspect and/or in connection with one possible implementation of the embodiment of the second aspect, the integrated circuit being connected to the first power supply and the second power supply, respectively.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 is a schematic diagram of a conventional power switching control circuit.

Fig. 2 shows a schematic structural diagram of a power supply switching control circuit provided in an embodiment of the present application.

Fig. 3 is a schematic structural diagram illustrating a connection between a switching circuit and a control signal generating circuit according to an embodiment of the present disclosure.

Fig. 4 shows a schematic circuit diagram of a power supply switching control circuit according to an embodiment of the present application.

Fig. 5 is a schematic circuit diagram illustrating a power switching control circuit according to an embodiment of the present disclosure.

Fig. 6 shows a schematic circuit diagram of another power supply switching control circuit provided in an embodiment of the present application.

Fig. 7 shows a schematic circuit diagram of another power supply switching control circuit provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as meaning either a fixed connection, a detachable connection, or an integral connection; or may be an electrical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In view of the fact that the conventional power switching control circuit does not support any power-on sequence, and in a specific power-on sequence (e.g., VDD33 is powered on first, and VDD18 is powered on later), a leakage path exists between multiple power supplies, which may pull up the voltage of the unpowered power supply, and finally cause a problem of abnormal operation caused by misjudgment of the chip system. The embodiment of the application provides a power supply switching control circuit capable of supporting any power-on, and a leakage path cannot be generated among multiple power supplies of the power supply switching control circuit, so that the voltage of a power supply which is not powered on cannot be increased, and the situation that a chip system is judged by mistake to cause abnormal work due to the fact that the voltage of the power supply which is not powered on is increased cannot occur.

For ease of understanding, the following description will be made in conjunction with the power supply switching control circuit shown in fig. 2. The power supply switching control circuit includes a switching circuit and a control signal generating circuit. The switching circuit is connected with the control signal generating circuit, and the control signal generating circuit is used for controlling the switching circuit to selectively access a first power supply (such as VDD18) or a second power supply (such as VDD33) as an input power supply and output an internal power supply.

The switching circuit is used for connecting a first power supply (such as VDD18) and a second power supply (such as VDD33), and the switching circuit is used for selectively connecting the first power supply or the second power supply as an input power supply according to a control signal and outputting an internal power supply, wherein the control signal is the first control signal or the second control signal.

Optionally, the switching circuit comprises: a first switch tube (such as MP3), a second switch tube (such as MP4) and a voltage divider circuit. The first end of the first switch tube is used for being connected with a first power supply (VDD18), the second end of the first switch tube is connected with the second end of the second switch tube, and the first end of the first switch tube is connected with the voltage division circuit. The control end of the first switch tube and the control end of the second switch tube are both connected with the control signal generating circuit. One end of the voltage dividing circuit is connected to a second power source (VDD33), the other end of the voltage dividing circuit is grounded, and the voltage dividing circuit is used for dividing the second power source and outputting a divided voltage (e.g., local 18). In one embodiment, a schematic circuit diagram of the switching circuit is shown in fig. 3. In fig. 3, the transistor MP3 is a first switch tube, the transistor MP4 is a second switch tube, the voltage divider circuit includes a resistor R1 and a resistor R0, LV18 is an output end of the switching circuit, and an internal power supply output by the voltage divider circuit can be represented by LV 18.

The control signal generating circuit is connected with the switching circuit and is used for receiving a detection signal (such as PWROK) representing the power-on condition of the first power supply and outputting a first control signal and a second control signal according to the detection signal. The first control signal, the second control signal and the internal power supply are control signals of the same power domain, and only one of the first control signal and the second control signal is valid at the same time. Since the transistors MP3 and MP4 in fig. 3 are both PMOS transistors and are turned on at low level, only one of the first control signal and the second control signal is at low level at the same time. Because the first control signal and the second control signal in the present application are control signals of the same power domain and are both controlled by the detection signal, only one of the first control signal and the second control signal is valid at the same time, and the influence of the VDD18 floating state on the control signals is eliminated, so that a conduction path between the powered power supply and the unpowered power supply can be avoided.

In one embodiment, the control signal generating circuit includes a level shift circuit and an inverter circuit. The level conversion circuit is connected with the switching circuit and is used for receiving a detection signal which is in the same power domain as the first power supply and converting the detection signal into a first control signal which is in the same power domain as the internal power supply and is opposite to the detection signal. The inverting circuit is connected with the level conversion circuit and the switching circuit and used for inverting the phase of the first control signal to obtain a second control signal.

Optionally, the level shifter circuit comprises a first transistor and a first impedance device. The control end of the first transistor is used for receiving a detection signal, the first end of the first transistor is connected with the output end of the switching circuit, which is used for outputting an internal power supply, through the first impedance device, the second end of the first transistor is grounded, the first end of the first transistor is also connected with the first control end of the inverter circuit and the first control end of the switching circuit, and the first control end is used for receiving a first control signal. Or the control end of the first transistor is used for receiving the detection signal, the second end of the first transistor is connected with the output end of the switching circuit, which is used for outputting the internal power supply, the first end of the first transistor is grounded through the first impedance device, and the first end of the first transistor is also connected with the inverter circuit and the first control end of the switching circuit.

If the first transistor is an NMOS transistor, the first end of the first transistor is connected to the output end of the switching circuit for outputting the internal power supply through the first impedance device, the second end of the first transistor is grounded, and the first end of the first transistor is further connected to the inverter circuit and the first control end of the switching circuit. If the first transistor is a PMOS transistor, the second end of the first transistor is connected to the output end of the switching circuit for outputting the internal power, the first end of the first transistor is grounded through the first impedance device, and the first end of the first transistor is further connected to the inverter circuit and the first control end of the switching circuit.

Wherein the first impedance device may be a resistive device or a transistor. The transistor can be an NMOS transistor or a PMOS transistor. When in connection, the drain and the gate of the MOS transistor may be commonly used as one of the connection terminals, and the source may be used as the other connection terminal. For example, when the first transistor is an NMOS transistor and the first impedance device is a PMOS transistor, the drain and the gate of the PMOS transistor are connected to the first end of the first transistor, and the source is connected to the output end of the switching circuit for outputting the internal power. For another example, when the first transistor is an NMOS transistor and the first impedance device is an NMOS transistor, the drain and the gate of the first impedance device (which is an NMOS transistor) are connected to the output terminal of the switching circuit for outputting the internal power source, and the source of the first impedance device is connected to the first terminal of the first transistor.

The drain of the MOS transistor may be one of the connection terminals, and the source may be the other connection terminal, and the gate of the MOS transistor may be grounded or connected to the power supply to be normally on. When the first impedance device is a PMOS tube, the grid electrode of the PMOS tube is grounded, and when the first impedance device is an NMOS tube, the grid electrode of the NMOS tube is connected with a power supply.

In an alternative embodiment, an inverter circuit includes: PMOS pipe and NMOS pipe. The control end of the PMOS tube is connected with the first end of the first transistor, and the second end of the PMOS tube is connected with the output end of the switching circuit, which is used for outputting the internal power supply. The control end of the NMOS tube is connected with the first end of the first transistor, the first end of the NMOS tube is connected with the first end of the PMOS tube, and the second end of the NMOS tube is grounded.

In yet another alternative embodiment, an inverter circuit includes: a second transistor and a second impedance device. The control terminal of the second transistor is connected with the first terminal of the first transistor. If the first end of the first transistor is connected with the output end of the switching circuit for outputting the internal power supply through the first impedance device, the first end of the second transistor is connected with the output end of the switching circuit for outputting the internal power supply through the second impedance device, and the second end of the second transistor is grounded; if the second end of the first transistor is connected with the output end of the switching circuit for outputting the internal power supply, the second end of the second transistor is connected with the output end of the switching circuit for outputting the internal power supply, and the first end of the second transistor is grounded through the second impedance device.

The second transistor can be an NMOS transistor or a PMOS transistor, when the second transistor is an NMOS transistor, the first end of the second transistor is connected with the output end of the switching circuit for outputting the internal power supply through the second impedance device, and the second end of the second transistor is grounded; when the transistor is a PMOS transistor, the second end of the second transistor is connected to the output end of the switching circuit for outputting the internal power, and the first end of the second transistor is grounded through the second impedance device.

The second impedance device may be a resistive device or a transistor, similar to the first impedance device. The transistor can be an NMOS transistor or a PMOS transistor. When in connection, the drain electrode and the grid electrode of the MOS tube are jointly used as one connection end, and the source electrode is used as the other connection end. In addition, the connection can also be in a switch form, and the specific connection mode is referred to the description of the first impedance device.

In order to facilitate understanding of the structure of the control signal generating circuit, the principle of the control signal generating circuit will be described below with reference to a partial schematic diagram. When the first transistor is an NMOS transistor, the first impedance device is a resistor device, as denoted by R2, and the inverter circuit includes a PMOS transistor and an NMOS transistor, the schematic circuit diagram of the power switching control circuit is shown in fig. 4. The transistors MP3 and MP4 are switching transistors of the switching circuit, and the control signal generating circuit includes a transistor MN0, a resistor R2, a transistor MP1, and a transistor MN1, wherein the transistor MN0 and the resistor R2 form a level shifter, and the transistor MP1 and the transistor MN1 form an inverter circuit. The substrate (source terminal) of all PMOS transistors is connected to LV 18. When only VDD33 is powered on, PWROK is 0, the drain terminal of the transistor MP4 and the parasitic forward diode of the substrate raise the voltage level of LV18 to local18-Vth (threshold voltage, also referred to as turn-on voltage), at which time the control signal generation circuit starts to operate, pg _ ct is LV18, the transistor MN1 is turned on pgb _ ct is 0, at which time the transistor MP4 is turned on, LV18 is local18, and the transistor MP3 is completely turned off. When only VDD18 is powered on, PWROK is 1, transistor MN0 is turned on, pg _ ct is 0, and at this time, transistor MP3 and transistor MP1 are turned on, transistor MN1 is turned off, LV18 is VDD18, transistor pgb _ ct is LV18, and transistor MP4 is completely turned off. In order to eliminate the influence of the floating state of VDD18 on the control signal, the first control signal (pg _ ct) is no longer controlled by the floating state of VDD18, and is in the LV18 power domain with the second control signal (pgb _ ct) of transistor MP4, so that a conduction path is not formed between the powered power supply and the unpowered power supply.

The transistor MP4 of the conventional power switching control circuit shown in fig. 1 is controlled by the PWROK signal, the transistor MP3 is controlled by the pg _ ct signal, and the pg _ ct signal is controlled by LV18, PWROK, VDD 18. When only VDD33 is powered on, VDD18 is in a floating state, PWROK is 0, transistor MN0 is turned off, transistor MP4 is turned on, LV18 is local18, during the power-on process of VDD33, the floating voltage of VDD18 may cause transistor MP2 to be turned off, and the pg _ ct voltage is also in the floating state, if the floating voltage is smaller than LV18-Vth, transistor MP3 is turned on, so that the voltage at VDD18 rises, and finally a stable state is maintained, and if the system detects that the voltage at VDD18 is high enough, PWROK 1 is output, so that the system malfunctions.

When the first transistor is an NMOS transistor, the first impedance device is a PMOS transistor, as indicated by P, and the inverter circuit includes a second transistor (which is an NMOS transistor) and a second impedance device (which is a resistor device, as indicated by R3), a schematic circuit diagram of the power switching control circuit is shown in fig. 5. The transistors MP3 and MP4 in fig. 5 are switching transistors of the switching circuit, and the control signal generating circuit includes a transistor MN0, a transistor P (connected in a diode form in the figure), a transistor MN1, and a resistor R3, wherein the transistor MN0 and the transistor P form a level shifter circuit, and the transistor MN1 and the resistor R3 form an inverter circuit. The substrate (source terminal) of all PMOS transistors is connected to LV 18. When only VDD33 is powered on, PWROK is 0, transistor MN0 is turned off, the drain terminal of transistor MP4 and the parasitic forward diode of the substrate raise LV18 to local18-Vth, at this time, the control signal generation circuit starts to operate, pg _ ct is LV18, transistor MN1 is turned on, pgb _ ct is 0, transistor MP4 is turned on, LV18 is local18, and transistor MP3 is completely turned off. When only VDD18 is powered on, PWROK is 1, transistor MN0 is turned on, pg _ ct is 0, and at this time, transistor MP3 is turned on, LV18 is VDD18, transistor MN1 is turned off, pgb _ ct is LV18, and transistor MP4 is completely turned off.

When the first transistor is a PMOS transistor, the first impedance device is an NMOS transistor, as represented by N, and the inverter circuit includes a PMOS transistor and an NMOS transistor, the schematic circuit diagram of the power switching control circuit is shown in fig. 6. The transistors MP3 and MP4 in fig. 6 are switching transistors of the switching circuit, and the control signal generating circuit includes a transistor MP0, a transistor N (connected in a switching manner in the figure), a transistor MP1, and a transistor MN1, wherein the transistor MP0 and the transistor N form a level shift circuit, and the transistor MN1 and the transistor MP1 form an inverter circuit. The substrate (source terminal) of all PMOS transistors is connected to LV 18. When only VDD33 is powered on, PWROK is 0, LV18 is raised to local18-Vth by the drain of transistor MP4 and the parasitic forward diode of the substrate, the control signal generating circuit starts to operate, transistor MP0 is turned on, pg _ ct is LV18, transistor MP1 is turned off, transistor MN1 is turned on, pgb _ ct is 0, transistor MP4 is turned on, LV18 is local18, and transistor MP3 is completely turned off. When only VDD18 is powered on, PWROK is 1, transistor MP0 is turned off, pg _ ct is 0, at this time, transistor MP3 is turned on, LV18 is VDD18, transistor MP1 is turned on, transistor MN1 is turned off, pgb _ ct is LV18, and transistor MP4 is completely turned off.

When the first transistor is a PMOS transistor, the first impedance device is a resistor device, as indicated by R2, and the inverter circuit includes a second transistor (which is a PMOS transistor) and a second impedance device (which is a resistor device, as indicated by R3), the schematic circuit diagram of the power switching control circuit is shown in fig. 7. In fig. 7, the transistors MP3 and MP4 are switching transistors of a switching circuit, and the control signal generating circuit includes a transistor MP0, a resistor R2, a transistor MP1, and a resistor R3, wherein the transistor MP0 and the resistor R2 form a level shifter, and the transistor MP1 and the resistor R3 form an inverter circuit. The substrate (source terminal) of all PMOS transistors is connected to LV 18. When only VDD33 is powered on, PWROK is 0, LV18 is raised to local18-Vth by the drain of transistor MP4 and the parasitic forward diode of the substrate, the control signal generating circuit starts to operate, transistor MP0 is turned on, pg _ ct is LV18, transistor MP1 is turned off, pgb _ ct is 0, transistor MP4 is turned on, LV18 is local18, and transistor MP3 is completely turned off. When only VDD18 is powered on, PWROK is 1, transistor MP0 is turned off, pg _ ct is 0, at this time, transistor MP3 is turned on, LV18 is VDD18, transistor MP1 is turned on, pgb _ ct is LV18, and transistor MP4 is completely turned off.

In another embodiment, the control signal generating circuit may not adopt the above-mentioned structure including the level shift circuit and the inverter circuit, but the control signal generating circuit includes a processor, and in this case, the processor is configured to receive a detection signal indicating a power-on condition of the first power supply, and output the first control signal and the second control signal according to the detection signal. The first control signal, the second control signal and the internal power supply are control signals of the same power domain, and only one of the first control signal and the second control signal is valid at the same time. For example, when the detection signal (PWROK ═ 0) indicates that the first power supply is not powered on, the first control signal at a high level and the second control signal at a low level are output; when the detection signal (PWROK ═ 1) indicates that the first power supply is powered on, the first control signal with low level and the second control signal with high level are output. Therefore, the above-described implementation in which the control signal generation circuit includes the level shift circuit and the inverter circuit cannot be understood as a limitation of the control signal generation circuit.

Based on the same inventive concept, the embodiment of the application further provides a multi-power-supply integrated circuit, which comprises a chip circuit and the power supply switching control circuit, wherein the power supply switching control circuit is used for providing different internal power supplies for the chip circuit so as to meet power consumption requirements of different application scenes. The integrated circuit powered by multiple power supplies may be a processor, for example, the processor may be an integrated circuit such as a CPU (Central Processing Unit), an MCU (Micro Controller Unit), and the like.

For a brief description, reference may be made to the corresponding contents in the foregoing power switching control circuit embodiment for a part of the embodiment of the integrated circuit with multiple power supplies that is not mentioned.

Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes a first power supply, a second power supply, and the above-mentioned multi-power-supply integrated circuit, where the multi-power-supply integrated circuit is respectively connected to the first power supply and the second power supply, for example, a switching circuit in a power supply switching control circuit in the multi-power-supply integrated circuit is connected to the first power supply and the second power supply. The electronic device may be a device with multiple power supply requirements, for example, a mobile phone, a tablet, a computer, a server, and the like.

The power switching control circuit provided in the embodiment of the electronic device has the same implementation principle and technical effect as those of the power switching control circuit embodiment, and for brief description, reference may be made to the corresponding contents in the power switching control circuit embodiment for the part of the embodiment of the electronic device that is not mentioned.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A power switching control circuit, comprising:

the switching circuit is used for selectively accessing the first power supply or the second power supply as an input power supply according to a control signal and outputting an internal power supply, wherein the control signal is a first control signal or a second control signal;

and the control signal generating circuit is connected with the switching circuit and is used for receiving a detection signal representing the power-on condition of the first power supply and outputting the first control signal and the second control signal according to the detection signal, wherein the first control signal, the second control signal and the internal power supply are control signals of the same power domain, and only one of the first control signal and the second control signal is valid at the same time.

2. The power supply switching control circuit of claim 1, wherein the control signal generating circuit comprises:

the level conversion circuit is connected with the switching circuit and is used for receiving the detection signal of the same power domain as the first power supply and converting the detection signal into the first control signal of the same power domain as the internal power supply and opposite to the detection signal;

and the inverting circuit is connected with the level conversion circuit and the switching circuit and is used for inverting the first control signal to obtain the second control signal.

3. The power switching control circuit of claim 2, wherein the level shifter circuit comprises a first transistor and a first impedance device, a control terminal of the first transistor is configured to receive the detection signal, a first terminal of the first transistor is further connected to the inverter circuit and a first control terminal of the switching circuit, the first control terminal is configured to receive the first control signal,

a first end of the first transistor is connected with an output end of the switching circuit for outputting the internal power supply through the first impedance device, and a second end of the first transistor is grounded; or, the second end of the first transistor is connected to the output end of the switching circuit for outputting the internal power supply, and the first end of the first transistor is grounded via the first impedance device.

4. The power switching control circuit according to claim 3, wherein if the first transistor is an NMOS transistor, a first terminal of the first transistor is connected to an output terminal of the switching circuit for outputting the internal power supply via the first impedance device, and a second terminal of the first transistor is grounded;

if the first transistor is a PMOS transistor, the second end of the first transistor is connected to the output end of the switching circuit for outputting the internal power supply, and the first end of the first transistor is grounded through the first impedance device.

5. The power supply switching control circuit according to claim 3, wherein the inverter circuit comprises:

the control end of the PMOS tube is connected with the first end of the first transistor, and the second end of the PMOS tube is connected with the output end of the switching circuit, which is used for outputting the internal power supply;

the control end of the NMOS tube is connected with the first end of the first transistor, the first end of the NMOS tube is connected with the first end of the PMOS tube, and the second end of the NMOS tube is grounded.

6. The power supply switching control circuit according to claim 3, wherein the inverter circuit comprises: the control end of the second transistor is connected with the first end of the first transistor;

if the first end of the first transistor is connected with the output end of the switching circuit for outputting the internal power supply through the first impedance device, the first end of the second transistor is connected with the output end of the switching circuit for outputting the internal power supply through the second impedance device, and the second end of the second transistor is grounded;

if the second end of the first transistor is connected to the output end of the switching circuit for outputting the internal power supply, the second end of the second transistor is connected to the output end of the switching circuit for outputting the internal power supply, and the first end of the second transistor is grounded via the second impedance device.

7. The power switching control circuit of claim 6, wherein the first impedance device and the second impedance device comprise at least one of a resistor device and a transistor.

8. A multi-power-supply integrated circuit comprising chip circuitry and a power-supply-switching control circuit as claimed in any one of claims 1 to 7 for providing different internal power supplies to said chip circuitry.

9. The integrated circuit of claim 8, wherein the integrated circuit is a processor.

10. An electronic device, comprising: a first power supply, a second power supply and an integrated circuit as claimed in claim 8 or 9, the integrated circuit being connected to the first power supply and the second power supply respectively.