CN212033003U - Medium-high power semiconductor device with special surface metallization - Google Patents

Medium-high power semiconductor device with special surface metallization Download PDF

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Publication number
CN212033003U
CN212033003U CN202021037161.5U CN202021037161U CN212033003U CN 212033003 U CN212033003 U CN 212033003U CN 202021037161 U CN202021037161 U CN 202021037161U CN 212033003 U CN212033003 U CN 212033003U
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CN
China
Prior art keywords
window
transition metal
passivation layer
solder
semiconductor device
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Application number
CN202021037161.5U
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Chinese (zh)
Inventor
朱袁正
周锦程
杨卓
叶鹏
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Wuxi NCE Power Co Ltd
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Wuxi NCE Power Co Ltd
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Priority to CN202021037161.5U priority Critical patent/CN212033003U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Abstract

The utility model relates to a power semiconductor device technical field specifically discloses a well high-power semiconductor device of special surface metallization, including metal disc and the first solder on it, the top of first solder sets up power chip, and the surface of semiconductor power chip sets up first passivation layer, sets up the window on the first passivation layer, sets up first transition metal and second transition metal in the window, and second transition metal sets up the second passivation layer with the surface of first passivation layer, sets up the window in the second passivation layer of second transition metal top once more, and sets up the second solder in this window, and the sheetmetal electrode passes through the second solder and is connected with the chip electricity. The utility model discloses make the distance between the window on semiconductor power chip surface can freely adjust, when obtaining better heat dissipation, lower encapsulation resistance and parasitic inductance, improved the yield of product.

Description

Medium-high power semiconductor device with special surface metallization
Technical Field
The utility model relates to a power semiconductor device technical field, more specifically relates to a well high-power semiconductor device of special surface metallization.
Background
In the field of semiconductor devices, there are many challenges in fabricating a plurality of semiconductor device packaged chips on one wafer. This is especially true for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, particularly vertically conducting power MOSFET devices having gate and source regions on one surface of the chip and a drain region on the opposite surface. Electrical connections are made to the front side of the designated chip and must be made additionally to the back side of the device. In a semiconductor package, if the chip area is too small, the source and gate regions are very close together, causing the solder to easily bond together, resulting in device failure.
SUMMERY OF THE UTILITY MODEL
The utility model provides a well high-power semiconductor device of special surface metallization to solve the chip area undersize that exists among the prior art, source region and gate region are very close to, lead to the solder to link together easily, thereby lead to the problem that the device became invalid.
As a first aspect of the present invention, there is provided a medium-and high-power semiconductor device with special surface metallization, comprising a metal plate, wherein a first solder is disposed on the metal plate, a semiconductor power chip is disposed above the first solder, a first passivation layer is disposed on a surface of the semiconductor power chip, a first window and a second window are disposed on the first passivation layer, a first transition metal is disposed in each of the first window and the second window, a second transition metal is disposed on a surface of the first transition metal, a second passivation layer is disposed on a surface of each of the second transition metal and the first passivation layer, a third window is disposed in the second passivation layer above the second transition metal in the first window, a fourth window is disposed in the second passivation layer above the second transition metal in the second window, and a second solder is disposed in each of the third window and the fourth window, and a first metal sheet electrode is arranged above the second welding flux in the third window, and a second metal sheet electrode is arranged above the second welding flux in the fourth window.
Further, the second solder in the third window is in contact with the second transition metal in the first window, and the second solder in the fourth window is in contact with the second transition metal in the second window; the third window is completely overlapped or partially overlapped with the boundary of the first window, and the fourth window is completely overlapped or partially overlapped with the boundary of the second window.
Further, the first passivation layer and the second passivation layer are both composed of insulating dielectric layers.
Further, the second transition metal, the first sheet metal electrode, and the second sheet metal electrode are each composed of copper, silver, or gold.
Further, the first transition metal is composed of a single metal or a composite metal.
Further, the first transition metal is tungsten or nickel-gold.
The utility model provides a well high-power semiconductor device of special surface metallization has following advantage:
1) the utility model obviously increases the thickness of the chip through two times of passivation, provides strong support for the chip, and ensures that the ultrathin wafer is not easy to damage;
2) the first window and the third window, the second window and the fourth window can be partially overlapped, so that the distance between the third window and the fourth window on the second passivation layer is increased when the chip area is smaller, and the connection of second welding fluxes in the two windows is prevented to cause the failure of a device;
3) the utility model discloses a set up first transition metal and second transition metal for the device can obtain lower encapsulation resistance, parasitic inductance and thermal resistance.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic cross-sectional structural diagram of a first window and a second window formed on a first passivation layer according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional structural diagram of forming a first transition metal and a second transition metal according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional structural diagram of the first transition metal and the second transition metal on the surface of the first passivation layer according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structural diagram of forming a third window and a fourth window on a second passivation layer according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of a semiconductor power chip soldered on a metal plate by a solder according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional structural diagram of forming a second solder in a third window and a fourth window according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional structural diagram of a medium-large semiconductor power device with special surface metallization according to an embodiment of the present invention.
Description of reference numerals: 01 — a first window; 02 — second window; 03 — third window; 04 — a fourth window; 1-a semiconductor power chip; 2-a first passivation layer; 3-a first transition metal; 4-a second passivation layer; 5-a first solder; 6-metal disc; 7-second solder; 8-a first sheet metal electrode; 9-a second sheet metal electrode; 10-a second transition metal.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose of the present invention, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of the semiconductor device with medium and high power, its specific embodiments, structures, features and effects according to the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
In the present embodiment, a medium-power semiconductor device with special surface metallization is provided, fig. 7 is a schematic cross-sectional structure diagram of a medium-power semiconductor device with special surface metallization provided according to an embodiment of the present invention, as shown in fig. 7, including a metal disc 6, a first solder 5 is disposed on the metal disc 6, a semiconductor power chip 1 is disposed above the first solder 5, a first passivation layer 2 is disposed on a surface of the semiconductor power chip 1, a first window 01 and a second window 02 are disposed on the first passivation layer 2, a first transition metal 3 is disposed in each of the first window 01 and the second window 02, a second transition metal 10 is disposed on a surface of the first transition metal 3, a second passivation layer 4 is disposed on a surface of the second transition metal 10 and the first passivation layer 2, a third window 03 is disposed in the second passivation layer 4 above the second transition metal 10 in the first window 01, a fourth window 04 is arranged in the second passivation layer 4 above the second transition metal 10 in the second window 02, second solders 7 are arranged in the third window 03 and the fourth window 04, a first metal sheet electrode 8 is arranged above the second solders 7 in the third window 03, and a second metal sheet electrode 9 is arranged above the second solders 7 in the fourth window 04.
Preferably, the second solder 7 in the third window 03 is in contact with the second transition metal 10 in the first window 01, and the second solder 7 in the fourth window 04 is in contact with the second transition metal 10 in the second window 02; the third window 03 completely overlaps or partially overlaps with the boundary of the first window 01, and the fourth window 04 completely overlaps or partially overlaps with the boundary of the second window 02; when the third window 03 overlaps with the boundary portion of the first window 01 and the fourth window 04 overlaps with the boundary portion of the second window 02, the distance between the first window 01 and the second window 02 is smaller than the distance between the third window 03 and the fourth window 04.
Preferably, the first passivation layer 2 and the second passivation layer 4 are both composed of insulating dielectric layers; wherein the first passivation layer 2 and the second passivation layer 4 are both made of silicon dioxide.
Preferably, the second transition metal 10, the first sheet metal electrode 8 and the second sheet metal electrode 9 are all made of copper, silver or gold.
Preferably, the first transition metal 3 is composed of a single metal or a composite metal.
Preferably, the first transition metal 3 is tungsten or nickel gold.
As another embodiment of the present invention, there is provided a method for manufacturing a medium and high power semiconductor device with special surface metallization, wherein, as shown in fig. 1 to 7, the method includes the following steps:
the method comprises the following steps: as shown in fig. 1, completing a first passivation of the chip surface on a wafer to form a first passivation layer 2, and providing a first window 01 and a second window 02 on the first passivation layer 2;
step two: as shown in fig. 2, a first transition metal 3 is formed on the surface of the wafer, and then a second transition metal 10 is formed on the surface of the first transition metal 3;
step three: as shown in fig. 3, the first transition metal 3 and the second transition metal 10 on the surface of the first passivation layer 2 are removed by a grinding process;
step four: as shown in fig. 4, completing a second passivation of the chip surface on the wafer, and forming a second passivation layer 4, wherein a third window 03 is disposed in the second passivation layer 4 above the second transition metal 10 in the first window 01, and a fourth window 04 is disposed in the second passivation layer 4 above the second transition metal 10 in the second window 02, wherein a distance between the first window 01 and the second window 02 is smaller than a distance between the third window 03 and the fourth window 04;
step five: as shown in fig. 5, after the wafer is diced, the chip is soldered on the metal plate 6 by the first solder 5;
step six: as shown in fig. 6, a second solder 7 is formed in the third window 03 and the fourth window 04;
step seven: as shown in fig. 7, the first sheet metal electrode 8 is soldered to the third window 03 by the second solder 7, and the second sheet metal electrode 9 is soldered to the fourth window 04 by the second solder 7.
The utility model provides a special surface metallization middle and high power semiconductor device, which obviously increases the thickness of the chip through two times of passivation, provides strong support for the chip, and ensures that the ultra-thin wafer is not easy to damage; the first window 01 and the third window 03, and the second window 02 and the fourth window 04 may partially overlap, so that when the chip area is small, the distance between the third window 03 and the fourth window 04 on the second passivation layer 4 is increased, and the second solders 7 in the two windows are prevented from being bonded, thereby causing the device failure; by arranging the first transition metal 3 and the second transition metal 10, the device can obtain lower packaging resistance, parasitic inductance and thermal resistance; the manufacturing process is compatible with the existing process.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments, and although the present invention has been disclosed with the preferred embodiments, it is not limited to the present invention, and any skilled person in the art can make some modifications or equivalent embodiments without departing from the scope of the present invention, but all the technical matters of the present invention are within the scope of the present invention.

Claims (6)

1. A medium and high power semiconductor device with special surface metallization comprises a metal disc (6), wherein a first solder (5) is arranged on the metal disc (6), a semiconductor power chip (1) is arranged above the first solder (5), a first passivation layer (2) is arranged on the surface of the semiconductor power chip (1), a first window (01) and a second window (02) are arranged on the first passivation layer (2), the medium and high power semiconductor device is characterized in that a first transition metal (3) is arranged in each of the first window (01) and the second window (02), a second transition metal (10) is arranged on the surface of the first transition metal (3), a second passivation layer (4) is arranged on the surfaces of the second transition metal (10) and the first passivation layer (2), and a third window (03) is arranged in the second passivation layer (4) above the second transition metal (10) in the first window (01), a fourth window (04) is arranged in the second passivation layer (4) above the second transition metal (10) in the second window (02), second solders (7) are arranged in the third window (03) and the fourth window (04), first metal sheet electrodes (8) are arranged above the second solders (7) in the third window (03), and second metal sheet electrodes (9) are arranged above the second solders (7) in the fourth window (04).
2. A semiconductor device with special surface metallization according to claim 1, characterized in that the second solder (7) in the third window (03) is in contact with the second transition metal (10) in the first window (01), and the second solder (7) in the fourth window (04) is in contact with the second transition metal (10) in the second window (02); the third window (03) completely or partially overlaps the boundary of the first window (01), and the fourth window (04) completely or partially overlaps the boundary of the second window (02).
3. A semiconductor device with special surface metallization according to claim 1, characterized in that the first passivation layer (2) and the second passivation layer (4) are both formed by insulating dielectric layers.
4. A semiconductor device with special surface metallization according to claim 1, characterized in that the second transition metal (10), the first sheet metal electrode (8) and the second sheet metal electrode (9) are made of copper, silver or gold.
5. A semiconductor device with special surface metallization as claimed in claim 1, characterized in that said first transition metal (3) is composed of a single metal or a composite metal.
6. A medium to high power semiconductor device with special surface metallization as claimed in claim 5, characterized in that said first transition metal (3) is tungsten or nickel-gold.
CN202021037161.5U 2020-06-08 2020-06-08 Medium-high power semiconductor device with special surface metallization Active CN212033003U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202021037161.5U CN212033003U (en) 2020-06-08 2020-06-08 Medium-high power semiconductor device with special surface metallization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202021037161.5U CN212033003U (en) 2020-06-08 2020-06-08 Medium-high power semiconductor device with special surface metallization

Publications (1)

Publication Number Publication Date
CN212033003U true CN212033003U (en) 2020-11-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202021037161.5U Active CN212033003U (en) 2020-06-08 2020-06-08 Medium-high power semiconductor device with special surface metallization

Country Status (1)

Country Link
CN (1) CN212033003U (en)

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