CN211980620U - JBS two-stage tube device structure with ladder-shaped structure - Google Patents
JBS two-stage tube device structure with ladder-shaped structure Download PDFInfo
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- CN211980620U CN211980620U CN202021025068.2U CN202021025068U CN211980620U CN 211980620 U CN211980620 U CN 211980620U CN 202021025068 U CN202021025068 U CN 202021025068U CN 211980620 U CN211980620 U CN 211980620U
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Abstract
The utility model relates to a JBS two-stage tube part structure with stairstepping structure, establish first conductivity type epitaxial layer on first conductivity type heavily doped substrate, establish the second conductivity type district that is stairstepping structure in first conductivity type epitaxial layer upper surface, the width in second conductivity type district is from up being successive layer increase setting down, upper surface in first conductivity type epitaxial layer and second conductivity type district is equipped with oxide layer and schottky metal layer, left end bonding interface below and right-hand member bonding interface below at schottky metal layer and oxide layer all are equipped with a second conductivity type district, both ends bonding interface still are equipped with a second conductivity type district at least about schottky metal layer and oxide layer between, lower surface at the substrate is equipped with the ohm metal level. The utility model discloses leakage current, the anti surge ability of reinforcing when can reach improvement device withstand voltage ability, reduce reverse bias voltage, further optimize the reliability of device.
Description
Technical Field
The utility model belongs to the technical field of two-stage tube device technique and specifically relates to a JBS (junction barrier schottky) two-stage tube device structure with stairstepping structure.
Background
The silicon carbide compound in the third generation wide bandgap semiconductor material field is very suitable for the market application of high-voltage and high-power devices due to the unique characteristics of high pressure resistance, high temperature resistance and high heat conductivity coefficient. After the first 600V silicon carbide Schottky Diode SBD (Schottky Barrier Diode ) was commercialized in 2001, the excellent electrical parameter characteristics of the silicon carbide Schottky Diode have brought a brand new terminal application to the fields of power factor improvement (power factor correction), photovoltaic inverters, ac-to-dc power conversion circuits, new energy automobiles, and the like. However, the first generation of planar sic schottky diode has two main problems, the first problem is that the surface electric field intensity of the sic schottky diode is about 8 to 10 times of that of the silicon device, and when operating at high temperature reverse bias voltage, the tunnel (tunneling) effect and the nano-hole (nano-pit) defect between the schottky metal layer and the sic contact surface can enlarge the leakage current, which causes the doubtful concern to the device reliability; the second problem is that the surge resistance of the first generation of planar silicon carbide schottky diode is far smaller than that of the schottky diode made of silicon-based material because the chip area is only 1/3 of silicon-based devices with the same specification, which brings much trouble to the application of large current and high power.
Disclosure of Invention
The utility model aims at overcoming the not enough of existence among the prior art, provide a can reduce surface electric field intensity, reduce leakage current and improve the schottky two-stage tube device structure of anti surge ability.
According to the technical scheme provided by the utility model, the JBS two-stage tube device structure with the step-shaped structure comprises a planar Schottky metal region and an oxide layer protection region, wherein the planar Schottky metal region is positioned in the central region of the device; the planar Schottky metal region comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped substrate and a first conductive type epitaxial layer positioned on the upper surface of the first conductive type heavily doped substrate, second conductive type body regions in a step-shaped structure are arranged in the upper surface of the first conductive type epitaxial layer, the width of each second conductive type body region is increased layer by layer from bottom to top, each second conductive type body region is made of a second conductive type material, an oxidation layer and a Schottky metal layer are arranged on the upper surfaces of the first conductive type epitaxial layer and the second conductive type body regions, the oxidation layer surrounds the Schottky metal layer, the second conductive type body regions are arranged below the left end combination interface and the right end combination interface of the Schottky metal layer and the oxidation layer, and at least one second conductive type body region is arranged between the left end combination interface and the right end combination interface of the Schottky metal layer and the oxidation layer, an ohmic metal layer is arranged on the lower surface of the first conductive type heavily doped substrate; the Schottky metal layer is used as an anode of the device, and the ohmic metal layer is used as a cathode of the device.
Preferably, the first conductive type heavily doped substrate and the first conductive type epitaxial layer are of N-type conductivity, and the second conductive type body region and the second conductive type material are of P-type conductivity.
Preferably, the schottky metal layer is planar and has a thickness of 100-1000 a.
Preferably, the oxide layer is located around the chip, and surrounds and protects the first conductivity type epitaxial layer and the schottky metal layer located in the middle of the device.
Preferably, the second conductivity type body regions located at the leftmost and rightmost sides serve as terminal outer rings of the protection device.
Preferably, the first conductive type heavily doped substrate and the first conductive type epitaxial layer are both made of silicon carbide.
Preferably, the thickness of the schottky metal layer is smaller than that of the oxide layer.
Preferably, the material of the ohmic metal layer is Ti/Ni/Ag alloy or Ti/Ni/Al alloy.
The utility model discloses utilize a plurality of stairstepping structures's second conductivity type body region effectively to adjust the surface electric field intensity of optimizing dispersion plane schottky two-stage tube spare, can reach and improve device withstand voltage ability, leakage current when reducing reverse bias voltage, the anti surge ability of reinforcing further optimizes the reliability of device.
Drawings
Fig. 1 is a schematic structural diagram of a first conductivity type heavily doped substrate and a first conductivity type epitaxial layer provided in step one of embodiment 1 of the present invention.
Fig. 2 is a schematic structural diagram of the embodiment 1 of the present invention after the second step.
Fig. 3 is a schematic structural diagram of the embodiment 1 of the present invention after the third step.
Fig. 4 is a schematic structural diagram after the processing of step four in embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram after the fifth step of the embodiment 1 of the present invention.
Fig. 6 is a schematic structural diagram after the sixth step of the embodiment 1 of the present invention.
Fig. 7 is a schematic structural diagram after the processing of step seven in embodiment 1 of the present invention.
Fig. 8 is a schematic structural diagram after processing in step eight in embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional view of a conventional planar silicon carbide JBS diode.
Detailed Description
The present invention will be further described with reference to the following specific embodiments.
Example 1
A JBS two-stage tube device structure with a step-shaped structure comprises a planar Schottky metal region and an oxide layer protection region, wherein the planar Schottky metal region is positioned in the central region of the device; the planar Schottky metal region comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped substrate 1 and a first conductive type epitaxial layer 2 located on the upper surface of the first conductive type heavily doped substrate 1, a second conductive type body region 3 in a step-shaped structure is arranged in the upper surface of the first conductive type epitaxial layer 2, the width of the second conductive type body region 3 is increased layer by layer from bottom to top, each second conductive type body region 3 is formed by a second conductive type material 4, an oxidation layer 5 and a Schottky metal layer 6 are arranged on the upper surfaces of the first conductive type epitaxial layer 2 and the second conductive type body region 3, the oxidation layer 5 surrounds the Schottky metal layer 6, one second conductive type body region 3 is arranged below a left end combination interface and one second conductive type body region 3 are arranged below a right end combination interface of the Schottky metal layer 6 and the oxidation layer 5, and three second conductive type body regions are further arranged between the left end combination interface and the right end combination interface of the Schottky metal layer 6 and the oxidation layer 5 The body region 3 is provided with an ohmic metal layer 7 on the lower surface of the first conductive type heavily doped substrate 1; the schottky metal layer 6 serves as an anode of the device and the ohmic metal layer 7 serves as a cathode of the device.
The first conductive type heavily doped substrate 1 and the first conductive type epitaxial layer 2 are of N-type conductivity, and the second conductive type body region 3 and the second conductive type material 4 are of P-type conductivity.
The schottky metal layer 6 is planar, and the thickness of the schottky metal layer 6 is 100-.
The oxide layer 5 is located around the chip, surrounding and protecting the first conductivity type epitaxial layer 2 and the schottky metal layer 6 located in the middle of the device.
The second conductivity type body regions 3 located leftmost and rightmost serve as terminal outer rings of the protection device.
The first conductive type heavily doped substrate 1 and the first conductive type epitaxial layer 2 are both made of silicon carbide.
The number, height and width of steps in the second conductive type body region 3 of the ladder type structure can be designed with different multivariable dimensions according to the requirement of device voltage resistance, and the second conductive type body regions 3 positioned at the leftmost side and the rightmost side are also used as terminal outer rings of the protection device at the same time.
The thickness of the Schottky metal layer 6 is smaller than that of the oxide layer 5.
The ohmic metal layer 7 is made of Ti/Ni/Ag alloy or Ti/Ni/Al alloy.
A method for manufacturing a JBS two-stage tube device structure with a ladder-shaped structure comprises the following steps:
providing a first conductive type heavily doped substrate 1 made of N-type silicon carbide, growing a first conductive type epitaxial layer 2 made of N-type silicon carbide on the first conductive type heavily doped substrate 1, wherein the upper surface of the first conductive type epitaxial layer 2 is a first main surface, and the lower surface of the first conductive type heavily doped substrate 1 is a second main surface;
performing boron or aluminum ion implantation on the first main surface for the first time to form a plurality of first P + type second conductive type body regions 3 in the first conductive type epitaxial layer 2 by adopting a high-temperature high-energy ion implantation device through shielding of a patterned photoetching plate designed by the device, and removing a surface oxide layer by adopting wet etching or hot HF after the implantation is finished;
implanting boron or aluminum ions into a P + type second conductive type material 4 for the second time on the first main surface by adopting a high-temperature high-energy ion implantation device through shielding of a graphical photoetching plate designed by the device, wherein the depth of the second implantation is smaller than that of the first implantation, the width of the second implantation is larger than that of the first implantation, a second conductive type body region 3 of a second layer is formed in the first conductive type epitaxial layer 2, and a surface oxide layer is removed by adopting wet etching or hot HF after the implantation is finished;
implanting boron or aluminum ions into a P + type second conductive type material 4 for the third time on the first main surface by adopting a high-temperature high-energy ion implantation device through shielding of a patterned photoetching plate designed by a device, wherein the depth of the third implantation is smaller than that of the second implantation, the width of the third implantation is larger than that of the second implantation, forming a third layer of second conductive type body area 3 in the first conductive type epitaxial layer 2, so that the second conductive type body area 3 with a stepped structure is formed after the P + type second conductive type material 4 is implanted by the boron or aluminum ions for the third time, the width of the second conductive type body area 3 is increased layer by layer from bottom to top, wet etching or hot HF surface oxide layer is removed after the implantation is finished, and then hot nitrogen is adopted to remove impurities remained on the surface;
growing an oxide layer 5 above the first conductive type epitaxial layer 2 made of N-type silicon carbide and the P + type second conductive type body region 3 by adopting a thermal oxidation process;
carrying out dry etching in the middle of the oxide layer 5 under the shielding of the graphical photoetching plate to form a middle Schottky metal region and an oxide layer protection region at the edge;
step seven, plating a layer of Schottky metal material in the Schottky metal area to form a Schottky metal layer 6;
and step eight, plating a layer of Ti/Ni/Ag alloy or Ti/Ni/Al alloy ohmic metal material with low resistance value on the second main surface to form an ohmic metal layer 7, wherein the ohmic metal layer 7 is used as a cathode of the device.
The utility model discloses a JBS (junction Barrier schottky) structural design pours into second conductivity type material 4 into in schottky metal level below, shifts the first conductivity type epitaxial layer 2 under the surface electric field, can reduce the leakage current problem of device when reverse bias voltage, but can't promote the anti surge current ability of device by a wide margin. The utility model discloses on the basis of current plane carborundum JBS two-stage pipe spare (as shown in figure 9), at the inside upper surface of first conductive type epitaxial layer 2, along plane schottky metal layer 6 and oxide layer 5's below, through multi-level hot ion implantation second conductive type epitaxial material 4, form the second conductive type somatic region 3 structure of a plurality of notch cuttype, make the device form P-N junction interface with first conductive type epitaxial layer 2 when the reverse bias voltage, simultaneously via the individual degree of depth and the width to the ladder quantity and each ladder of second conductive type somatic region 3), do multidimensional variable control, can effectively adjust and reduce the surface electric field intensity in the middle of first conductive type epitaxial layer 2 and schottky metal layer 6, reduce the leakage current of device under the reverse bias voltage; also can disperse surge current's distribution simultaneously, disperse the crowded effect of surge current (growing effect), improve the anti surge ability of carborundum JBS two-stage tube device by a wide margin, and promote the utility model discloses the reliable performance of device.
Claims (8)
1. A JBS two-stage tube device structure with a step-shaped structure comprises a planar Schottky metal region and an oxide layer protection region, wherein the planar Schottky metal region is positioned in the central region of the device; the planar Schottky metal region comprises a semiconductor substrate, the semiconductor substrate comprises a first conduction type heavily doped substrate (1) and a first conduction type epitaxial layer (2) located on the upper surface of the first conduction type heavily doped substrate (1), and the planar Schottky metal region is characterized in that: a second conductive type body area (3) with a step-shaped structure is arranged in the upper surface of the first conductive type epitaxial layer (2), the width of the second conductive type body area (3) is gradually increased from bottom to top, each second conductive type body area (3) is formed by a second conductive type material (4), an oxide layer (5) and a Schottky metal layer (6) are arranged on the upper surfaces of the first conductive type epitaxial layer (2) and the second conductive type body area (3), the oxide layer (5) surrounds the Schottky metal layer (6), the second conductive type body area (3) is arranged below the left end combination interface and the right end combination interface of the Schottky metal layer (6) and the oxide layer (5), at least one second conductive type body area (3) is arranged between the left end combination interface and the right end combination interface of the Schottky metal layer (6) and the oxide layer (5), an ohmic metal layer (7) is arranged on the lower surface of the first conduction type heavily doped substrate (1); the Schottky metal layer (6) is used as an anode of the device, and the ohmic metal layer (7) is used as a cathode of the device.
2. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the first conductive type heavily doped substrate (1) and the first conductive type epitaxial layer (2) are N-type conductive, and the second conductive type body region (3) and the second conductive type material (4) are P-type conductive materials.
3. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the Schottky metal layer (6) is planar, and the thickness of the Schottky metal layer (6) is 100-1000A.
4. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the oxide layer (5) is located around the chip, and surrounds and protects the first conductivity type epitaxial layer (2) and the Schottky metal layer (6) located in the middle of the device.
5. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the second conductivity type body regions (3) located leftmost and rightmost serve as terminal outer rings of the protection device.
6. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the first conductive type heavily doped substrate (1) and the first conductive type epitaxial layer (2) are both made of silicon carbide.
7. The JBS two-stage device structure with the stepped structure as claimed in claim 1 or 3, wherein: the thickness of the Schottky metal layer (6) is smaller than that of the oxide layer (5).
8. The JBS two-stage device structure with a stepped structure of claim 1, wherein: the ohmic metal layer (7) is made of Ti/Ni/Ag alloy or Ti/Ni/Al alloy.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021025068.2U CN211980620U (en) | 2020-06-05 | 2020-06-05 | JBS two-stage tube device structure with ladder-shaped structure |
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| CN202021025068.2U CN211980620U (en) | 2020-06-05 | 2020-06-05 | JBS two-stage tube device structure with ladder-shaped structure |
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| CN211980620U true CN211980620U (en) | 2020-11-20 |
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Effective date of registration: 20230918 Address after: Unit 802E, No. 155 Taidong Road, Siming District, Xiamen City, Fujian Province, 361000 Patentee after: Xiamen Xinheda Investment Co.,Ltd. Address before: 215612 2nd floor, building e, Fenghuang science and Technology Pioneer Park, Fenghuang Town, Zhangjiagang City, Suzhou City, Jiangsu Province Patentee before: SUZHOU FENGHUANGXIN ELECTRONIC TECHNOLOGY CO.,LTD. |