CN211908361U - Input surge protection circuit with bolt-lock control - Google Patents
Input surge protection circuit with bolt-lock control Download PDFInfo
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- CN211908361U CN211908361U CN202020885578.0U CN202020885578U CN211908361U CN 211908361 U CN211908361 U CN 211908361U CN 202020885578 U CN202020885578 U CN 202020885578U CN 211908361 U CN211908361 U CN 211908361U
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Abstract
The utility model discloses a take bolt-lock controlled input surge protection circuit, including MOS pipe Q1, triode Q2, diode D1 and MOS pipe Q3, MOS pipe Q1's source connecting resistance R3, NTC device NTC1, triode Q2's projecting pole, resistance R1, diode D1's positive pole and input voltage DCin, diode D1's positive pole is connected to resistance R3's the other end, MOS pipe Q1's grid, resistance R4 and triode Q2's collecting electrode, triode Q2's base connecting resistance R1's the other end and resistance R2, diode Z2's negative pole is connected to resistance R2's the other end, NTC device 1's the other end, MOS pipe Q1's drain electrode and output voltage, the utility model discloses a bolt-lock increases, delays electric capacity, has guaranteed that first switch on power and during operation fast switching power supply all can guarantee to current limiting's stability, has promoted the Vin 3 5 of circuit.
Description
Technical Field
The utility model relates to a protection circuit technical field specifically is an input surge protection circuit of bolt-lock control in area.
Background
When the load characteristic of the equipment is capacitive (for example, a large amount of large capacitance exists on the input side or the load is similar to a PTC device), if the power supply is input, because the capacitive load is approximately short-circuited, an extremely large input surge current (which is dozens of times of a normal operating current) can be generated. If the inrush current is not limited, permanent damage may be done to the devices on the input path.
The traditional surge protection is to protect the circuit by connecting a high-power NTC in series at the input front stage and utilizing the negative temperature characteristic of the NTC. Under normal conditions, the normal temperature resistance of the NTC is relatively large, when a circuit is switched on, the input current on the circuit is inhibited due to the existence of the NTC, the temperature of the NTC begins to rise along with the continuous conduction of the current, the resistance becomes small, the voltage drop at two ends is reduced, and the input voltage is basically loaded on a load. When the NTC current power consumption and heat dissipation reach thermal balance, the circuit is in stable working state, thereby realizing the purpose of inhibiting surge current.
The problems with the above circuit:
1. because the single NTC circuit works, the NTC is always in a power-on state and works at high temperature, the circuit has the problems of serious heat generation and easy failure of devices. Meanwhile, the NTC device is often in a short-circuit state when in failure, and the surge function is lost.
2. When the circuit is turned off after operation and turned on again in a short time, the resistance is still small because the NTC temperature during the turn-off period does not fall to the ambient temperature in time, and the effect of limiting the current is lost after the circuit is turned on again.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a take bolt-lock control's input surge protection circuit to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
an input surge protection circuit with bolt-lock control comprises a MOS tube Q1, a triode Q2, a diode D1 and a MOS tube Q3, the source of the MOS transistor Q1 is connected to the resistor R3, the NTC device NTC1, the emitter of the transistor Q2, the resistor R1, the anode of the diode D1, and the input voltage DCin, the other end of the resistor R3 is connected to the anode of the diode D1, the gate of the MOS transistor Q1, the resistor R4, and the collector of the transistor Q4, the base of the transistor Q4 is connected to the other end of the resistor R4 and the resistor R4, the other end of the resistor R4 is connected to the cathode of the diode Z4, the other end of the NTC device NTC 4, the drain of the MOS transistor Q4 and the output voltage Vin, the anode of the diode D4 is connected to the gate of the MOS transistor Q4, the resistor R4, and the capacitor C4, the source of the MOS transistor Q4 is connected to the other end of the resistor R4, the other end of the capacitor C4 and the ground.
As a further technical solution of the present invention: the MOS tube Q1 is an N-type MOS tube.
As a further technical solution of the present invention: the triode Q2 is a PNP triode.
As a further technical solution of the present invention: the MOS tube Q3 is a P-type MOS tube.
As a further technical solution of the present invention: the diode Z3 is a zener diode.
Compared with the prior art, the beneficial effects of the utility model are that: 1. the PMOSFET and the NTC are added to be connected in parallel, and a control circuit is added after being started. And when the voltage of the NTC output side is gradually increased, the PMOSFET is switched on to short-circuit the NTC. The NTC can limit current after being electrified, no current flows any more after the output voltage is stable, and the phenomenon that the current flows through the NTC all the time to generate heat when the surge protection circuit of the single NTC works is avoided.
2. Meanwhile, as the NTC does not flow current in the working period, the resistance is gradually recovered to the normal temperature resistance, and thus when the input is disconnected and the resistance of the NTC is started for a short time, the resistance of the NTC is recovered to be normal, the current can be limited again, and the phenomenon that the single NTC circuit fast switch loses the current limiting effect is avoided.
3. By adding the bolt-lock circuit and the slow-start capacitor, the stability of limiting surge current can be ensured by switching on the power supply for the first time and rapidly switching the power supply during working, and the robustness of the circuit is improved.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, embodiment 1: an input surge protection circuit with bolt-lock control comprises a MOS tube Q1, a triode Q2, a diode D1 and a MOS tube Q3, the source of the MOS transistor Q1 is connected to the resistor R3, the NTC device NTC1, the emitter of the transistor Q2, the resistor R1, the anode of the diode D1, and the input voltage DCin, the other end of the resistor R3 is connected to the anode of the diode D1, the gate of the MOS transistor Q1, the resistor R4, and the collector of the transistor Q4, the base of the transistor Q4 is connected to the other end of the resistor R4 and the resistor R4, the other end of the resistor R4 is connected to the cathode of the diode Z4, the other end of the NTC device NTC 4, the drain of the MOS transistor Q4 and the output voltage Vin, the anode of the diode D4 is connected to the gate of the MOS transistor Q4, the resistor R4, and the capacitor C4, the source of the MOS transistor Q4 is connected to the other end of the resistor R4, the other end of the capacitor C4 and the ground.
As shown in fig. 1, the present design adds a PMOSFET in parallel with the NTC and corresponding turn-on and turn-off control circuit, latch circuit ((r) in the figure), and protection circuit ((r) in the figure). DCin in the figure is the input voltage and is connected to the NTC1 input. NTC1 is an NTC device, and Vin is the output (input of the following stage) after surge current suppression is added. The MOS transistor Q1 is a PMOSFET connected in parallel with the NTC, and the G pole of the PMOSFET is connected between the voltage dividing resistor R3 and the resistor R4 at the point A and is also the voltage at the point C. The MOS transistor Q3 has a D electrode connected to the lower end of the resistor R4, an S electrode connected to GND, and a G electrode connected to the upper end of the resistor R6. Z3 is a voltage stabilizing diode, connected to the output of NTC (D pole of MOS tube Q1), a resistor R5, a resistor R6 are bias resistors and voltage dividing resistors, connected to the anode of Z3, the upper end of a resistor R6 is connected to the G pole of MOS tube Q3, and the on and off of MOS tube Q3 are controlled.
In order to increase the stability and reliability of the system, a latch control circuit is optionally added on the basis of the circuit, as shown in the block (r). The transistor Q2 is a P-type transistor, the E-pole is connected to the input voltage DCin, and the C-pole is connected to the G-pole of the MOS transistor Q1. The resistor R1 and the resistor R2 are voltage dividing resistors, the B pole of the triode Q2 is connected between the resistor R1 and the resistor R2, and the lower end of the resistor R2 is connected to Vin (output of the NTC).
In order to ensure the G pole safety of the MOS transistor Q3 and prevent the over-high voltage, a D2 is added as a protection device, as shown in a box II.
In order to make the Vin voltage fluctuate, causing the MOS transistor Q3 to be frequently in on and off states, a capacitor C1 is connected in parallel to the resistor R6, as shown in block C.
When the DCin is electrified, the load capacitor is empty and is in a short-circuit state, the voltage at Vin is low, the Z3 is in a cut-off state, the voltage of the G electrode of the MOS transistor Q3 is 0 and is in a cut-off state, and the voltage at the point C is equal to the voltage at the point a, so that the MOS transistor Q1 is in a cut-off state. All current flows from NTC1, so the current flowing through NTC1 is small due to the large normal resistance of NTC1 and charges the load capacitance. As the load capacitor voltage increases, the NTC1 temperature increases, the resistance decreases, and the voltage at point B gradually increases. When the voltage at the point B rises above the regulated voltage of Z3, Z3 breaks down and is in a regulated state, and the voltage at the two ends does not rise any more. When the voltage at the point B continues to rise, so that the voltage at the upper segment of the resistor R6 rises, and the capacitor C1 is charged, the voltage at the upper end of the resistor R6 starts to slowly and stably rise. When the voltage reaches the turn-on voltage of the MOS transistor Q3, the MOS transistor Q3 is turned on, the D-pole is connected to GND, the upper end voltage of the resistor R4 is lowered, the MOS transistor Q1 is turned on, the NTC is short-circuited, and the current flows through the MOS transistor Q1. After the NTC1 is short-circuited, no current flows any more, the temperature is reduced, the resistance is gradually increased, and the normal resistance is recovered until the next DCin reloading.
In the process that the voltage at the point B gradually rises from low, because the voltage at the point B is lower than the voltage at the point A, the voltage at the point B of the triode Q2 is lower than the voltage at the point E, the triode Q2 is in an on state, the voltage (voltage at the point C) of the G of the MOS tube Q1 is locked to be approximate to the voltage at the point A, so that the Q is always in an off state in the process that the voltage at the point B rises until the voltage at the point B rises to be lower than the voltage at the point A, and when the voltage at the point B is about 0.5V, the triode Q2 is turned off, the voltage at the point C is unlocked. Therefore, the bolt-lock function of the MOS tube Q1 is realized, the MOS tube Q1 is switched on when the A, B voltage is close to the voltage, a fixed starting condition is realized, the MOS tube Q1 is prevented from being switched on by the low voltage of the point B caused by the failure of the Z3, and the surge current is generated.
When the input is disconnected after a period of operation and is switched on again in a short time, because the voltage at the point B in the figure has already dropped a little, and because of the existence of the latch circuit, the MOS tube Q1 is in the cut-off state immediately after DCin is disconnected, even if the MOS tube Q3 is turned on, the MOS tube Q1 cannot be turned on. The current flows through NTC1 again until the voltage rises at point B, and finally the MOS transistor Q1 is turned on. Therefore, even if the switch is quickly switched off during working, surge current can not be generated, and the reliability of surge protection is ensured.
In embodiment 2, the MOS transistor Q1 is an N-type MOS transistor in addition to embodiment 1. The transistor Q2 is a PNP transistor. The MOS transistor Q3 is a P-type MOS transistor. Diode Z3 is a zener diode.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (5)
1. An input surge protection circuit with latch control comprises a MOS tube Q1, a triode Q2, a diode D1 and a MOS tube Q3, wherein the source of the MOS tube Q3 is connected with a resistor R3, an NTC device NTC 3, the emitter of the triode Q3, the resistor R3, the anode of the diode D3 and an input voltage DCin, the other end of the resistor R3 is connected with the anode of the diode D3, the gate of the MOS tube Q3, the resistor R3 and the collector of the triode Q3, the base of the triode Q3 is connected with the other end of the resistor R3 and the resistor R3, the other end of the resistor R3 is connected with the cathode of the diode Z3, the other end of the NTC device NTC 3, the drain of the MOS tube Q3 and the output voltage, the anode of the diode D3 is connected with the gate of the MOS tube Q3, the resistor R3 and the anode of the capacitor C3, the other end of the diode Z3 is connected with the ground, and the anode of the diode Z3, the drain of the MOS transistor Q3 is connected to the other end of the resistor R4.
2. The input surge protection circuit with latch control according to claim 1, wherein the MOS transistor Q1 is an N-type MOS transistor.
3. The input surge protection circuit with latch control according to claim 1, wherein said transistor Q2 is a PNP transistor.
4. The input surge protection circuit with latch control according to claim 1, wherein the MOS transistor Q3 is a P-type MOS transistor.
5. The input surge protection circuit with latch control according to any of claims 1-4, wherein said diode Z3 is a zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020885578.0U CN211908361U (en) | 2020-05-22 | 2020-05-22 | Input surge protection circuit with bolt-lock control |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020885578.0U CN211908361U (en) | 2020-05-22 | 2020-05-22 | Input surge protection circuit with bolt-lock control |
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| CN211908361U true CN211908361U (en) | 2020-11-10 |
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| CN202020885578.0U Active CN211908361U (en) | 2020-05-22 | 2020-05-22 | Input surge protection circuit with bolt-lock control |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769321A (en) * | 2020-11-14 | 2021-05-07 | 东莞市盈聚电源有限公司 | Novel high-power switching power supply surge current suppression circuit |
| CN114204533A (en) * | 2021-12-17 | 2022-03-18 | 成都新欣神风电子科技有限公司 | High-reliability impact current suppression circuit |
-
2020
- 2020-05-22 CN CN202020885578.0U patent/CN211908361U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769321A (en) * | 2020-11-14 | 2021-05-07 | 东莞市盈聚电源有限公司 | Novel high-power switching power supply surge current suppression circuit |
| CN114204533A (en) * | 2021-12-17 | 2022-03-18 | 成都新欣神风电子科技有限公司 | High-reliability impact current suppression circuit |
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