CN211858587U - Ultra-thin chip structure - Google Patents
Ultra-thin chip structure Download PDFInfo
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- CN211858587U CN211858587U CN202020837237.6U CN202020837237U CN211858587U CN 211858587 U CN211858587 U CN 211858587U CN 202020837237 U CN202020837237 U CN 202020837237U CN 211858587 U CN211858587 U CN 211858587U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Manufacturing Of Printed Wiring (AREA)
Abstract
The utility model relates to an ultra-thin chip structure, which comprises a circuit layer, an ink layer and a chip, wherein the chip is connected with the top of the circuit layer, the ink layer is embedded in the circuit layer, the ink layer comprises an embedded part and a top layer part, wherein, the top layer part is fixedly connected with the top of the embedded part, the top layer part is provided with an opening, the circuit layer is arranged under the opening, the embedded part is embedded in the circuit layer, the circuit layer comprises a plurality of circuits, the embedded part is arranged between any two adjacent circuits, the top layer part is pressed on the top of the circuits, the top part of the circuit layer is respectively provided with a nickel layer and a gold layer, the nickel layer and the gold layer are arranged in the opening, wherein, the nickel layer is arranged on the top of the circuit layer, the gold layer is arranged on the top of the nickel layer, the top of the gold layer is arranged on the top of the nickel layer, and the, the top of the chip is packaged in a black glue layer, and the chip is covered on the top of the circuit layer by the black glue layer.
Description
Technical Field
The utility model relates to a chip architecture especially indicates a structure of ultra-thin chip.
Background
In the information age of today, with the rapid development of electronic industry, products such as computers, mobile phones, etc. are increasingly popularized. People have more and more requirements on functions and more strong requirements on performance of electronic products, which promotes the development of the electronic products towards multifunction, high performance, miniaturization and light weight. To achieve this goal, IC chips are becoming smaller in feature size and increasingly complex, and ultra-thin package substrate technology is becoming more popular to meet this development requirement. And the technology is still developing towards fine pitch, high end count. However, the current substrate packaging method and structure cannot accommodate ultra-thin and small-sized packages, which is a major drawback of the conventional technology.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical scheme who adopts does: an ultra-thin chip structure comprises a circuit layer, an ink layer and a chip, wherein the chip is connected to the top of the circuit layer, the ink layer is embedded in the circuit layer and comprises an embedded part and a top layer part, wherein the top layer part is fixedly connected to the top of the embedded part, the top layer part is provided with an opening, the circuit layer is positioned under the opening, the embedded part is embedded in the circuit layer, the circuit layer comprises a plurality of circuits, the embedded part is arranged between any two adjacent circuits, the top layer part is pressed on the top of the circuits, the top part of the circuit layer is respectively provided with a nickel layer and a gold layer, the nickel layer and the gold layer are positioned in the opening, the nickel layer is arranged on the top of the circuit layer, the gold layer is arranged on the top of the nickel layer, the top surface of the gold layer is flush with the top surface of the ink layer, and the top of the chip is packaged in a black adhesive layer, the black glue layer covers the chip on the top of the circuit layer.
An anti-oxidation layer is arranged at the bottom of the line layer and is arranged at the bottom of each line. The thickness of the nickel layer is 2.54-15um, and the thickness of the gold layer is 0.03-0.5 um. And a silver layer is arranged between the nickel layer and the gold layer.
The utility model has the advantages that: the utility model discloses a chip simple structure is reliable, utilizes its structure to be fit for making ultra-thin chip.
Drawings
Fig. 1 is a schematic diagram of the first step of the present invention.
Fig. 2 is a schematic diagram of the fourth step of the present invention.
Fig. 3 is a schematic diagram of the seventh step of the present invention.
Fig. 4 is a schematic diagram of the eighth step of the present invention.
Fig. 5 is a schematic diagram of the ninth step of the present invention.
Fig. 6 is a schematic diagram of the tenth step of the present invention.
Fig. 7 is a schematic diagram of the tenth step of the present invention.
Fig. 8 is a schematic diagram of the chip structure of the present invention.
Detailed Description
For convenience of understanding, the specific production and packaging method of the ultra-thin chip structure of the present invention will be described as follows.
As shown in fig. 1 to 7, the production packaging method of the present invention is for manufacturing. Which comprises the following steps.
As shown in fig. 1, the first step: a carrier substrate 10 is fabricated.
The carrier substrate 10 includes a substrate layer 11, a copper-clad layer 12 and a copper foil layer 13, wherein the copper-clad layer 12 is respectively disposed on the top surface and the bottom surface of the substrate layer 11, the copper foil layer 13 is disposed on the top surface of the copper-clad layer 12 on the substrate layer 11, when the carrier substrate is implemented specifically, the thickness of the copper-clad layer 12 is preferably 18um, and the thickness of the copper foil layer 13 is preferably 3 um.
In practical implementation, the carrier substrate 10 is fabricated as follows.
Step 1, the copper-clad layer 12 is respectively fixed on the top surface and the bottom surface of the substrate layer 11.
And 2, roughening the top surface of the copper-clad layer 12 on the top surface of the substrate layer 11 and the bottom surface of the copper foil layer 13, namely roughening the joint surface of the copper foil layer 13 and the copper-clad layer 12 to obtain a micro-rough structure on the copper surface and increase the roughness of the surface, so that the adhesive force between the copper surface and the copper foil is obviously improved, and a precondition is provided for pressing.
And 3, pressing the copper foil layer 13 on the top of the copper-clad layer 12 on the top surface of the substrate layer 11 by using a hot press, specifically, pressing the copper surfaces of the 3um copper foil and the 18um substrate together by using the high-temperature resin curing principle to obtain the carrier substrate 10.
The second step is that: and (3) carrying out high-temperature baking on the carrier plate substrate 10, controlling the temperature at 195 ℃ in the baking process, and continuing for 2H to remove the moisture on the surface of the carrier plate substrate 10, stabilize the size expansion and shrinkage of the carrier plate substrate 10, reduce the deformation of the carrier plate substrate 10 in the subsequent production, clearly marking the 3um copper foil surface by using a copper detector, and facilitating the subsequent drilling and direction division.
The third step: and mechanically drilling, specifically, drilling the 3um copper foil surface upwards, and detecting that the size of the drilled hole is qualified and numbering.
As shown in fig. 2, the fourth step: and (5) manufacturing a circuit to obtain a dry film layer cavity 15.
The method comprises the following specific steps.
Step 1, performing medium coarsening film pressing, and arranging a dry film layer 14 on the top of the copper foil layer 13, specifically describing that a chemical reaction of medium coarsening liquid medicine enables a microscopic rough structure to be created on the surface of the copper foil layer 13, so as to improve the binding force between a dry film and a copper surface, and a film pressing machine presses a photosensitive material (the dry film layer 14) on the copper foil layer 13.
And 2, line exposure, specifically, the line exposure is described as using the principle that a dry film has photosensitivity, transferring line film data to the dry film layer 14 by using an exposure machine, and performing positive exposure, positive word alignment and negative word exposure treatment on the semi-finished plate body by using the exposure machine.
And 3, developing, etching and removing the film, specifically, removing the unexposed dry film layer 14 by using a developer to obtain a dry film layer cavity 15, etching to remove redundant copper sheets, reserving the circuit pattern, pickling to clean the copper surface, and drying the surface to prevent the copper foil from being oxidized.
The fifth step: the line is detected, and specifically, the AOI machine detects the open short circuit of the line by using an optical principle.
And a sixth step: and (3) pickling and finishing the copper thickness of the copper foil layer 13, specifically, pickling before the plate is electrified to remove copper surface oxidation, and then electrically requiring the copper thickness of the copper foil layer 13 to enable the copper foil layer 13 to have conductivity.
As shown in fig. 3, the seventh step: electroplating and stripping the circuit, electroplating the circuit in the dry film layer cavity 15 to form a circuit layer 16, and stripping the dry film layer 14, wherein the circuit layer 16 is arranged on the top surface of the copper foil layer 13.
As shown in fig. 4, the eighth step: printing and developing an ink layer, printing the ink layer 17 on the top of the carrier substrate 10 in the seventh step, and developing the ink layer 17 to form a plurality of openings 173.
The bottom surface of the ink layer 17 is disposed on the top surface of the copper foil layer 13, and meanwhile, the ink layer 17 is embedded in the circuit layer 16, the ink layer 17 includes a buried portion 171 and a top layer portion 172, wherein the top layer portion 172 is fixedly connected to the top of the buried portion 171, the top layer portion 172 has an opening 173, and in practice, the opening 173 may be an opening, a hole, an open channel, or the like.
The circuit layer 16 is located right under the opening 173, and the embedded portion 171 is embedded in the circuit layer 16.
In one embodiment, the circuit layer 16 includes a plurality of circuits 161, the embedded portion 171 is disposed between any two adjacent circuits 161, and the top portion 172 is pressed on top of the circuits 161.
As shown in fig. 5, the ninth step: and plating a nickel-gold layer.
Electroplating a nickel layer 181 and a gold layer 182 on the top of the circuit layer 16 in the eighth step, wherein the nickel layer 181 and the gold layer 182 are in the opening 173, the nickel layer 181 is disposed on the top of the circuit layer 16, the gold layer 182 is disposed on the top of the nickel layer 181, and the top surface of the gold layer 182 is flush with the top surface of the ink layer 17.
The nickel-gold plating was performed as follows.
Firstly, the top surface of the circuit layer 16 is roughened by micro-etching, the top surface is activated by sulfuric acid washing to prevent the copper surface from being oxidized, then a layer of nickel is plated on the part needing to be plated with the nickel layer to provide reliability for bonding and welding, and finally a layer of gold is plated on the part needing to be plated with the gold layer for bonding or welding.
In specific implementation, the thickness of the nickel layer 181 is 2.54-15um, and the thickness of the gold layer 182 is 0.03-0.5 um.
In practice, the nickel layer may be a nickel-silver layer, the thickness of the silver layer is 0.5-2um, and the silver layer is located between the nickel layer 181 and the gold layer 182, so as to reduce the thickness of the precious metal and reduce the product cost.
In practice the thickness of the silver plating is preferably 1 μm.
The nickel plating solution of the utility model contains: 70-110 g/L of nickel sulfamate, 10-30 g/L of nickel chloride, 30-50 g/L of boric acid, 55-65 ℃ of nickel plating solution temperature and 3.8-4.4 of pH.
The utility model discloses direct plating one deck nickel layer replaces present copper layer on this circuit layer 16, even silver-plated layer thickness can not the high temperature change of colour at 0.1 ~ 0.3 mu m yet, when guaranteeing the performance requirement, has reduced the use of noble metal silver, has practiced thrift the cost, has solved present silver-plated layer thin then high temperature toasts the colour change, and the thick yield of silver layer is not high, problem with high costs.
In practice, after the ninth step, the forming machine can use the CAD data, and the milling cutter depth compensation can be used to mill the required size to obtain the desired size of the finished product and ensure the SET size requirement. And cleaning the surface of the molded product to obtain a final packaging substrate finished product.
As shown in fig. 6, the tenth step: and attaching a chip 20 on the top of the carrier substrate 10 in the ninth step, bonding and interconnecting, and packaging.
The concrete description is as follows: the carrier substrate 10 with the chip 20 attached thereon is placed in a customized mold, and the chip and the substrate are encapsulated together by glue filling of the black glue layer 21, thereby primarily completing the encapsulation of the BGA.
As shown in fig. 7, the eleventh step: and stripping the carrier substrate 10 to obtain a finished product, and cutting the finished product to obtain a finished chip.
In one embodiment, the eleventh step comprises the following steps.
Step 1, the substrate layer 11 and the copper clad layer 12 are stripped off at the same time, and the copper foil layer 13 is exposed.
And 2, micro-etching to strip the copper foil layer 13, specifically, etching the copper foil layer 13 by using a micro-etching method.
And step 3, performing anti-oxidation treatment on the bottom of the circuit layer 16 to form an anti-oxidation layer 162, specifically, the exposed circuit layer 16 is subjected to the OSP (anti-oxidation treatment) to facilitate subsequent tin coating on the circuit layer 16.
And 4, cutting the finished product into a plurality of chips to obtain the finished product chips.
As shown in fig. 8, an ultra-thin chip structure includes a circuit layer 16, an ink layer 17 and a chip 20, wherein the chip 20 is connected to the top of the circuit layer 16, and the ink layer 17 is embedded in the circuit layer 16.
The ink layer 17 includes a buried portion 171 and a top layer portion 172, wherein the top layer portion 172 is fixedly connected to the top of the buried portion 171, the top layer portion 172 has an opening 173, and in practice, the opening 173 may be an opening, a hole, an opening channel, or the like.
The circuit layer 16 is located right below the opening 173, the embedded portion 171 is embedded in the circuit layer 16, in an implementation, the circuit layer 16 includes a plurality of circuits 161, the embedded portion 171 is disposed between any two adjacent circuits 161, and the top portion 172 is pressed on top of the circuits 161.
The top of the circuit layer 16 is respectively provided with a nickel layer 181 and a gold layer 182, the nickel layer 181 and the gold layer 182 are located in the opening 173, wherein the nickel layer 181 is disposed on the top of the circuit layer 16, the gold layer 182 is disposed on the top of the nickel layer 181, and the top surface of the gold layer 182 is flush with the top surface of the ink layer 17.
The top of the chip 20 is encapsulated in a black glue layer 21, the chip 20 is covered on the top of the circuit layer 16 by the black glue layer 21, an oxidation preventing layer 162 is arranged at the bottom of the circuit layer 16, and the oxidation preventing layer 162 is arranged at the bottom of each circuit 161.
Claims (4)
1. An ultra-thin chip structure which characterized in that: which comprises a circuit layer, an ink layer and a chip, wherein the chip is connected with the top of the circuit layer, the ink layer is embedded in the circuit layer,
the ink layer comprises a buried part and a top layer part, wherein the top layer part is fixedly connected to the top of the buried part and is provided with an opening,
the circuit layer is positioned under the opening, the embedded part is embedded in the circuit layer, the circuit layer comprises a plurality of circuits, the embedded part is arranged between any two adjacent circuits, the top layer part is pressed on the top of the circuit,
the top of the circuit layer is respectively provided with a nickel layer and a gold layer, the nickel layer and the gold layer are positioned in the opening, wherein the nickel layer is arranged at the top of the circuit layer, the gold layer is arranged at the top of the nickel layer, the top surface of the gold layer is flush with the top surface of the ink layer,
the top of the chip is packaged in a black glue layer, and the chip is covered on the top of the circuit layer by the black glue layer.
2. The ultra-thin chip structure of claim 1, wherein: an anti-oxidation layer is arranged at the bottom of the line layer and is arranged at the bottom of each line.
3. The ultra-thin chip structure of claim 1, wherein: the thickness of the nickel layer is 2.54-15um, and the thickness of the gold layer is 0.03-0.5 um.
4. The ultra-thin chip structure of claim 1, wherein: and a silver layer is arranged between the nickel layer and the gold layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020837237.6U CN211858587U (en) | 2020-05-19 | 2020-05-19 | Ultra-thin chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020837237.6U CN211858587U (en) | 2020-05-19 | 2020-05-19 | Ultra-thin chip structure |
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| CN211858587U true CN211858587U (en) | 2020-11-03 |
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| CN202020837237.6U Active CN211858587U (en) | 2020-05-19 | 2020-05-19 | Ultra-thin chip structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477556A (en) * | 2020-05-19 | 2020-07-31 | 深圳市和美精艺科技有限公司 | Packaging method of ultrathin substrate and chip structure thereof |
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2020
- 2020-05-19 CN CN202020837237.6U patent/CN211858587U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477556A (en) * | 2020-05-19 | 2020-07-31 | 深圳市和美精艺科技有限公司 | Packaging method of ultrathin substrate and chip structure thereof |
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Address after: 2 / F, No.26, niumianling new village, sifangpu community, Pingdi street, Longgang District, Shenzhen, Guangdong 518000 Patentee after: Shenzhen Hemei Jingyi Semiconductor Technology Co.,Ltd. Address before: 2 / F, No.26, niumianling new village, sifangpu community, Pingdi street, Longgang District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN HEMEI JINGYI TECHNOLOGY Co.,Ltd. |