CN211828750U - Short circuit prevention lead frame, short circuit prevention structure and packaging structure - Google Patents
Short circuit prevention lead frame, short circuit prevention structure and packaging structure Download PDFInfo
- Publication number
- CN211828750U CN211828750U CN202020141605.3U CN202020141605U CN211828750U CN 211828750 U CN211828750 U CN 211828750U CN 202020141605 U CN202020141605 U CN 202020141605U CN 211828750 U CN211828750 U CN 211828750U
- Authority
- CN
- China
- Prior art keywords
- short
- glue overflow
- lead frame
- chip
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The application relates to the technical field of packaging, in particular to a short-circuit-preventing lead frame, a short-circuit-preventing structure and a packaging structure. The short-circuit prevention lead frame includes: the chip mounting structure comprises a carrier plate, wherein the carrier plate comprises a mounting area for mounting a chip, and at least one glue overflow groove is formed in the periphery of the mounting area on the carrier plate. The short-circuit prevention structure includes: the glue overflow device comprises a carrier plate, a glue tank and a glue tank, wherein the carrier plate comprises a mounting area, and at least one glue overflow groove is formed in the periphery of the mounting area; and the chip is attached in the attaching area of the carrier plate through a conductive adhesive layer. The application can effectively prevent the occurrence of short circuit problem caused by glue overflow between chips.
Description
Technical Field
The application relates to the technical field of packaging, in particular to a short-circuit-proof lead frame, a short-circuit-proof structure and a short-circuit-proof lead frame packaging structure.
Background
With the development of electronic technology, the semiconductor packaging industry has gradually developed various types of package structures to meet higher requirements (such as high-density, low-cost, and high-performance packages), and currently, quad flat non-leaded packages are commonly used in the market. Referring to fig. 1, the chips are electrically connected to the frame by leads, respectively, and the chip 23 is stacked on the chip 22, and electrodes of the chips are led out by the leads.
However, as shown in fig. 1, the lead frame of the related art is a planar structure, when a plurality of chips are required to be packaged together by a chip mounter, a short circuit may occur between two adjacent chips, because: when the chip is mounted on the lead frame, an adhesive layer is required to be formed on the lead frame, the adhesive layer is generally a conductive layer, such as Sn, and external force intervenes in the mounting process to cause the adhesive layer to overflow, and the two chips are short-circuited once the overflow adhesive layer is fused. In addition, sometimes to meet the high density and small size requirements, the distance between 2 or more of the plurality of chips on the plurality of lead frames is reduced, which is more likely to result in adhesive layer interconnections and ultimately failure of the packaged product.
Disclosure of Invention
In order to solve the deficiency that exists among the prior art, this application provides a prevent short circuit lead frame, prevent short circuit structure and prevent short circuit lead frame packaging structure, can effectively prevent to take place the appearance of short circuit problem because of overflowing gluing between the chip.
According to the technical scheme that this application provided, as the first aspect of this application, provide a prevent short circuit lead frame, prevent short circuit lead frame includes:
the chip mounting structure comprises a carrier plate, wherein the carrier plate comprises a mounting area for mounting a chip, and at least one glue overflow groove is formed in the periphery of the mounting area on the carrier plate.
Optionally, the glue overflow groove surrounds the periphery of the mounting area.
Optionally, the depth of the glue overflow groove is one third to five sixths of the thickness of the carrier plate.
Optionally, at least one flow blocking rib is arranged on the inner wall of the glue overflow groove.
Optionally, choked flow concave points are densely distributed on the inner wall of the glue overflow groove.
As a second aspect of the present application, there is provided a short-circuit prevention structure including:
the short-circuit prevention lead frame according to the first aspect of the present application, further comprising:
and the chip is attached in the attaching area of the carrier plate through a conductive adhesive layer.
Optionally, the glue overflow groove surrounds the periphery of the mounting area.
Optionally, the chip is connected to the pins by wires.
As a third aspect of the present application, there is provided a short-circuit prevention lead frame package structure, including a plastic package layer in which at least one pin is plastic-packaged, and the short-circuit prevention structure according to the second aspect of the present invention, the short-circuit prevention structure corresponding to the pin.
Optionally, a bonding pad covers a connection point of the chip, one end of the lead is connected to the bonding pad, and the other end of the lead is connected to the pin.
From the aforesaid can see, the short circuit prevention lead frame that this application provided, prevent short circuit structure and prevent short circuit lead frame packaging structure compares with prior art and possesses following advantage: when the chip is mounted in the mounting area, a layer of conductive adhesive layer is required to be coated between the chip and the mounting area, so that the chip and the carrier plate are coupled and connected. Once the coating dosage is improperly controlled, the conductive adhesive layer can flow and spread around. Through overflowing gluey groove at least one and can playing the effect of blockking to the extension from conductive adhesive layer, place because of conductive adhesive layer's further extension and with other chips or the conductive adhesive layer fusion of other chips and be connected, and then place the short circuit connection between the chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of the related art of the present application.
Fig. 2 is a schematic top view of the first aspect of the present application.
Fig. 3 is a schematic cross-sectional structure of a second aspect of the present application.
Fig. 4 is an enlarged structural schematic diagram of a portion a in fig. 3 corresponding to embodiment 5.
Fig. 5 is an enlarged structural diagram of a portion a in fig. 3 corresponding to embodiment 6.
Fig. 6 is a schematic structural diagram of a third aspect of the present invention.
100. The chip package structure comprises a carrier plate, 110 mounting areas, 120 glue overflow grooves, 121 flow-resisting convex ribs, 122 flow-resisting concave points, 200 chips, 210 bonding pads, 220 leads, 300 conductive glue layers, 400 plastic package layers and 500 pins.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
As a first aspect of the present application, referring to fig. 2, a short-circuit prevention lead frame is provided.
Example 1:
the short-circuit prevention lead frame comprises a carrier 100, wherein the carrier 100 comprises a mounting area 110 for mounting a chip 200, and at least one glue overflow groove 120 is formed in the periphery of the mounting area 110 on the carrier 100.
It should be noted that, in the miniaturized package structure, if the distance between the glue overflow groove 120 and the side edge of the mounting region 110 is too far, and the area of the bonding material is too large, short circuit may occur during wire bonding, so the distance between the glue overflow groove 120 and the side edge of the mounting region 110 is 100 to 1000 micrometers.
Since a conductive adhesive layer 300 is required to be coated between the chip 200 and the mounting region 110 when the chip 200 is mounted in the mounting region 110, the chip 200 and the carrier 100 are coupled. Once the coating dose is improperly controlled, the conductive adhesive layer 300 may flow around and spread. The at least one glue overflow groove 120 can play a role in blocking expansion of the conductive glue layer 300, and the conductive glue layer 300 is placed to be fused and connected with other chips 200 or the conductive glue layers 300 of other chips 200 due to further expansion of the conductive glue layer 300, so that short circuit connection among the chips 200 is placed.
The glue overflow groove 120 surrounds the periphery of the mounting area 110. The glue overflow groove 120 is a closed ring shape, and surrounds the periphery of the mounting area 110, so that the mounting area 110 can have a sufficient blocking effect, and the glue overflow at each position of the mounting area 110 can be placed.
The depth of the glue overflow groove 120 is one third to five sixths of the thickness of the carrier 100. Increasing the depth of the glue overflow groove 120 can improve the glue overflow blocking effect thereof to some extent.
Example 2:
in order to make the glue overflow groove 120 have a certain blocking effect on glue overflow, the glue overflow speed is controlled, and the glue overflow is prevented from leaking before solidification due to the excessively high glue overflow speed.
In this embodiment, on the basis of embodiment 1, at least one flow blocking rib 121 is disposed on the inner wall of the glue overflow slot 120, and the inner wall of the glue overflow slot 120 includes the bottom surface and at least one side surface of the side wall of the glue overflow slot 120.
Specifically, the short-circuit prevention lead frame comprises a carrier 100, the carrier 100 comprises a mounting area 110 for mounting a chip 200, and at least one glue overflow groove 120 is formed on the carrier 100 at the periphery of the mounting area 110. The inner wall of the glue overflow groove 120 is provided with at least one flow blocking convex rib 121.
It is understood that the flow blocking ribs 121 can block the glue overflow, so as to control the flow rate of the glue overflow.
Example 3
In order to make the glue overflow groove 120 have a certain blocking effect on glue overflow, the glue overflow speed is controlled, and the glue overflow is prevented from leaking before solidification due to the excessively high glue overflow speed.
In this embodiment, on the basis of embodiment 1, concave points are densely distributed on the inner wall of the glue overflow groove 120, and the inner wall of the glue overflow groove 120 includes at least one of the bottom surface and the side wall of the glue overflow groove 120.
Specifically, the short-circuit prevention lead frame comprises a carrier 100, the carrier 100 comprises a mounting area 110 for mounting a chip 200, and at least one glue overflow groove 120 is formed on the carrier 100 at the periphery of the mounting area 110. And flow-resisting concave points 122 are densely distributed on the inner wall of the glue overflow groove 120.
It is understood that the flow-blocking pits 122 can block the glue overflow, thereby reducing the flow rate of the glue overflow.
It should be noted that, in order to make the glue overflow groove 120 have a certain blocking effect on glue overflow, the glue overflow speed is controlled, and the glue overflow is prevented from leaking before solidification due to too high glue overflow speed. The first aspect of the present application may also adopt other alternatives besides the technical solutions of the above embodiments 2 and 3, as long as the flow-resisting effect on the overflowing glue is achieved.
As a second aspect of the present application, referring to fig. 3, there is provided a short circuit prevention structure,
example 4:
the short-circuit prevention structure in this embodiment includes:
the carrier plate 100, the carrier plate 100 includes a mounting area 110, and at least one glue overflow groove 120 is formed on the carrier plate 100 at the periphery of the mounting area 110; the glue overflow groove 120 surrounds the periphery of the mounting area 110.
The chip 200 is attached to the attachment region 110 of the carrier 100 through a conductive adhesive layer 300, and the chip 200 is connected to the lead 500 through a lead 220.
It should be explained that the conductive adhesive layer 300 may adopt silica gel containing conductive particles, which has conductive performance.
It can be understood that the coupling connection between the chip 200 and the carrier board 100 is achieved because when the chip 200 is mounted on the mounting region 110, a conductive adhesive layer 300 is required to be coated between the chip 200 and the mounting region 110. Once the coating dose is improperly controlled, the conductive adhesive layer 300 may flow around and spread. The at least one glue overflow groove 120 can play a role in blocking expansion of the conductive glue layer 300, and the conductive glue layer 300 is placed to be fused and connected with other chips 200 or the conductive glue layers 300 of other chips 200 due to further expansion of the conductive glue layer 300, so that short circuit connection among the chips 200 is placed.
Example 5:
referring to fig. 4, the present embodiment includes:
the short-circuit prevention lead frame of the first aspect of the present invention comprises a carrier 100, wherein the carrier 100 comprises a mounting area 110 for mounting a chip 200, and at least one glue overflow groove 120 is formed on the carrier 100 at the periphery of the mounting area 110. The inner wall of the glue overflow groove 120 is provided with at least one flow blocking convex rib 121. The inner wall of the glue overflow groove 120 includes the bottom surface of the glue overflow groove 120 and at least one surface of the side wall.
The chip 200 is attached to the attachment region 110 of the carrier 100 through a conductive adhesive layer 300, and the chip 200 is connected to the lead 500 through a lead 220.
It should be noted that, in order to make the glue overflow groove 120 have a certain blocking effect on glue overflow, the glue overflow speed is controlled to prevent glue overflow from leaking before solidification due to too high glue overflow speed. The flow blocking ribs 121 can block the excessive glue, so that the flow speed of the excessive glue can be controlled.
Example 6:
referring to fig. 5, the present embodiment includes:
the short-circuit prevention lead frame of the first aspect of the present invention comprises a carrier 100, wherein the carrier 100 comprises a mounting area 110 for mounting a chip 200, and at least one glue overflow groove 120 is formed on the carrier 100 at the periphery of the mounting area 110. And flow-resisting concave points 122 are densely distributed on the inner wall of the glue overflow groove 120. The inner wall of the glue overflow groove 120 includes the bottom surface of the glue overflow groove 120 and at least one surface of the side wall.
The chip 200 is attached to the attachment region 110 of the carrier 100 through a conductive adhesive layer 300, and the chip 200 is connected to the lead 500 through a lead 220.
It should be noted that, in order to make the glue overflow groove 120 have a certain blocking effect on glue overflow, the glue overflow speed is controlled to prevent glue overflow from leaking before solidification due to too high glue overflow speed. The flow-resisting concave points 122 can block the glue overflow, so that the flow speed of the glue overflow can be controlled.
As a third aspect of the present invention, there is provided a short-circuit prevention lead frame package structure, which includes a plastic package layer 400, at least one pin 500 being plastic-molded in the plastic package layer 400, and the short-circuit prevention structure according to the second aspect of the present invention.
The short-circuit prevention structure corresponds to the pin 500, that is, a bonding pad 210 covers a connection point of the chip, one end of a lead 220 is connected to the bonding pad 210, and the other end of the lead is connected to the pin 500.
Those of ordinary skill in the art will understand that: the above description is only exemplary of the present application and should not be construed as limiting the present application, and any modification, equivalent replacement, or improvement made within the spirit of the present application should be included in the protection scope of the present application.
Claims (8)
1. An anti-short circuit lead frame, comprising:
the chip mounting structure comprises a carrier plate, wherein the carrier plate comprises a mounting area for mounting a chip, at least one glue overflow groove is formed in the periphery of the mounting area, at least one flow-resisting convex rib is arranged on the inner wall of the glue overflow groove, or flow-resisting concave points are densely distributed on the inner wall of the glue overflow groove.
2. The short-circuit-proof lead frame according to claim 1, wherein the glue-overflow groove surrounds the periphery of the mounting area.
3. The short-circuit-proof lead frame according to claim 1, wherein the depth of the glue overflow groove is one third to five sixths of the thickness of the carrier.
4. A short-circuit prevention structure, comprising: a short-circuit prevention lead frame according to any one of claims 1 to 3; further comprising:
and the chip is attached in the attaching area of the carrier plate through a conductive adhesive layer.
5. The short-circuit prevention structure of claim 4, wherein the glue overflow groove surrounds the periphery of the mounting area.
6. The short-circuit prevention structure of claim 5, wherein the chip is connected to the pin by a wire.
7. An anti-short circuit lead frame packaging structure, characterized in that the anti-short circuit lead frame packaging structure comprises a plastic packaging layer, at least one pin is plastic-packaged in the plastic packaging layer, and the anti-short circuit structure according to claim 6 corresponds to the pin.
8. The short-circuit prevention lead frame package structure as claimed in claim 7, wherein the connection points of the chip are covered with pads, one end of the lead is connected to the pad, and the other end is connected to the pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020141605.3U CN211828750U (en) | 2020-01-21 | 2020-01-21 | Short circuit prevention lead frame, short circuit prevention structure and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020141605.3U CN211828750U (en) | 2020-01-21 | 2020-01-21 | Short circuit prevention lead frame, short circuit prevention structure and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211828750U true CN211828750U (en) | 2020-10-30 |
Family
ID=72992488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020141605.3U Active CN211828750U (en) | 2020-01-21 | 2020-01-21 | Short circuit prevention lead frame, short circuit prevention structure and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211828750U (en) |
-
2020
- 2020-01-21 CN CN202020141605.3U patent/CN211828750U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6838754B2 (en) | Multi-chip package | |
| US6759737B2 (en) | Semiconductor package including stacked chips with aligned input/output pads | |
| JP4195804B2 (en) | Dual die package | |
| US7790504B2 (en) | Integrated circuit package system | |
| US20030006055A1 (en) | Semiconductor package for fixed surface mounting | |
| KR20170084174A (en) | Sensing chip encapsulation component and electronic device with same | |
| KR100394030B1 (en) | stack-type semiconductor package | |
| JPH1084069A (en) | Bottom lead type semiconductor package | |
| CN211828750U (en) | Short circuit prevention lead frame, short circuit prevention structure and packaging structure | |
| CN214099628U (en) | Lead frame structure, chip device structure and packaging body | |
| US20070267756A1 (en) | Integrated circuit package and multi-layer lead frame utilized | |
| KR100723453B1 (en) | Semiconductor package for tab bonding | |
| US20080038872A1 (en) | Method of manufacturing semiconductor device | |
| KR200182574Y1 (en) | Stack package | |
| CN218160365U (en) | Packaging structure | |
| KR100610917B1 (en) | Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same | |
| KR100235498B1 (en) | Semiconductor package | |
| KR19990086280A (en) | Semiconductor package | |
| KR19990026494A (en) | Dual laminated package and manufacturing method | |
| KR20010026512A (en) | Multi chip package | |
| KR20010111659A (en) | Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same | |
| KR100222294B1 (en) | Semiconductor package | |
| KR20000003001A (en) | Multi chip package using double sided tape | |
| KR100457421B1 (en) | semiconductor package | |
| KR20030055834A (en) | Ball grid array type semiconductor chip package using leadframe and stack package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |