CN211827250U - Relay protection system and special multi-core Soc chip architecture thereof - Google Patents
Relay protection system and special multi-core Soc chip architecture thereof Download PDFInfo
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- CN211827250U CN211827250U CN202020560251.6U CN202020560251U CN211827250U CN 211827250 U CN211827250 U CN 211827250U CN 202020560251 U CN202020560251 U CN 202020560251U CN 211827250 U CN211827250 U CN 211827250U
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Abstract
The embodiment of the utility model relates to relay protection system and special multicore Soc chip framework thereof, handle core, communication data processing core, protection shutting including integrated first double-channel DDR, second double-channel DDR, management that sets up on a chip and handle the core, protect logic processing core, first second level buffer memory, second level buffer memory, first one-level buffer memory, second one-level buffer memory and watchdog logic detector. According to the multi-core Soc chip architecture special for the relay protection system, a plurality of chip hardware are integrated on a chip, so that the original complex multi-chip hardware architecture is simplified; the low running reliability and stability of the relay protection system caused by the unstable connection of the multi-chip hardware structure are avoided, and the running reliability and stability of the relay protection system are improved. The technical problems that the multi-chip architecture of the existing relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the running stability and reliability of a relay protection product are influenced are solved.
Description
Technical Field
The utility model relates to an electric power system relay protection technical field especially relates to a relay protection system and special multicore Soc chip framework thereof.
Background
The method is popularized and applied to the power system at present, corresponding intelligent and digital technologies are mature day by day, and the relay protection of the power system at present is intelligent and digital relay protection.
The multi-chip architecture of the traditional relay protection is complex, so that the operation stability and reliability of a relay protection product are influenced, and the system structure of the relay protection product is complex, so that the manufacturing cost is high.
Therefore, in view of the above situation, how to simplify the multi-chip architecture for relay protection and improve the stability and reliability of the multi-chip architecture becomes an important technical problem to be solved urgently by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a relay protection system and special multicore Soc chip framework thereof for the multichip framework who solves current relay protection adopts the framework that a plurality of chips adopted a plurality of cardboards, and this multichip framework is complicated, thereby influences the technical problem of relay protection product operating stability and reliability.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
a multi-core Soc chip architecture special for a relay protection system is used for the relay protection system and comprises at least four processing cores, a first double-channel DDR, a second double-channel DDR and a watchdog logic detector, wherein the four processing cores are integrated on one chip, the watchdog logic detector is used for detecting the running state of each processing core, and the four processing cores are respectively a management processing core, a communication data processing core, a protection locking processing core and a protection logic processing core; a first secondary cache and a second secondary cache are connected between the first double-channel DDR and the second double-channel DDR; the management processing core and the message data processing core are respectively connected with the first secondary cache, and the protection locking processing core and the protection logic processing core are respectively connected with the second secondary cache;
the management processing core and the communication data processing core are respectively provided with a first primary cache between the first secondary cache and the second secondary cache, and the protection locking processing core and the protection logic processing core are respectively provided with a second primary cache between the second secondary cache and the second primary cache.
Preferably, the watchdog logic detector is provided with detection IO interfaces, the number of which is matched with that of the processing cores, and the detection IO interfaces are connected with the processing cores.
Preferably, the first secondary cache and the first double-channel DDR are connected, and the second secondary cache and the second double-channel DDR are connected by a data bus.
Preferably, the first primary Cache and the second primary Cache are both Cache memories, and bit rates of the first primary Cache and the second primary Cache are both 32 kbps; the first second-level Cache and the second-level Cache are Cache memories, and the bit rates of the first second-level Cache and the second-level Cache are 1 Mbps.
Preferably, the processing core is a processing core of a C-Sky architecture model CK 860;
the management processing core is configured to read a result processed by the protection logic processing core and a result processed by the protection locking processing core from the memories of the first double-channel DDR and the second double-channel DDR for management, and also configured to read original data provided by the communication data processing core from the first secondary cache for wave recording;
the communication data processing core is used for realizing the receiving identification and the message sending of different types of data messages and carrying out data exchange with the outside;
the protection locking processing core is used for reading data of the second double-channel DDR memory through the second secondary cache to perform logic processing, and sending a processing result to the second double-channel DDR memory through the second secondary cache; the relay protection system is also used for carrying out logic judgment according to the processing result to determine whether to operate a relay for starting the relay protection system;
the protection logic processing core is used for reading the data of the first double-channel DDR through the second secondary cache to perform logic processing, and sending a processing result to the memory of the first double-channel DDR through the second secondary cache; and the logic judgment is also carried out according to the processing result to determine whether to operate the protection outlet relay of the relay protection system.
Preferably, the main frequency of the processing core of the C-Sky architecture CK860 model is 800 MHZ.
Preferably, the management processing core is provided with a debugging network interface.
Preferably, at least four connection interfaces are arranged on the communication data processing core. Wherein, each connection interface is an optical fiber connection interface with SV, GOOSE and MMS three-in-one network.
The utility model also provides a relay protection system, including the aforesaid special multicore Soc chip framework of relay protection system.
According to the above technical scheme, the utility model discloses an advantage that embodiment has:
1. according to the special multi-core Soc chip architecture for the relay protection system, the four processing cores, the first double-channel DDR, the second double-channel DDR, the first secondary cache, the second secondary cache, the first primary cache, the second primary cache and the watchdog logic detector are integrally arranged on a chip, so that the original complex multi-chip hardware architecture is simplified; the operation reliability and the stability of the relay protection system caused by unstable connection of a multi-chip hardware structure are also avoided to be low, and the multi-chip integration is adopted by the special multi-core Soc chip framework for the relay protection system, so that the operation reliability and the stability of the relay protection system are also improved. The technical problems that the multi-chip architecture of the conventional relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the running stability and reliability of a relay protection product are influenced are solved;
2. the relay protection system adopts the special multi-core Soc chip architecture of the relay protection system to replace the design of a plurality of clamping plates of a plurality of chips adopted in the existing relay protection system, and the special multi-core Soc chip architecture of the relay protection system simplifies the original complex multi-chip hardware architecture; the operation reliability and the stability of the relay protection system caused by unstable connection of a multi-chip hardware structure are also avoided to be low, and the multi-chip integration is adopted by the special multi-core Soc chip framework for the relay protection system, so that the operation reliability and the stability of the relay protection system are also improved. The technical problems that the multi-chip architecture of the existing relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the running stability and reliability of a relay protection product are influenced are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a frame diagram of a multi-core Soc chip architecture for a relay protection system according to an embodiment of the present invention.
Fig. 2 is a circuit frame diagram of another embodiment of the multi-core Soc chip architecture for relay protection system according to the embodiment of the present invention.
Fig. 3 is a circuit frame diagram of another embodiment of the multi-core Soc chip architecture for relay protection system according to the embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and obviously, the embodiments described below are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
With the continuous change of the operating environment of the relay protection device by the power system, the ideas of miniaturization of the secondary equipment and integration of the primary equipment and the secondary equipment are provided, the requirements on reliability and stability are higher and higher, and the complexity of a hardware architecture of the device is often a bottleneck for limiting the reliability and the stability of the relay protection device.
Therefore, the embodiment of the application provides a relay protection system and a special multi-core Soc chip architecture thereof, which are used for solving the technical problems that the multi-chip architecture of the existing relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the operation stability and reliability of a relay protection product are influenced.
The first embodiment is as follows:
fig. 1 is a frame diagram of a multi-core Soc chip architecture for a relay protection system according to an embodiment of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a special multi-core Soc chip architecture for a relay protection system, which includes at least four processing cores 10, a first dual-channel DDR20, a second dual-channel DDR30 and a watchdog logic detector 60, where the four processing cores 10 are respectively a management processing core 11, a communication data processing core 12, a protection locking processing core 13 and a protection logic processing core 14; a first secondary cache 40 and a second secondary cache 50 are connected between the first double-channel DDR20 and the second double-channel DDR 30; the management processing core 11 and the message data processing core 12 are respectively connected with the first secondary cache 40, and the protection locking processing core 13 and the protection logic processing core 14 are respectively connected with the second secondary cache 50;
the management processing core 11 and the communication data processing core 12 are respectively connected with the first second-level cache 40, and a first-level cache 41 is arranged between the management processing core and the communication data processing core, and the protection locking processing core 13 and the protection logic processing core 14 are respectively connected with the second-level cache 50, and a second first-level cache 51 is arranged between the protection locking processing core and the protection logic processing core.
In the embodiment of the utility model, the special multicore Soc chip framework of relay protection system includes that the processing core 10 of four C-Sky framework CK860 models realizes the relay protection system of single cardboard of chip ization, and with the traditional relay protection system that adopts a plurality of multi-board card structures of a plurality of hardware, the special multicore Soc chip framework of relay protection system integrates a plurality of chip hardware and sets up on an integrated chip, has simplified original complicated multichip hardware framework; the low reliability and stability of the operation of the relay protection system caused by the unstable connection of the multi-chip multi-board structure are avoided, and the reliability and stability of the operation of the relay protection system are also improved by adopting multi-chip integration in the multi-core Soc chip architecture special for the relay protection system.
It should be noted that the multi-core Soc chip architecture dedicated for the relay protection system reasonably distributes functions of the four processing cores, and the processing cores with different functions perform different data logic processing analyses. The main frequency of the processing core of the CK860 model of the C-Sky architecture is preferably 800 MHZ.
In the embodiment of the present invention, the first dual channel DDR20 and the second dual channel DDR30 are preferably disposed outside the integrated chip.
It should be noted that the dual channel DDR means that the chipset can address and read data on two different data channels respectively; the two memory channels working independently depend on two independent and parallel working. Specifically, the double-channel DDR has two 64-bit memory controllers, the bandwidth provided by the double 64-bit memory system is equal to the bandwidth provided by a 128-bit memory system, but the two have different effects; the dual channel architecture includes two independent, complementary intelligent memory controllers that are capable of operating simultaneously with zero latency with respect to each other. For example, when controller B is ready to access the memory the next time, controller A is reading/writing the main memory and vice versa. The complementary 'nature' of the two memory controllers can reduce the effective waiting time by 50%, and improve the efficiency of channel data exchange and data reading. Each processing core in the multi-core Soc chip architecture special for the relay protection system adopts a double-channel DDR to cache data, and the processing efficiency of the processing cores is improved.
In the embodiment of the present invention, the connection between the first secondary cache 40 and the first dual channel DDR20 and the connection between the second secondary cache 50 and the second dual channel DDR30 are all data bus connections.
The embodiment of the present invention provides a Cache memory for the first second-level Cache 40 and the second-level Cache 50, and 1Mbps is preferred for the bit rate of the first second-level Cache 40 and the second-level Cache 50. The first-level Cache 41 and the second first-level Cache 51 both preferably use Cache memories, and the bit rates of the first-level Cache 41 and the second first-level Cache 51 both preferably use 32 kbps. In other embodiments, the first primary Cache 41 and the second primary Cache 51 may also be other memories having the same or similar functional principles as the Cache memory.
It should be noted that, in other embodiments, the first-level second-level Cache 40 and the second-level Cache 50 may also use a memory having the same or similar functional principle as the Cache memory.
In an embodiment of the present invention, watchdog logic detector 60 is primarily used to detect the operating state of each processing core 10. The watchdog logic detector 60 is mainly used to improve the safety and stability of the four processing cores during operation. The number of processing cores is set corresponding to the multi-core Soc chip architecture special for the relay protection system, and the number of detection IO interfaces is set corresponding to the watchdog logic detector 60, and the detection IO interfaces are connected with the processing cores.
It should be noted that the watchdog logic detector 60 is used to periodically check the internal conditions of the processing core, and send a restart signal to the chip once an error occurs; while the watchdog command has the highest priority among the interrupts of the program. The watchdog logic detector 60 restarts the chip or locks the exit when each processing core is in an abnormal state, so as to prevent system malfunction and operation rejection when the CPU in the relay protection system is abnormal.
According to the special multi-core Soc chip architecture for the relay protection system, the four processing cores, the first double-channel DDR, the second double-channel DDR, the first secondary cache, the second secondary cache, the first primary cache, the second primary cache and the watchdog logic detector are integrally arranged on a chip, so that the original complex multi-chip hardware architecture is simplified; the operation reliability and the stability of the relay protection system caused by unstable connection of a multi-chip hardware structure are also avoided to be low, and the multi-chip integration is adopted by the special multi-core Soc chip framework for the relay protection system, so that the operation reliability and the stability of the relay protection system are also improved. The technical problems that the multi-chip architecture of the existing relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the running stability and reliability of a relay protection product are influenced are solved.
In the embodiment of the present invention, the management processing core 11 is mainly configured to read the result processed by the protection logic processing core 14 and the result processed by the protection locking processing core 13 from the memories of the first dual-channel DDR20 and the second dual-channel DDR30 for management, and is also configured to read the original data provided by the communication data processing core 12 from the first secondary cache 40 for wave recording.
It should be noted that the management processing core 11 is further configured to send a GOOSE trip instruction to the relay protection system and send an mms message to the monitoring device to notify that a protection action occurs through the communication data processing core 12. The original data may be information such as a sampling value, which means data obtained from the outside without logical operation or difference processing.
In the embodiment of the present invention, the communication data processing core 12 is mainly used for implementing the data exchange between the identification of the different types of data message reception, the message transmission and the outside, and specifically, the communication data processing core 12 implements the data exchange between the identification of the different types of data message reception, the data preprocessing function, the message transmission and the outside; and sends the preprocessed data to the shared region of the memories of the first and second dual channel DDR20 and DDR30 through the first level two cache 40 (i.e. the same data is sent to both the first and second dual channel DDR20 and 30).
It should be noted that the memories of the dual channel DDR are physically isolated, and a fixed address in each channel memory is set to enable data to be carried by using the CPU bus, so as to achieve the purpose of sharing and using data in a fixed memory space.
In the embodiment of the present invention, the protection locking processing core 13 is mainly configured to read data of the second double-channel DDR30 memory through the second-level cache 50 to perform logic processing, and send the processing result to the memory of the second double-channel DDR30 through the second-level cache 50; and the relay protection system is also used for carrying out logic judgment according to the processing result to determine whether to operate the relay for starting the relay protection system.
In the embodiment of the present invention, the protection logic processing core 14 is mainly configured to read the data of the first double-channel DDR20 through the second-level cache 50 to perform logic processing, and send the processing result to the memory of the first double-channel DDR20 through the second-level cache 50; and the logic judgment is also carried out according to the processing result to determine whether to operate the protection outlet relay of the relay protection system.
It should be noted that the logic processing in the protection logic processing core 14 refers to protection logic judgment, such as differential protection logic, overcurrent protection logic, and the like, and may also be various protection principles and algorithms of the secondary device in the power system.
Fig. 2 is a circuit frame diagram of another embodiment of the multi-core Soc chip architecture for relay protection system according to the embodiment of the present invention.
As shown in fig. 2, in an embodiment of the present application, a debugging port 111 is provided on the management processing core 11.
It should be noted that at least one debugging network port 111 is arranged on the management processing core 11, and the debugging network port 111 is mainly used for implementing the debugging function of each functional module in the relay protection system.
Fig. 3 is a circuit frame diagram of another embodiment of the multi-core Soc chip architecture for relay protection system according to the embodiment of the present invention.
As shown in fig. 3, in an embodiment of the present application, at least four connection interfaces 121 are disposed on the communication data processing core 12.
It should be noted that, each connection interface 121 preferably selects an optical fiber connection interface with SV, GOOSE, and MMS three-in-one network, and the optical fiber connection interface is mainly used for connection to realize identification of different types of data message reception, data preprocessing function, message transmission, and data exchange with the outside; and sends the preprocessed data to the shared region of the memories of the first and second dual channel DDR20 and DDR30 through the first level two cache 40 (i.e. the same data is sent to both the first and second dual channel DDR20 and 30).
Example two:
the embodiment of the utility model provides a relay protection system is still provided, including embodiment one the special multicore Soc chip framework of relay protection system.
It should be noted that the architecture of the multi-core Soc chip dedicated for the relay protection system has been described in detail in the first embodiment, and therefore, is not described in the first embodiment.
The relay protection system adopts the special multi-core Soc chip architecture of the relay protection system to replace the design of a plurality of clamping plates of a plurality of chips adopted in the existing relay protection system, and the special multi-core Soc chip architecture of the relay protection system simplifies the original complex multi-chip hardware architecture; the operation reliability and the stability of the relay protection system caused by unstable connection of a multi-chip hardware structure are also avoided to be low, and the multi-chip integration is adopted by the special multi-core Soc chip framework for the relay protection system, so that the operation reliability and the stability of the relay protection system are also improved. The technical problems that the multi-chip architecture of the existing relay protection adopts an architecture that a plurality of chips adopt a plurality of clamping plates, and the multi-chip architecture is complex, so that the running stability and reliability of a relay protection product are influenced are solved.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. A multi-core Soc chip architecture special for a relay protection system is used for the relay protection system and is characterized by comprising at least four processing cores, a first double-channel DDR, a second double-channel DDR and a watchdog logic detector, wherein the four processing cores are integrated on one chip, the watchdog logic detector is used for detecting the running state of each processing core, and the four processing cores are a management processing core, a communication data processing core, a protection locking processing core and a protection logic processing core respectively; a first secondary cache and a second secondary cache are connected between the first double-channel DDR and the second double-channel DDR; the management processing core and the message data processing core are respectively connected with the first secondary cache, and the protection locking processing core and the protection logic processing core are respectively connected with the second secondary cache;
the management processing core and the communication data processing core are respectively provided with a first primary cache between the first secondary cache and the second secondary cache, and the protection locking processing core and the protection logic processing core are respectively provided with a second primary cache between the second secondary cache and the second primary cache.
2. The special multi-core Soc chip architecture for the relay protection system according to claim 1, wherein the watchdog logic detector is provided with detection IO interfaces with the number matched with that of the processing cores, and the detection IO interfaces are connected with the processing cores.
3. The relay protection system dedicated multi-core Soc chip architecture of claim 1, wherein the first secondary cache and the first double-channel DDR are connected, and the second secondary cache and the second double-channel DDR are connected by a data bus.
4. The special multi-core Soc chip architecture for the relay protection system according to claim 1, wherein the first primary Cache and the second primary Cache are both Cache memories, and the bit rates of the first primary Cache and the second primary Cache are both 32 kbps; the first second-level Cache and the second-level Cache are Cache memories, and the bit rates of the first second-level Cache and the second-level Cache are 1 Mbps.
5. The relay protection system dedicated multi-core Soc chip architecture of claim 1, wherein the four processing cores are C-Sky architecture CK860 type processing cores;
the management processing core is configured to read a result processed by the protection logic processing core and a result processed by the protection locking processing core from the memories of the first double-channel DDR and the second double-channel DDR for management, and also configured to read original data provided by the communication data processing core from the first secondary cache for wave recording;
the communication data processing core is used for realizing the receiving identification and the message sending of different types of data messages and carrying out data exchange with the outside;
the protection locking processing core is used for reading data of the second double-channel DDR memory through the second secondary cache to perform logic processing, and sending a processing result to the second double-channel DDR memory through the second secondary cache; the relay protection system is also used for carrying out logic judgment according to the processing result to determine whether to operate a relay for starting the relay protection system;
the protection logic processing core is used for reading the data of the first double-channel DDR through the second secondary cache to perform logic processing, and sending a processing result to the memory of the first double-channel DDR through the second secondary cache; and the logic judgment is also carried out according to the processing result to determine whether to operate the protection outlet relay of the relay protection system.
6. The relay protection system dedicated multi-core Soc chip architecture of claim 5, wherein the dominant frequency of the processing core of the C-Sky architecture CK860 model is 800 MHZ.
7. The special multi-core Soc chip architecture for the relay protection system according to claim 1, wherein the management processing core is provided with a debugging network port.
8. The special multi-core Soc chip architecture for the relay protection system according to claim 1, wherein the communication data processing core is provided with at least four connection interfaces.
9. The relay protection system specific multi-core Soc chip architecture of claim 8, wherein each of the connection interfaces is an optical fiber connection interface with SV, GOOSE, and MMS integration.
10. A relay protection system, comprising the multicore Soc chip architecture dedicated for relay protection systems according to any one of claims 1 to 9.
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