CN211744322U - Current type full-bridge control circuit - Google Patents
Current type full-bridge control circuit Download PDFInfo
- Publication number
- CN211744322U CN211744322U CN201922331134.2U CN201922331134U CN211744322U CN 211744322 U CN211744322 U CN 211744322U CN 201922331134 U CN201922331134 U CN 201922331134U CN 211744322 U CN211744322 U CN 211744322U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- operational amplifier
- resistor
- peak current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The utility model discloses a current type full-bridge control circuit in the power electronic technology field, clock controller and peak current detector, the maximum duty cycle limiter is connected, and for it provides clock signal, peak current detector's output and drive controller are connected, peak current among its detection circuitry and send control signal to drive controller, the output and the drive controller of maximum duty cycle limiter are connected, whether its detection circuitry duty cycle exceeds the setting value, and send control signal to drive controller, drive controller receives the control signal of peak current detector and maximum duty cycle limiter after, send interlocking and alternative drive signal. The utility model discloses control signal is accurate, the response is fast, the reliability is high, can restrain the input voltage jump simultaneously, improves transient response, improves the circuit reliability.
Description
Technical Field
The utility model relates to a power electronic technology field, specific theory relates to a current type full-bridge control circuit.
Background
With the development of science and technology, the application of the switching power supply is more and more extensive, the application of various components can be involved in the power supply topological structure of the switching power supply, however, the power supply is limited by the supply side of many components under the influence of trade regionalization, and thus, the domestic requirements on the components applied in China are provided.
However, the existing switching power supply device is difficult to realize the requirement of localization, and the complete function of the whole switching power supply topological structure is difficult to complete, and the reliability of the whole topological structure is greatly influenced.
Disclosure of Invention
In order to overcome the deficiencies of the prior art, the utility model provides a current type full-bridge control circuit.
The utility model discloses technical scheme as follows:
a current mode full bridge control circuit comprising a clock controller, a peak current detector, a maximum duty cycle limiter and a drive controller;
the clock controller is connected with the peak current detector and the maximum duty ratio limiter and provides a clock signal for the peak current detector and the maximum duty ratio limiter;
the output end of the peak current detector is connected with the driving controller, and the peak current detector detects the peak current in the circuit and sends a control signal to the driving controller;
the output end of the maximum duty ratio limiter is connected with the driving controller, and the output end of the maximum duty ratio limiter detects whether the duty ratio of a circuit exceeds a set value or not and sends a control signal to the driving controller;
and the driving controller sends out interlocking and alternating driving signals after receiving the control signals of the peak current detector and the maximum duty ratio limiter.
According to the above technical solution, in the clock controller, the reference voltage VREF is respectively connected to one end of a ninth resistor R9 and one end of a seventh resistor R7, the other end of the ninth resistor R9 is respectively connected to a sixth pin of a fourth capacitor C4 and a second operational amplifier U12, the other end of the seventh resistor R7 is respectively connected to a sixth resistor R6 and a fifth pin of the second operational amplifier U12, the other end of the fourth capacitor C4 and the other end of the sixth resistor R6 are both grounded, the seventh pin of the second operational amplifier U12 generates the clock signal CLK, and the fifth pin of the second operational amplifier U12 is connected through an eighth resistor R8.
According to the utility model discloses of above-mentioned scheme, characterized in that in the peak current detector, clock signal CLK that clock controller produced IS connected with the third pin that U1 was put to first fortune after first triode Q12, current detection signal IS through filter circuit after with the third pin that U1 was put to first fortune IS connected, feedback loop signal voltage in proper order through first diode D1, fourth resistance R4 after with the second pin that U1 was put to first fortune IS connected, the second pin that U1 was put to first fortune still IS through third resistance R3 ground connection, the first pin that U1 was put to first fortune with drive controller IS connected.
Further, the first diode D1 includes two diodes connected in series.
Further, the eighth pin of the first op-amp U1 is grounded through the third capacitor C3, and the fourth pin thereof is grounded.
The utility model discloses according to the above scheme, characterized in that, in the maximum duty cycle limiter, the clock signal CLK that the clock controller produced is connected with the third pin of second operational amplifier U12 through sixteenth resistance R16, the second pin of the U12 of said second operational amplifier is still connected with said clock signal CLK through sixth diode D6;
the third pin of the second operational amplifier U12 is grounded after passing through a twentieth resistor R20, the second pin thereof is connected with the input voltage VIN through a twelfth resistor R22 and is grounded through an eighth capacitor C8, and the first pin of the second operational amplifier U12 is connected with the driving controller and is connected with the third pin thereof through a twenty-fifth resistor R25.
Furthermore, an eighth pin of the second operational amplifier U12 is grounded after passing through the seventh capacitor C7, and a fourth pin thereof is grounded.
Further, a second pin of the second op-amp U12 is connected to an anode of the sixth diode D6, and a cathode of the sixth diode D6 is connected to the clock signal CLK.
According to the above technical solution the utility model discloses, characterized in that, in the drive controller, the control signal of peak current detector connects the AND gate second input end of the third chip after passing through the NAND gate of the second chip, the output end of the AND gate of the third chip connects the second input end of the AND gate of the sixth chip and the second input end of the AND gate of the seventh chip;
a control signal of the maximum duty ratio limiter is respectively connected with a CP end of a D trigger of a fourth chip and a first input end of an AND gate of the third chip, a Q end of the D trigger of the fourth chip is respectively connected with an input end of a fifth chip and a first input end of an AND gate of a sixth chip, and an output end of the fifth chip is respectively connected with a D end of the D trigger of the fourth chip and a first input end of an AND gate of a seventh chip;
and the output end of the AND gate of the sixth chip and the output end of the AND gate of the seventh chip respectively output two driving signals, and the two driving signals are interlocked and alternately conducted.
Further, the VCC ports of the second chip, the third chip, the fourth chip, the fifth chip, the sixth chip and the seventh chip are all connected to a reference voltage VREF, the reference voltage VREF is grounded after passing through a twelfth capacitor C12, and the GND ports of the second chip, the third chip, the fourth chip, the fifth chip, the sixth chip and the seventh chip are all grounded.
The utility model has the advantages that each part of the utility model is built by discrete devices, and is controlled by cascade interlocking, thereby realizing the localization requirement of 100 percent of devices; the whole topological structure has the characteristics of quick response, high reliability, low cost and the like, is particularly suitable for places with localization requirements, and can be applied to the technical fields of laser, medicine, industry, military and the like.
Drawings
Fig. 1 is a block diagram of the present invention.
Fig. 2 is a circuit diagram of a clock controller.
Fig. 3 is a circuit diagram of a peak current detector.
Fig. 4 is a circuit diagram of a maximum duty cycle limiter.
Fig. 5 is a schematic diagram of a drive controller.
Fig. 6 is a circuit diagram of the drive controller.
Detailed Description
The invention is further described with reference to the following figures and embodiments:
as shown in FIG. 1, a current mode full bridge control circuit includes four parts, a clock controller, a peak current detector, a maximum duty cycle limiter and a driving controller. The clock controller is connected with the peak current detector and the maximum duty cycle limiter, the output ends of the peak current detector and the maximum duty cycle limiter are connected with the driving controller, and the driving controller sends out interlocking and alternating driving signals.
1. Clock controller
As shown in fig. 2, a clock controller is coupled to and provides a clock signal to the peak current detector, the maximum duty cycle limiter. The clock controller includes a second op-amp U12-B (high speed op-amp).
The reference voltage VREF is respectively connected with one end of a ninth resistor R9 and one end of a seventh resistor R7, the other end of the ninth resistor R9 is respectively connected with a fourth capacitor C4 and a sixth pin of a second operational amplifier U12-B, the other end of the seventh resistor R7 is respectively connected with a sixth resistor R6 and a fifth pin of the second operational amplifier U12-B, the other end of the fourth capacitor C4 and the other end of the sixth resistor R6 are grounded, the seventh pin of the second operational amplifier U12-B generates a clock signal CLK, and is connected with the fifth pin of the second operational amplifier U12-B through an eighth resistor R8.
In the clock controller, the reference voltage VREF charges and discharges a fourth capacitor C4 through a ninth resistor R9, after a triangular wave is generated, the sixth pin of the second operational amplifier U12-B is compared with the fifth pin, and a clock signal CLK is generated. The high-precision resistor and capacitor are matched with the high-speed operational amplifier to generate a high-precision clock signal.
2. Peak current detector
As shown in fig. 3, the output of the peak current detector is connected to the drive controller, which detects the peak current in the circuit and sends a control signal to the drive controller. The peak current detector comprises a first operational amplifier U1-A (high-speed operational amplifier), wherein the eighth pin of the first operational amplifier U1-A is grounded through a third capacitor C3, and the fourth pin of the first operational amplifier is grounded.
A clock signal CLK generated by a clock controller IS connected with a third pin of a first operational amplifier U1 after passing through a first triode Q12, a current detection signal IS IS connected with a third pin of a first operational amplifier U1-A after passing through a filter circuit, a feedback loop signal voltage VE IS connected with a second pin of a first operational amplifier U1-A after passing through a first diode D1 and a fourth resistor R4 in sequence, the second pin of the first operational amplifier U1-A IS grounded through a third resistor R3, and the first pin of the first operational amplifier U1-A IS connected with a driving controller.
Preferably, in the filter circuit, the current detection signal IS connected to the first capacitor C1 and the third pin of the first operational amplifier U1-a through the first resistor R1, and the other end of the first capacitor C1 IS grounded. The first diode D1 includes two diodes connected in series and the polarity profiles of the two diodes are the same along the extension of the circuit.
In the peak current detector, the feedback loop signal voltage VE is fed to the second pin of the first operational amplifier U1-a through the first diode D1 and the resistor divider (the third resistor R3, the fourth resistor R4) as a reference signal. The current detection signal IS + IS sent to the third pin of the first operational amplifier U1-a through RC filtering (the first resistor R1 and the first capacitor C1), and when the level of the third pin IS higher than the voltage of the second pin, the first pin of the first operational amplifier U1-a sends a signal to the driving controller. If the peak current setting has not been reached during a cycle, the clock signal pulls the voltage at the third pin of the first operational amplifier U1-A low via the first transistor Q12 and the first pin of the first operational amplifier U1-A sends a signal to the drive signal controller.
3. Maximum duty cycle limiter
As shown in fig. 4, the output of the maximum duty cycle limiter is connected to the drive controller, which detects whether the circuit duty cycle exceeds a set value and sends a control signal to the drive controller. The maximum duty cycle limiter comprises a second operational amplifier U12-A (high-speed operational amplifier), wherein the eighth pin of the second operational amplifier U12-A is grounded after passing through a seventh capacitor C7, and the fourth pin of the second operational amplifier U12-A is grounded.
The clock signal CLK generated by the clock controller is connected with the third pin of the second operational amplifier U12-A through a sixteenth resistor R16, and the second pin of the second operational amplifier U12-A is also connected with the clock signal CLK through a sixth diode D6. The third pin of the second operational amplifier U12-a is grounded after passing through the twentieth resistor R20, the second pin thereof is connected with the input voltage VIN through the twelfth resistor R22 and is grounded through the eighth capacitor C8, and the first pin of the second operational amplifier U12-a is connected with the driving controller and is connected with the third pin thereof through the twenty-fifth resistor R25.
Preferably, the second pin of the second operational amplifier U12-a is connected to the anode of the sixth diode D6, and the cathode of the sixth diode D6 is connected to the clock signal CLK, so as to ensure the control of the signal flow direction.
In the maximum duty ratio limiter, an input voltage VIN + charges an eighth capacitor C8 through a twelfth resistor R22 to generate a triangular wave, the triangular wave is sent to a second pin of a second operational amplifier U12-A, a clock signal voltage CLK and an output voltage of a first pin of the second operational amplifier U12-A are sent to a third pin of the second operational amplifier U12-A as reference voltages after being subjected to voltage division through a sixteenth resistor R16, a twenty-fifth resistor R25 and a twentieth resistor R20, the reference voltages are compared with the second pin, and when the voltage of the second pin exceeds the voltage of the third pin, the first pin of the second operational amplifier U12-A sends a signal to a driving controller.
4. Drive controller
As shown in fig. 5 and 6, the driving controller receives the control signals of the peak current detector and the maximum duty limiter, and then sends out the interlocking and alternating driving signals.
A control signal of the peak current detector passes through the NAND gate of the second chip and then is connected with a second input end of the AND gate of the third chip, and an output end of the AND gate of the third chip is connected with a second input end of the AND gate of the sixth chip and a second input end of the AND gate of the seventh chip; the control signal of the maximum duty ratio limiter is respectively connected with the CP end of the D trigger of the fourth chip and the first input end of the AND gate of the third chip, the Q end of the D trigger of the fourth chip is respectively connected with the input end of the fifth chip and the first input end of the AND gate of the sixth chip, and the output end of the fifth chip is respectively connected with the D end of the D trigger of the fourth chip and the first input end of the AND gate of the seventh chip.
And the output end of the AND gate of the sixth chip and the output end of the AND gate of the seventh chip respectively output two driving signals, and the two driving signals are interlocked and alternately conducted.
In this embodiment, VCC ports of the second chip U2, the third chip U3, the fourth chip U4, the fifth chip U5, the sixth chip U6 and the seventh chip U7 are all connected to a reference voltage VREF, the reference voltage VREF passes through the twelfth capacitor C12 and is grounded, and GND ports of the second chip U2, the third chip U3, the fourth chip U4, the fifth chip U5, the sixth chip U6 and the seventh chip U7 are all grounded.
In the drive controller, the drive controller receives a SIGNAL (SIGNAL-IS) of a peak current detector and a SIGNAL (MAX-duty-CYCLE) of a maximum duty limiter, and when the drive controller receives one of the two SIGNALs, the drive IS turned off. The fourth chip U4 adopts a D flip-flop and is controlled by a NAND gate of the fifth chip U5, the level of a fourth pin (Q end) of the fourth chip U4 is ensured to be inverted in each period, and the interlocking and alternate conduction of the two drives (DRV1 and DRV2) are ensured under the control of the sixth chip U6 and the seventh chip U7 and the AND gate.
The utility model discloses an implementation principle does:
(1) sending out an accurate clock signal through a clock controller;
(2) the peak current detector and the maximum duty cycle limiter receive a signal from the clock controller;
(3) the clock controller triggers the peak current detector and the maximum duty cycle limiter to work;
(4) the peak current detector sends a signal to the drive controller after detecting that the current reaches a set value; or under a special transient state, the maximum duty ratio limiter detects that the duty ratio exceeds a set value, and sends a signal to the drive controller;
(5) the driving controller uses the logic circuit of the AND gate and the NAND gate to realize that interlocking and alternate driving signals are sent out, and when the peak current detector and the maximum duty ratio limiter signal are received, the driving signals are closed.
The utility model discloses control signal is accurate, the response is fast, the reliability is high, can restrain input voltage jump transient response simultaneously, improves the circuit reliability.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are considered to be within the scope of the invention as defined by the following claims.
The above exemplary description of the present invention is made in conjunction with the accompanying drawings, and it is obvious that the present invention is not limited by the above manner, and various improvements made by the method concept and technical solution of the present invention or by directly applying the concept and technical solution of the present invention to other occasions without improvement are all within the protection scope of the present invention.
Claims (10)
1. A current mode full bridge control circuit comprising a clock controller, a peak current detector, a maximum duty cycle limiter and a drive controller;
the clock controller is connected with the peak current detector and the maximum duty ratio limiter and provides a clock signal for the peak current detector and the maximum duty ratio limiter;
the output end of the peak current detector is connected with the driving controller, and the peak current detector detects the peak current in the circuit and sends a control signal to the driving controller;
the output end of the maximum duty ratio limiter is connected with the driving controller, and the output end of the maximum duty ratio limiter detects whether the duty ratio of a circuit exceeds a set value or not and sends a control signal to the driving controller;
and the driving controller sends out interlocking and alternating driving signals after receiving the control signals of the peak current detector and the maximum duty ratio limiter.
2. The current-mode full-bridge control circuit according to claim 1, wherein in the clock controller, a reference voltage VREF is respectively connected to one end of a ninth resistor R9 and one end of a seventh resistor R7, the other end of the ninth resistor R9 is respectively connected to a sixth pin of a fourth capacitor C4 and a second operational amplifier U12, the other end of the seventh resistor R7 is respectively connected to a sixth resistor R6 and a fifth pin of the second operational amplifier U12, the other end of the fourth capacitor C4 and the other end of the sixth resistor R6 are both grounded, the seventh pin of the second operational amplifier U12 generates a clock signal CLK, and is connected to the fifth pin of the second operational amplifier U12 through an eighth resistor R8.
3. The current-mode full-bridge control circuit according to claim 1, wherein in the peak current detector, the clock signal CLK generated by the clock controller IS connected to the third pin of the first operational amplifier U1 after passing through the first transistor Q12, the current detection signal IS connected to the third pin of the first operational amplifier U1 after passing through the filter circuit, the feedback loop signal voltage VE IS connected to the second pin of the first operational amplifier U1 after passing through the first diode D1 and the fourth resistor R4 in sequence, the second pin of the first operational amplifier U1 IS further grounded through the third resistor R3, and the first pin of the first operational amplifier U1 IS connected to the driving controller.
4. A current-mode full-bridge control circuit according to claim 3, wherein said first diode D1 comprises two diodes connected in series.
5. A current mode full bridge control circuit according to claim 3, wherein the eighth pin of said first op-amp U1 is connected to ground via a third capacitor C3, and the fourth pin is connected to ground.
6. A current-mode full-bridge control circuit according to claim 1, wherein in the maximum duty cycle limiter, a clock signal CLK generated by the clock controller is connected to the third pin of the second operational amplifier U12 through a sixteenth resistor R16, and the second pin of the second operational amplifier U12 is further connected to the clock signal CLK through a sixth diode D6;
the third pin of the second operational amplifier U12 is grounded after passing through a twentieth resistor R20, the second pin thereof is connected with the input voltage VIN through a twelfth resistor R22 and is grounded through an eighth capacitor C8, and the first pin of the second operational amplifier U12 is connected with the driving controller and is connected with the third pin thereof through a twenty-fifth resistor R25.
7. A current mode full bridge control circuit according to claim 6, wherein the eighth pin of said second operational amplifier U12 is grounded after passing through the seventh capacitor C7, and the fourth pin is grounded.
8. A current-mode full-bridge control circuit according to claim 6, wherein a second pin of the second operational amplifier U12 is connected to an anode of the sixth diode D6, and a cathode of the sixth diode D6 is connected to the clock signal CLK.
9. The current-mode full-bridge control circuit according to claim 1, wherein in the driving controller, the control signal of the peak current detector passes through the nand gate of the second chip and is connected to the second input terminal of the and gate of the third chip, and the output terminal of the and gate of the third chip is connected to the second input terminal of the and gate of the sixth chip and the second input terminal of the and gate of the seventh chip;
a control signal of the maximum duty ratio limiter is respectively connected with a CP end of a D trigger of a fourth chip and a first input end of an AND gate of the third chip, a Q end of the D trigger of the fourth chip is respectively connected with an input end of a fifth chip and a first input end of an AND gate of a sixth chip, and an output end of the fifth chip is respectively connected with a D end of the D trigger of the fourth chip and a first input end of an AND gate of a seventh chip;
and the output end of the AND gate of the sixth chip and the output end of the AND gate of the seventh chip respectively output two driving signals, and the two driving signals are interlocked and alternately conducted.
10. The current-mode full-bridge control circuit according to claim 9, wherein VCC ports of the second, third, fourth, fifth, sixth and seventh chips are all connected to a reference voltage VREF, and the reference voltage VREF is grounded after passing through a twelfth capacitor C12, and GND ports of the second, third, fourth, fifth, sixth and seventh chips are all grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922331134.2U CN211744322U (en) | 2019-12-23 | 2019-12-23 | Current type full-bridge control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922331134.2U CN211744322U (en) | 2019-12-23 | 2019-12-23 | Current type full-bridge control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211744322U true CN211744322U (en) | 2020-10-23 |
Family
ID=72868853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922331134.2U Active CN211744322U (en) | 2019-12-23 | 2019-12-23 | Current type full-bridge control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211744322U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769333A (en) * | 2020-12-31 | 2021-05-07 | 深圳市核达中远通电源技术股份有限公司 | Novel current type staggered PWM control circuit |
-
2019
- 2019-12-23 CN CN201922331134.2U patent/CN211744322U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769333A (en) * | 2020-12-31 | 2021-05-07 | 深圳市核达中远通电源技术股份有限公司 | Novel current type staggered PWM control circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101047356B (en) | Overcurrent detection circuit for electric machine driver | |
| CN100372221C (en) | Power circuit and PVVM circuit | |
| US9362823B2 (en) | Switch-mode power supply, charging current source and associated method | |
| CN1848683B (en) | Trianglar-wave generator and pulse-width modulation signal generating circuit containing the same | |
| CN205015388U (en) | Controllable formula low -voltage detection chip and power management chip delay | |
| CN104956580A (en) | Using synchronous converter in asynchronous mode to prevent current reversal during battery charging | |
| TW200424824A (en) | Switching voltage regulator and method for improving load transient efficiency | |
| CN211744322U (en) | Current type full-bridge control circuit | |
| CN202798435U (en) | High-performance and low-cost IGBT negative voltage bootstrap drive circuit | |
| CN112104203B (en) | Switch current-limiting circuit and power chip | |
| CN205015387U (en) | Anti -interference low -voltage detection chip | |
| CN105356564A (en) | Wireless energy receiving system | |
| CN112103920A (en) | DC/DC converter overcurrent protection circuit | |
| CN105305811A (en) | Charge pump drive circuit system for stepper motor | |
| CN108233690B (en) | Intelligent power module, air conditioner controller and air conditioner | |
| US8476942B2 (en) | Summation circuit in DC-DC converter | |
| CN203151079U (en) | Double-current loop protective circuit of limited current and excess current | |
| CN203278773U (en) | Square wave generation circuit, integrated circuit including same, DC/DC converter and AC/DC converter | |
| CN1938935A (en) | Power transistor protecting circuit of motor drive circuit, motor drive circuit, and semiconductor device | |
| CN107579648A (en) | A kind of inverse-excitation type switch power-supply and its control circuit | |
| CN218771776U (en) | Linear voltage reduction circuit and electronic equipment | |
| CN201956951U (en) | Multi-stage rotation speed control device for fan motor | |
| CN103187710A (en) | Current-limit and over-current double current loop protection circuit | |
| CN106787636A (en) | The synchronous commutating control circuit of compatible CCM mode of operations | |
| CN100557543C (en) | Two kinds of high-voltage constant current source circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |