CN211670840U - Clock switching circuit structure of satellite communication receiver - Google Patents
Clock switching circuit structure of satellite communication receiver Download PDFInfo
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- CN211670840U CN211670840U CN202020508443.2U CN202020508443U CN211670840U CN 211670840 U CN211670840 U CN 211670840U CN 202020508443 U CN202020508443 U CN 202020508443U CN 211670840 U CN211670840 U CN 211670840U
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Abstract
The utility model discloses a satellite communication receiver clock conversion circuit structure is including the frequency doubling circuit of connection at the signal access end, the frequency doubling circuit is including the input signal filter circuit who is used for filtering clock signal self higher harmonic who establishes ties in proper order, a first order amplifier circuit for amplifying the clock signal level, a diode bridge circuit for producing higher harmonic, a frequency-selective filter circuit for filtering unnecessary harmonic, a second grade amplifier circuit for improving clock signal drive power, frequency doubling circuit's output is connected with frequency division circuit, frequency division circuit is including being used for the D trigger that reduces the clock signal frequency according to the integer multiple, frequency division circuit's output is connected with the PLL circuit. The circuit structure can convert a standard satellite communication reference signal reference source into a frequency meeting special requirements, and has the advantages of small volume, low power consumption and high reliability.
Description
Technical Field
The utility model relates to the field of communication technology, concretely relates to satellite communication receiver clock conversion circuit structure.
Background
In a terrestrial application system for satellite communication, there are high demands for weight reduction, size reduction, and low power consumption, and strict design is required for each part of the system design, and a radio frequency front end includes parts such as an LNB, a BUC, and an antenna. The LNB mainly comprises a low noise amplifier, a down converter, a frequency synthesizer, an intermediate frequency amplifier and the like. By combining the requirements of miniaturization, low power consumption and high reliability required by a system, a down-conversion integrated chip integrating functions of a down converter, a frequency synthesizer, intermediate frequency amplification and the like is applied after the practical scheme is demonstrated and comprehensively considered.
Because of the special requirement of the chip, the input requirement of the frequency synthesizer part for the reference signal is not a 10MHz reference source used by standard satellite communication ground equipment, but a 15MHz reference source, so a signal conversion circuit is needed to be designed to extract the required frequency signal, and the reference input signal 10MHz is converted to meet the reference input used by PLL, thereby meeting the reference input requirement of the chip.
Disclosure of Invention
For overcoming prior art's not enough, the utility model provides a satellite communication receiver clock conversion circuit structure, it can change the satellite communication reference signal reference source of standard into the frequency that accords with special demand to small, low power dissipation, reliability are high.
For realizing the above-mentioned purpose, the utility model discloses a satellite communication receiver clock conversion circuit structure is including the frequency multiplier circuit who connects at the signal access end, frequency multiplier circuit is including the input signal filter circuit who is used for filtering clock signal self higher harmonic who establishes ties in proper order, a first order amplifier circuit for amplifying the clock signal level, a diode bridge circuit for producing higher harmonic, a frequency-selective filter circuit for filtering unnecessary harmonic, a second level amplifier circuit for improving clock signal drive power, frequency multiplier circuit's output is connected with frequency division circuit, frequency division circuit is including being used for the D trigger that reduces the clock signal frequency according to the integer multiple, frequency division circuit's output is connected with the PLL circuit.
Further, the input signal filter circuit comprises a first inductor, a second inductor and a third inductor which are sequentially connected in series, the input end of the first inductor is connected with a first resistor, the first resistor is grounded, a fifth inductor is connected between the first inductor and the second inductor, the other end of the fifth inductor is connected with a first capacitor in series, the first capacitor is grounded, a fourth inductor is connected between the second inductor and the third inductor, the other end of the fourth inductor is connected with a second capacitor in series, the second capacitor is grounded, the output end of the third inductor is connected with a second resistor, the second resistor is grounded, and the output end of the third inductor is connected with the first-stage amplifying circuit.
Furthermore, the diode bridge circuit is built by adopting a schottky diode, the diode bridge circuit comprises a first diode, a second diode, a third diode and a fourth diode, the cathode of the first diode is connected to the output end of the first amplifying circuit, the anode of the second diode is connected to the anode of the first diode, the cathode of the second diode is connected to the frequency-selecting filter circuit, the cathode of the first diode is connected to the anode of the third diode, the cathode of the third diode is connected to the cathode of the fourth diode, and the anode of the fourth diode is connected to the cathode of the second diode.
Furthermore, the frequency-selecting filter circuit comprises a third capacitor, a sixth inductor and a fourth capacitor which are sequentially connected in series, a fifth capacitor is connected in parallel at two ends of the sixth inductor, a sixth capacitor and a seventh capacitor are respectively connected to connection points at two ends of the sixth inductor and two ends of the fifth capacitor, the sixth capacitor and the seventh capacitor are grounded, a seventh inductor is connected between the third capacitor and the sixth capacitor, an eighth inductor is connected between the fourth capacitor and the seventh capacitor, and the seventh inductor and the eighth inductor are grounded.
Furthermore, the D trigger comprises a first-stage frequency-selecting filter, a CLK module and a second-stage frequency-selecting filter which are sequentially connected, wherein the output end of the first-stage frequency-selecting filter is connected to the input end of the CLK module, the D port of the CLK module is connected with the Q inverse port, and the Q port of the CLK module is connected to the second-stage frequency-selecting filter.
Furthermore, the output end of the second-stage frequency-selecting filter is connected with an amplifying unit.
The utility model discloses a satellite communication receiver clock conversion circuit structure can change the satellite communication reference signal reference source of standard into the frequency that accords with special demand to small, low power dissipation, reliability are high.
Drawings
The invention will be further described and illustrated with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of the whole structure of a clock conversion circuit of a satellite communication receiver according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of an input signal filter circuit;
fig. 3 is a schematic diagram for embodying a frequency selective filter circuit structure.
Reference numerals: 1. a frequency multiplier circuit; 11. an input signal filter circuit; 111. a first inductor; 112. a second inductor; 113. a third inductor; 114. a fourth inductor; 115. a fifth inductor; 116. a first resistor; 117. a second resistor; 118. a first capacitor; 119. a second capacitor; 12. a first stage amplification circuit; 13. a diode bridge circuit; 131. a first diode; 132. a second diode; 133. a third diode; 134. a fourth diode; 14. a frequency selective filter circuit; 141. a sixth inductor; 142. a seventh inductor; 143. an eighth inductor; 144. a third capacitor; 145. a fourth capacitor; 146. a fifth capacitor; 147. a sixth capacitor; 148. a seventh capacitance; 15. a second stage amplification circuit; 2. a frequency dividing circuit; 21. a first-order frequency-selective filter; 22. a CLK module; 23. a second-order frequency-selective filter; 24. an amplifying unit; 3. a PLL circuit.
Detailed Description
The technical solution of the present invention will be more clearly and completely explained by the description of the preferred embodiments of the present invention with reference to the accompanying drawings.
As shown in fig. 1, the clock conversion circuit structure of the satellite communication receiver according to the preferred embodiment of the present invention includes a frequency multiplier circuit 1 and a frequency divider circuit 2.
As shown in fig. 1, the frequency multiplier circuit 1 includes an input signal filter circuit 11, a first-stage amplifier circuit 12, a diode bridge circuit 13, a frequency-selective filter circuit 14, and a second-stage amplifier circuit 15, which are connected in series in this order.
As shown in fig. 2, the input signal filtering circuit 11 includes a first inductor 111, a second inductor 112, and a third inductor 113 connected in series in sequence, a first resistor 116 is connected to an input end of the first inductor 111, the first resistor 116 is grounded, a fifth inductor 115 is connected between the first inductor 111 and the second inductor 112, a first capacitor 118 is connected in series to the other end of the fifth inductor 115, the first capacitor 118 is grounded, a fourth inductor 114 is connected between the second inductor 112 and the third inductor 113, a second capacitor 119 is connected in series to the other end of the fourth inductor 114, the second capacitor 119 is grounded, a second resistor 117 is connected to an output end of the third inductor 113, a second resistor 117 is grounded, and an output end of the third inductor 113 is connected to the first-stage amplifying circuit 12.
The input signal filter circuit 11 is to filter the higher harmonics caused by the clock signal itself, and the first-stage amplifier circuit 12 is to ensure that the level of the clock signal can drive the threshold level of the diode bridge circuit 13, so as to ensure that the diode bridge circuit 13 can work normally.
As shown in fig. 1, the diode bridge circuit 13 is constructed by schottky diodes, the diode bridge circuit 13 includes a first diode 131, a second diode 132, a third diode 133 and a fourth diode 134, a cathode of the first diode 131 is connected to the output terminal of the first amplifying circuit, an anode of the second diode 132 is connected to the anode of the first diode 131, a cathode of the second diode 132 is connected to the frequency-selective filter circuit 14, a cathode of the first diode 131 is connected to the anode of the third diode 133, a cathode of the third diode 133 is connected to the cathode of the fourth diode 134, and an anode of the fourth diode 134 is connected to the cathode of the second diode 132.
It is known that when a sine wave signal passes through a nonlinear component, various new frequency signals, such as a fundamental wave signal, a harmonic signal, etc., are generated. The utility model discloses a through the nonlinearity of diode, produce the harmonic of octave, rethread frequency-selective filter circuit 14 extracts the signal that needs in the harmonic, sends next grade network after enlargiing. Based on miniaturized demand, according to the bridging form, the utility model discloses a low-cost HP company's HSMS series's of a section chip has been selected and has been designed. The chip is a bridge circuit built by Schottky diodes, is simple to apply and does not have a complex peripheral circuit.
As shown in fig. 3, the frequency-selective filter circuit 14 includes a third capacitor 144, a sixth inductor 141, and a fourth capacitor 145 that are sequentially connected in series, a fifth capacitor 146 is connected in parallel at two ends of the sixth inductor 141, a sixth capacitor 147 and a seventh capacitor 148 are respectively connected to connection points of two ends of the sixth inductor 141 and the fifth capacitor 146, the sixth capacitor 147 and the seventh capacitor 148 are grounded, a seventh inductor 142 is connected between the third capacitor 144 and the sixth capacitor 147, an eighth inductor 143 is connected between the fourth capacitor 145 and the seventh capacitor 148, and the seventh inductor 142 and the eighth inductor 143 are grounded.
The frequency-selective filter circuit 14 is designed to obtain a desired frequency, and since the frequency of the reference input signal is not high and the harmonic bandwidth is narrow, the frequency-selective filter circuit 14 is required to have a high suppression degree, and to suppress harmonics of other multiples, thereby avoiding introducing spurs. The second stage amplifying circuit 15 is to increase the driving power of the signal to meet the frequency dividing requirement.
The overall function of the frequency multiplier circuit 1 is to boost the integer multiple of the input frequency signal to generate a circuit with an output signal equal to the integer multiple of the input signal, such as the frequency multiplier circuit 1, the frequency tripler circuit 1, etc. Then, the required frequency is obtained through the frequency selecting filter circuit 14.
As shown in fig. 1, the frequency dividing circuit 2 includes a D flip-flop for reducing the frequency of the clock signal by an integer multiple, and an output terminal of the frequency dividing circuit 2 is connected to the PLL circuit 3. The D flip-flop comprises a first-stage frequency-selecting filter 21, a CLK module 22, a second-stage frequency-selecting filter 23 and an amplifying unit 24 which are connected in sequence, wherein the output end of the first-stage frequency-selecting filter 21 is connected to the input end of the CLK module 22, the D port of the CLK module 22 is connected with the Q-bar port, and the Q port of the CLK module 22 is connected to the second-stage frequency-selecting filter 23.
The frequency dividing circuit 2 is used for reducing the frequency of an input signal according to integral multiple, available integrated frequency dividing chips are available in the market at present, but the cost and the power consumption are increased by adopting the integrated frequency dividing chips. Therefore, the utility model discloses a D flip-flop circuit realizes the frequency halving. The input signal of the CLK module 22 is a frequency-multiplied and then filtered signal, and the output of the Q port is a two-frequency-divided signal. In order not to interfere with the main signal, a second-order frequency-selecting filter 23 is added after the output of the Q end, and other frequency division amounts are suppressed. Meanwhile, according to the requirements of the PLL and the requirements of the system on phase noise, the signal frequency division filtering can be selected and added into the amplifying unit 24 to meet the driving requirements of the PLL. The welding pattern of the amplification unit 24 may be reserved for a through channel at the time of a specific circuit design.
Verify according to actual circuit processing, confirmed wave filter simulation result, the utility model discloses a satellite communication receiver clock converting circuit structure can satisfy the demand that the PLL part consulted. In LNB system applications, the amplification unit 24 can be eliminated to further reduce system power consumption, depending on the phase noise requirements.
The above detailed description merely describes the preferred embodiments of the present invention and does not limit the scope of the present invention. Without departing from the design concept and spirit scope of the present invention, the ordinary skilled in the art should belong to the protection scope of the present invention according to the present invention provides the text description and drawings to the various modifications, replacements and improvements made by the technical solution of the present invention. The scope of protection of the present invention is determined by the claims.
Claims (6)
1. The utility model provides a satellite communication receiver clock conversion circuit structure, its characterized in that, is including the frequency doubling circuit who connects at the signal access end, the frequency doubling circuit is including the input signal filter circuit who is used for filtering clock signal self higher harmonic, the first order amplifier circuit who is used for amplifying the clock signal level, the diode bridge circuit who is used for producing higher harmonic that establish ties in proper order, the frequency selection filter circuit who is used for filtering unnecessary harmonic, the second order amplifier circuit who is used for improving clock signal drive power, the output of frequency doubling circuit is connected with frequency division circuit, frequency division circuit is including being used for the D trigger that reduces clock signal frequency according to the integer multiple, frequency division circuit's output is connected with the PLL circuit.
2. The clock conversion circuit structure of claim 1, wherein the input signal filtering circuit comprises a first inductor, a second inductor and a third inductor connected in series in sequence, a first resistor is connected to an input end of the first inductor, the first resistor is grounded, a fifth inductor is connected between the first inductor and the second inductor, a first capacitor is connected in series to the other end of the fifth inductor, the first capacitor is grounded, a fourth inductor is connected between the second inductor and the third inductor, a second capacitor is connected in series to the other end of the fourth inductor, the second capacitor is grounded, a second resistor is connected to an output end of the third inductor, the second resistor is grounded, and an output end of the third inductor is connected to the first-stage amplifying circuit.
3. The clock switching circuit structure of claim 1, wherein said diode bridge circuit is constructed by schottky diodes, said diode bridge circuit comprises a first diode, a second diode, a third diode and a fourth diode, a cathode of said first diode is connected to an output terminal of said first amplifying circuit, an anode of said second diode is connected to an anode of said first diode, a cathode of said second diode is connected to said frequency selective filter circuit, a cathode of said first diode is connected to an anode of said third diode, a cathode of said third diode is connected to a cathode of said fourth diode, and an anode of said fourth diode is connected to a cathode of said second diode.
4. The clock conversion circuit structure of a satellite communication receiver according to claim 1, wherein the frequency-selective filter circuit includes a third capacitor, a sixth inductor and a fourth capacitor connected in series in sequence, a fifth capacitor is connected in parallel to two ends of the sixth inductor, a sixth capacitor and a seventh capacitor are connected to connection points of two ends of the sixth inductor and the fifth capacitor respectively, the sixth capacitor and the seventh capacitor are grounded, a seventh inductor is connected between the third capacitor and the sixth capacitor, an eighth inductor is connected between the fourth capacitor and the seventh capacitor, and the seventh inductor and the eighth inductor are grounded.
5. The satellite communications receiver clock conversion circuit arrangement of claim 1, wherein said D flip-flop includes a first stage frequency selective filter, a CLK block, and a second stage frequency selective filter connected in series, an output of said first stage frequency selective filter being connected to an input of said CLK block, a D port of said CLK block being connected to a Q bar port, a Q port of said CLK block being connected to said second stage frequency selective filter.
6. The satellite communications receiver clock conversion circuit arrangement of claim 5, wherein an amplification unit is coupled to an output of said second stage frequency selective filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020508443.2U CN211670840U (en) | 2020-04-09 | 2020-04-09 | Clock switching circuit structure of satellite communication receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020508443.2U CN211670840U (en) | 2020-04-09 | 2020-04-09 | Clock switching circuit structure of satellite communication receiver |
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| Publication Number | Publication Date |
|---|---|
| CN211670840U true CN211670840U (en) | 2020-10-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020508443.2U Active CN211670840U (en) | 2020-04-09 | 2020-04-09 | Clock switching circuit structure of satellite communication receiver |
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| CN (1) | CN211670840U (en) |
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2020
- 2020-04-09 CN CN202020508443.2U patent/CN211670840U/en active Active
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Address after: Room 713a, building 1, 266 Chuangyan Road, Qilin hi tech Industrial Development Zone, Nanjing, Jiangsu 210000 Patentee after: Nanjing Houshi Electronic Technology Co., Ltd Address before: Room 713a, building 1, 266 Chuangyan Road, Qilin hi tech Industrial Development Zone, Nanjing, Jiangsu 210000 Patentee before: Nanjing Chuangji Information Technology Co.,Ltd. |
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