CN211378143U

CN211378143U - High-speed data acquisition system based on FPGA image processing card

Info

Publication number: CN211378143U
Application number: CN202020312710.9U
Authority: CN
Inventors: 甘留军; 廖恩红; 钟永成; 赵朝阳
Original assignee: Nexwise Intelligence China Ltd
Current assignee: Nexwise Intelligence China Ltd
Priority date: 2020-03-13
Filing date: 2020-03-13
Publication date: 2020-08-28
Anticipated expiration: 2030-03-13

Abstract

The utility model discloses a high-speed data acquisition system based on FPGA image processing card, this system includes the first FPGA chip of decoding chip and first camera through first video and being connected, decode the second FPGA chip that chip and second camera are connected through the second video, and the main FPGA chip of being connected through parallel bus and first FPGA chip and second FPGA chip, this main FPGA chip synthesizes the first way digital image signal and the second way digital image signal that first FPGA chip and second FPGA chip conveying come, main FPGA chip still is connected with the DSP treater, an image data for handling the main FPGA chip and obtaining packs and data receiving and dispatching, and be connected with the node host computer of arranging at the control crossing through the PCI bus interface of being connected with the DSP treater. The utility model discloses a high-speed data acquisition system synthesizes the two way digital image signal of first FPGA chip and second FPGA chip into all the way through main FPGA chip, has reduced the data volume greatly, has realized image data's high-speed collection and transmission.

Description

High-speed data acquisition system based on FPGA image processing card

Technical Field

The utility model relates to a road monitoring visual identification technical field, concretely relates to high-speed data acquisition system based on FPGA image processing card.

Background

Abnormal behaviors of vehicles and pedestrians are important causes of traffic accidents, and very important clues are provided for criminal investigation and case solving. The intelligent analysis and prediction of the behaviors of targets such as pedestrians and vehicles in the massive monitoring video data plays an important role in the public safety fields such as intelligent transportation and intelligent security, and the image acquisition and processing of the vehicles and the pedestrians are established on the premise. The intelligent traffic monitoring system is a main way for realizing intelligent traffic and intelligent security based on massive data acquisition and computer vision processing operation in the field of road monitoring depending on the development of machine vision and the updating of hardware technology. In this process, image data acquisition is a prerequisite for machine vision recognition by computers. The demand for real-time high-speed data acquisition is also increasing. In some high-speed and high-precision measurements such as signal measurement, image processing, audio signal processing, and the like, high-speed and high-precision data acquisition is required. This places two requirements on the design of the data acquisition system: on the one hand, the interface is required to be simple and flexible and have a high data transmission rate; on the other hand, the data volume is usually large, so that the host is required to be capable of quickly reacting to the data and analyzing and processing the data in time.

SUMMERY OF THE UTILITY MODEL

In order to solve the defects existing in the technology, the utility model provides a high-speed data acquisition system based on FPGA image processing card.

The utility model discloses realize that the technical scheme that above-mentioned technological effect adopted is:

a high-speed data acquisition system based on an FPGA image processing card comprises:

the first FPGA chip is connected with the first camera through a first video decoding chip, and the first video decoding chip converts the video analog signal collected by the first camera into a first path of digital image signal;

the second FPGA chip is connected with the second camera through a second video decoding chip, and the second video decoding chip converts the video analog signals collected by the second camera into a second path of digital image signals;

the main FPGA chip is connected with the first FPGA chip and the second FPGA chip through a parallel bus and synthesizes a first path of digital image signal and a second path of digital image signal transmitted by the first FPGA chip and the second FPGA chip;

and the DSP processor is connected with the main FPGA chip, packages and receives and transmits the image data processed by the main FPGA chip, and is connected with the node host arranged at the monitoring intersection through a PCI bus interface connected with the DSP processor.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the first FPGA chip and the second FPGA chip are both connected to an SRAM memory 1 and an SRAM memory 2, so as to perform read-write operation in a "ping-pong mode".

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the first camera and the first video decoding chip are connected sequentially through a first low-pass filter and a first 1/8 analog signal selector, the first low-pass filter is used for performing high-frequency denoising on 8 channels of video analog input signals of the first camera, and the first 1/8 analog signal selector controls the first 1/8 analog signal selector to gate 1 channel of the 8 channels of input signals to an output end according to an address code from the first FPGA chip, and sends the signal to the first video decoding chip to convert the input 1 channel of analog signals into digital signals.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the second camera and the second first video decoding chip are sequentially connected through a second low-pass filter and a second 1/8 analog signal selector, the second low-pass filter is used for performing high-frequency denoising on 8 channels of video analog input signals of the second camera, and the second 1/8 analog signal selector controls the second 1/8 analog signal selector to gate 1 channel of the 8 channels of input signals to an output end according to an address code from the second FPGA chip, and sends the selected channel of input signals to the second video decoding chip to convert the input 1 channel of analog signals into digital signals.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the image data bus, the frame image data clock port, the frame synchronization signal port, and the line synchronization signal port of the first video decoding chip are respectively connected to the first FPGA chip, and the image data bus, the frame image data clock port, the frame synchronization signal port, and the line synchronization signal port of the second video decoding chip are respectively connected to the second FPGA chip.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the node host disposed at the monitoring intersection is connected to the PCI bus interface through a PCI bus, and the node host disposed at the monitoring intersection is connected to the cluster server at the rear end through light.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the first FPGA chip, the second FPGA chip, and the main FPGA chip are all CycIone series FPGA chips with model number EP1C3T 144.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the first video decoding chip and the second video decoding chip are video decoding chips with model number LSI-MB86H 60.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the DSP processor is a digital signal processor with a model number of TMs320VC5416, and the PCI bus interface includes a PCI bus interface chip with a model number of PCI 9054.

Preferably, in the high-speed data acquisition system based on the FPGA image processing card, the high-speed data acquisition system is arranged on a light pole of the municipal administration monitoring intersection.

The utility model has the advantages that: the utility model discloses a high-speed data acquisition system adopts the multi-standard of double-circuit to carry out synchronous acquisition to the video analog signal of two cameras, video decoding chip through connecting separately carries out analog-to-digital conversion to this way video analog signal, convert standard 8bit digital image signal into, two way digital image signal do not convert the image signal of RGB format into through the FPGA chip that corresponds again, synthesize through main FPGA chip at last and be all the way, the size of image data has been reduced greatly, carry out data arrangement through the DSP treater again, the mark, packing and data preprocessing, make the FPGA chip can be absorbed in the leading discernment processing who accomplishes the image, the data acquisition speed and the operational capability of system have been improved, be connected at the node host computer of control crossing with arranging through PCI bus interface, can further improve the transmission speed of data.

Drawings

Fig. 1 is a block diagram of the present invention;

fig. 2 is a connection block diagram of the first camera and the first video decoding chip of the present invention;

fig. 3 is a connection block diagram of the second camera and the second video decoding chip of the present invention;

fig. 4 is the connection block diagram of the main FPGA chip and the first FPGA chip of the present invention.

Detailed Description

For a further understanding of the invention, reference is made to the following description taken in conjunction with the accompanying drawings and specific examples, in which:

in the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

As shown in fig. 1, the embodiment of the utility model provides a high-speed data acquisition system based on FPGA image processing card, this data acquisition system include first FPGA chip, second FPGA chip, main FPGA chip and DSP treater. The first FPGA chip is connected with a first camera through a first video decoding chip, and the first video decoding chip is used for converting video analog signals collected by the first camera into a first path of digital image signals. The second FPGA chip is connected with a second camera through a second video decoding chip, and the second video decoding chip converts the video analog signals collected by the second camera into a second path of digital image signals. The main FPGA chip is connected with the first FPGA chip and the second FPGA chip through a parallel bus and used for synthesizing the first path of digital image signal and the second path of digital image signal transmitted by the first FPGA chip and the second FPGA chip. And the DSP processor is connected with the main FPGA chip and is used for packaging and receiving and transmitting the image data processed by the main FPGA chip. The DSP processor is connected with a PCI bus interface, and the PCI bus interface is connected with a node host arranged at the monitoring intersection through a PCI bus. The utility model discloses a high-speed data acquisition system adopts the multi-standard of double-circuit to carry out synchronous acquisition to the video analog signal of two cameras, video decoding chip through connecting separately carries out analog-to-digital conversion to this way video analog signal, convert standard 8bit digital image signal into, two way digital image signal do not convert the image signal of RGB format into through the FPGA chip that corresponds again, synthesize through main FPGA chip at last and be all the way, the size of image data has been reduced greatly, carry out data arrangement through the DSP treater again, the mark, packing and data preprocessing, make the FPGA chip can be absorbed in the leading discernment processing who accomplishes the image, the data acquisition speed and the operational capability of system have been improved, be connected at the node host computer of control crossing with arranging through PCI bus interface, can further improve the transmission speed of data.

Further, in the preferred embodiment of the present invention, the first FPGA chip and the second FPGA chip are both connected to the SRAM memory 1 and the SRAM memory 2, which perform read-write operations in the "ping-pong mode". As shown in fig. 4, it is a connection block diagram of the main FPGA chip and the first FPGA chip. The SRAM memory 1 and the SRAM memory 2 of the first FPGA chip provide double buffering functions of data input/output, and play roles in preventing data overflow and ensuring continuity of data transmission. The SRAM memory 1 and the SRAM memory 2 constitute a storage buffer for data transfer. The two SRAMs are used for executing the ping-pong mode read-write operation, the cost is low, the capacity is large, the operation is simple, and the image data buffering function can be completed. The SRAM memory 1 and the SRAM memory 2 are static memories with the model number of IDT71V416, the capacity of 256 Kxl6 bit and the access speed of 10 ns, and a 256 Kxl6 bit x2=8 Mbit cache can be formed by using two pieces of SRAM, so that uninterrupted transmission of image data can be realized.

Further, in the preferred embodiment of the present invention, as shown in fig. 2 and fig. 3, the first camera and the first video decoding chip are connected to the first 1/8 analog signal selector sequentially through the first low pass filter, and the first low pass filter is used to perform high frequency denoising on the 8 channels of video analog input signals of the first camera. The first 1/8 analog signal selector controls the first 1/8 analog signal selector to select 1 of the 8 inputs to the output end according to the address code from the first FPGA chip, and sends the selected 1 input analog signal to the first video decoding chip to be converted into a digital signal. The second camera and the second first video decoding chip are connected through a second low-pass filter and a second 1/8 analog signal selector in sequence, and the second low-pass filter is used for carrying out high-frequency denoising on 8 paths of video analog input signals of the second camera. The second 1/8 analog signal selector controls the second 1/8 analog signal selector to select 1 of the 8 inputs to the output end according to the address code from the second FPGA chip, and sends the selected 1 input analog signal to the second video decoding chip to be converted into a digital signal. In the preferred embodiment of the present invention, the first low pass filter and the second low pass filter both adopt the anti-aliasing low pass filter with the model number of THS4052 for removing the high frequency component of the 8-channel video analog input signals of the first camera and the second camera, and preventing the signals from generating the "aliasing phenomenon". The first 1/8 analog signal selector and the second 1/8 analog signal selector each employ an analog signal selector model 74HC 4051.

Further, in the preferred embodiment of the present invention, the image data bus, the frame image data clock port, the frame synchronization signal port, and the line synchronization signal port of the first video decoding chip are respectively connected to the first FPGA chip, and the image data bus, the frame image data clock port, the frame synchronization signal port, and the line synchronization signal port of the second video decoding chip are respectively connected to the second FPGA chip. The node host arranged at the monitoring intersection is connected with the PCI bus interface through the PCI bus, and the node host arranged at the monitoring intersection is connected with the cluster server at the rear end through light rays. In the preferred embodiment of the utility model, first FPGA chip, second FPGA chip and main FPGA chip all adopt CycIone series's model to be EP1C3T 144's FPGA chip, and first video decoding chip and second video decoding chip all adopt the model to be LSI-MB86H 60's video decoding chip. The DSP processor adopts a digital signal processor with the model of TMs320VC5416, and the PCI bus interface comprises a PCI bus interface chip with the model of PCI 9054. The utility model discloses a high-speed data acquisition system sets up on the light pole at municipal administration control crossing, and each high-speed data acquisition system still accomplishes video analog signal's digital image fusion processing through FPGA chip wherein and DSP treater when accomplishing many cameras tracking shooting, has improved the data acquisition speed and the operational capability of system.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, but rather is described in the foregoing embodiments and the description with reference to the principles of the invention and that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that all such changes and modifications fall within the scope of the invention as claimed, which is defined by the claims appended hereto and their equivalents.

Claims

1. A high-speed data acquisition system based on FPGA image processing card, characterized by that, includes:

2. The high-speed data acquisition system based on the FPGA image processing card as claimed in claim 1, wherein the first FPGA chip and the second FPGA chip are both connected with an SRAM memory 1 and an SRAM memory 2 for performing read-write operation in a ping-pong mode.

3. The high-speed data acquisition system based on the FPGA image processing card according to claim 1, wherein the first camera and the first video decoding chip are connected to each other through a first low pass filter and a first 1/8 analog signal selector in sequence, the first low pass filter is configured to perform high-frequency denoising on 8 channels of video analog input signals of the first camera, and the first 1/8 analog signal selector controls the first 1/8 analog signal selector to gate 1 channel of the 8 channels of inputs to an output terminal according to an address code from the first FPGA chip, and sends the selected channel of input analog signals to the first video decoding chip to convert the input 1 channel of analog signals into digital signals.

4. The high-speed data acquisition system based on the FPGA image processing card according to claim 3, wherein the second camera and the second video decoding chip are sequentially connected through a second low pass filter and a second 1/8 analog signal selector, the second low pass filter is used for performing high-frequency denoising on 8 channels of video analog input signals of the second camera, and the second 1/8 analog signal selector controls the second 1/8 analog signal selector to gate 1 channel of the 8 channels of input signals to the output end according to an address code from the second FPGA chip, and sends the selected channel of input signals to the second video decoding chip to convert the input 1 channel of analog signals into digital signals.

5. The high-speed data acquisition system based on the FPGA image processing card according to claim 1, wherein an image data bus, a frame image data clock port, a frame synchronization signal port, and a line synchronization signal port of the first video decoding chip are respectively connected to the first FPGA chip, and an image data bus, a frame image data clock port, a frame synchronization signal port, and a line synchronization signal port of the second video decoding chip are respectively connected to the second FPGA chip.

6. The high-speed data acquisition system based on the FPGA image processing card as claimed in claim 1, wherein the node host arranged at the monitoring intersection is connected with the PCI bus interface through a PCI bus, and the node host arranged at the monitoring intersection is connected with a cluster server at the rear end through light.

7. The FPGA-image-processing-card-based high-speed data acquisition system according to claim 1, wherein the first FPGA chip, the second FPGA chip and the main FPGA chip are all CycIone-series FPGA chips with model number EP1C3T 144.

8. The high-speed data acquisition system based on the FPGA image processing card as recited in claim 1, wherein the first video decoding chip and the second video decoding chip are video decoding chips with model number LSI-MB86H 60.

9. The high-speed data acquisition system based on the FPGA image processing card as claimed in claim 1, wherein the DSP processor is a digital signal processor with a model of TMs320VC5416, and the PCI bus interface comprises a PCI bus interface chip with a model of PCI 9054.

10. The FPGA image processing card-based high-speed data acquisition system as recited in claim 1, wherein the high-speed data acquisition system is disposed on a light pole of a municipal monitoring intersection.