CN209046794U

CN209046794U - A kind of Real-time Image Collecting System

Info

Publication number: CN209046794U
Application number: CN201822248961.0U
Authority: CN
Inventors: 洪亚德; 王士奇; 赖达炜
Original assignee: G-FIRST OEIC Co Ltd
Current assignee: G-FIRST OEIC Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-06-28
Anticipated expiration: 2028-12-29

Abstract

The utility model discloses a kind of Real-time Image Collecting Systems, including CCD camera, A/D conversion module, synchronizing signal separator, FPGA module, the first SRAM, the 2nd SRAM, image compression module and DSP module；The CCD camera, A/D conversion module and FPGA module are sequentially connected, the CCD camera, synchronizing signal separator and FPGA module are sequentially connected, first SRAM module is connected with the FPGA module respectively with the second SRAM module, described image compression module is made of 4 picture compression chips, and the 4 picture compression chip is two-by-two in groups.The FPGA module, image compression module and DSP module are connected with each other.The utility model carries out function division from data processing angle first, using FPGA module as image preprocessing, post-processing and main control module, the compression processing of image is carried out using image compression module sole duty, the processing such as image encryption and distribution is carried out using DSP module, Each performs its own functions for each module, provides processing speed, and be all made of the storage of " table tennis " pattern switching in image preprocessing and compression of images link, data-handling efficiency is improved, real-time is improved.

Description

A kind of Real-time Image Collecting System

Technical field

The utility model relates to Image Acquisition fields, and in particular to a kind of Real-time Image Collecting System.

Background technique

With the development of digital multimedia technology and machine vision technique, image collection processing system is in industry, military, peace The every field such as anti-, which suffer from, to be extremely widely applied.

Current image capturing system is mainly divided to two kinds:

1, acquisition is only responsible in front end, and acquired image turns to be handled by the rear end end PC；

2, front end is not only responsible for acquiring, and is also responsible for the processing to image data.

With the extension that Image Acquisition is applied, such as mobile robot field, its drawback of the first image capturing system Gradually highlight, meanwhile, second of image capturing system has welcome bigger challenge, when facing video image or high-definition image, It brings bigger processing real-time and transmission real-time challenge.

Utility model content

The purpose of this utility model is to provide a kind of Real-time Image Collecting Systems.

To achieve the above object, the utility model uses following technical scheme:

A kind of Real-time Image Collecting System, including CCD camera, A/D conversion module, synchronizing signal separator, FPGA mould Block, the first SRAM, the 2nd SRAM, image compression module and DSP module；The CCD camera, A/D conversion module and FPGA mould Block is sequentially connected, and the CCD camera, synchronizing signal separator and FPGA module are sequentially connected, first SRAM module with Second SRAM module is connected with the FPGA module respectively, the FPGA module, image compression module and DSP module phase each other Even.

Further, described image compression module is made of 4 picture compression chips, the 4 picture compression chip two Two in groups.

Further, the FPGA module is separately connected two groups of image compression chips by two sets of VDATA buses；Institute It states two groups of image compression chips and HDATA bus and the ADDR bus connection DSP module is respectively adopted；The DSP module passes through EMIF interface connects the FPGA module.

Further, the FPGA module uses XC3S500E array, and described image compression chip uses ADV212 chip, The DSP module uses TMS320C6416 chip.

Further, the A/D conversion module uses TLC5510 chip, and the synchronizing signal separator uses LM1881 Chip.

It further, further include the USB main interface being connected respectively with the FPGA module and USB from interface, the USB master The transmission rate of interface is lower than the USB from interface.

Further, the USB main interface uses SL811HST chip, and the USB uses CY7C68001 core from interface Piece.

It further, further include the gigabit ethernet transceiver being connected with the FPGA module.

After adopting the above technical scheme, the utility model compared with the background art, has the advantages that

1, the utility model carries out function division from data processing angle first, is located in advance using FPGA module as image Reason, post-processing and main control module, the compression processing of image is carried out using image compression module sole duty, is carried out using DSP module The processing such as image encryption and distribution, Each performs its own functions for each module, processing speed is provided, simultaneously as FPGA module is related to image Pretreatment, image preprocessing has the characteristics that data throughout is big, therefore is configured with the first SRAM module and second for it SRAM module, two panels SRAM module improve data-handling efficiency with the storage of " table tennis " pattern switching.

2, image compression module described in the utility model is realized in groups two-by-two using 4 picture compression chips, same Continuous-flow type compression is carried out to by pretreated image data with " table tennis " mode, improves compression of images rate, and then improve The transmission rate of image.

3, the utility model provides a variety of with external device communication interface, the USB main interface for realizing with it is outer Portion stores the data interaction of equipment (mobile hard disk etc.), improves the portability of data；The USB from interface for realizing with local The data interaction of machine, the gigabit ethernet transceiver is for realizing the data interaction with long-range host computer.

Detailed description of the invention

Fig. 1 is Tthe utility model system block diagram.

Specific embodiment

In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain The utility model is not used to limit the utility model.

In the present invention it should be noted that term " on " "lower" " left side " " right side " "vertical" "horizontal" "inner" "outside" etc. It is to be based on the orientation or positional relationship shown in the drawings, it is only for convenient for description the utility model and simplify description, without It is that the device of indication or suggestion the utility model or element must have a particular orientation, therefore should not be understood as practical new to this The limitation of type.

Embodiment

It please refers to shown in Fig. 1, the utility model discloses a kind of Real-time Image Collecting Systems, including CCD camera, A/D Conversion module, synchronizing signal separator, FPGA module, the first SRAM, the 2nd SRAM, image compression module and DSP module.

Wherein, the CCD camera, A/D conversion module and FPGA module are sequentially connected, the CCD camera, synchronous letter Number separator and FPGA module are sequentially connected, first SRAM module and the second SRAM module respectively with the FPGA module phase Even, the FPGA module, image compression module and DSP module are connected with each other.

In this way, the FPGA module is equipped with two SRAM modules, then when carrying out Image Acquisition, i.e., available " ping pong scheme " is cut Change storage.Two panels SRAM is selected by tri-state gate, and when No. the 1st imaging sensor output data, image data is cached to the One SRAM；When No. the 2nd imaging sensor output data, switched by tri-state gate, by data buffer storage into the 2nd SRAM；3rd time When imaging sensor output data, switched by tri-state gate, by data buffer storage into the first SRAM, such as a little circulations realize table tennis behaviour Make, improves speed.

Similarly, in the present embodiment, described image compression module is made of 4 picture compression chips, the 4 picture compression Chip is two-by-two in groups.

The function that the overall performance of image capturing system cannot only consider used device and be completed, it is also necessary to comprehensive The interface form considered between each device is closed, prevents data transmission bottle neck from occurring between each core component.In the present embodiment, The FPGA module is separately connected two groups of image compression chips by two sets of VDATA buses；Two groups of image compressed cores HDATA bus is respectively adopted in piece and ADDR bus connects the DSP module；The DSP module passes through described in the connection of EMIF interface FPGA module, to realize the seamless interfacing between each core component.In view of this, the FPGA module uses in the present embodiment XC3S500E array, described image compression chip use ADV212 chip, and the DSP module uses TMS320C6416 chip.

In the present embodiment, the A/D conversion module uses TLC5510 chip, and the synchronizing signal separator uses LM1881 chip.The synchronizing signal separator acquires synchronization signal to FPGA module, the FPGA module from analog signal Control A/D conversion module carries out data acquisition accordingly.This kind of combination both ensure that structure was simple, be easy to the characteristics of developing, But also with stronger versatility.

Preferably, the utility model further includes the USB main interface being connected respectively with the FPGA module and USB from interface, The transmission rate of the USB main interface is lower than the USB from interface.In the present embodiment, the USB main interface uses SL811HST Chip, from interface as the communication bridge between image capturing system and PC, rate is straight by full speed 12Mbps, the USB It connects the overall performance of influence system, in the present embodiment, uses CY7C68001 chip, high-speed mode 480Mbps.

Meanwhile in order to realize remote transmission function, in the present embodiment, Real-time Image Collecting System further includes and the FPGA The connected gigabit ethernet transceiver of module.

The preferable specific embodiment of the above, only the utility model, but the protection scope of the utility model is not It is confined to this, anyone skilled in the art within the technical scope disclosed by the utility model, can readily occur in Change or replacement, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should It is subject to the protection scope in claims.

Claims

1. a kind of Real-time Image Collecting System, it is characterised in that: including CCD camera, A/D conversion module, synchronization signal separation Device, FPGA module, the first SRAM, the 2nd SRAM, image compression module and DSP module；The CCD camera, A/D conversion module And FPGA module is sequentially connected, and the CCD camera, synchronizing signal separator and FPGA module are sequentially connected, and described first SRAM module is connected with the FPGA module respectively with the second SRAM module, the FPGA module, image compression module and DSP mould Block is connected with each other.

2. a kind of Real-time Image Collecting System as described in claim 1, it is characterised in that: described image compression module is by 4 Image compression chip composition, the 4 picture compression chip is two-by-two in groups.

3. a kind of Real-time Image Collecting System as claimed in claim 2, it is characterised in that: the FPGA module passes through two sets VDATA bus is separately connected two groups of image compression chips；Two groups of image compression chips be respectively adopted HDATA bus and ADDR bus connects the DSP module；The DSP module connects the FPGA module by EMIF interface.

4. a kind of Real-time Image Collecting System as claimed in claim 3, it is characterised in that: the FPGA module uses XC3S500E array, described image compression chip use ADV212 chip, and the DSP module uses TMS320C6416 chip.

5. a kind of Real-time Image Collecting System as claimed in claim 4, it is characterised in that: the A/D conversion module uses TLC5510 chip, the synchronizing signal separator use LM1881 chip.

6. a kind of Real-time Image Collecting System as described in claim 1, it is characterised in that: further include respectively with the FPGA mould From interface, the transmission rate of the USB main interface is lower than the USB from interface by the connected USB main interface of block and USB.

7. a kind of Real-time Image Collecting System as claimed in claim 6, it is characterised in that: the USB main interface uses SL811HST chip, the USB use CY7C68001 chip from interface.

8. a kind of Real-time Image Collecting System as described in claim 1, it is characterised in that: further include and the FPGA module phase Gigabit ethernet transceiver even.