CN102801948B - High-definition serial digital interface data transfer device and device - Google Patents
High-definition serial digital interface data transfer device and device Download PDFInfo
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Abstract
The present invention is applicable to safety monitoring technical field, a kind of HD-SDI data transfer device and device are provided, described method comprises: write in high-order brightness buffer memory by the most-significant byte of the brightness Y data in the video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys; The chrominance C b data of half line number in described video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, second half line number chrominance C r data are deleted, chrominance C b data most-significant byte writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys; By in the video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory.By under the prerequisite that present invention can be implemented in not compressed video data, HD video data are transmitted by gigabit Ethernet, enriched the solution of HD video transmission.
Description
Technical field
The invention belongs to safety monitoring technical field, particularly relate to a kind of high-definition serial digital interface data transfer device and device.
Background technology
In protection and monitor field, along with the development of Video Supervision Technique, video monitoring system requires that high Qinghua, digitized trend are more and more obvious.Serial digital interface (SerialDigitalInterface, SDI) be organize a kind of video interface standard system of working out by SMPTE, its interface is mainly used to transmit incompressible digital video signal, is widely used in other relevant industries such as radio and television at present.High-definition serial digital interface (High-definitionSerialDigitalInterface, HD-SDI) SMPTE274M standard and SMPTE292M standard is met, supporting the video signal transmission speed of 1.485Gb/s and 1.485/1.001Gb/s, can transmitting image resolution be the high clear video image of 1920 × 1080.Relative to other high definition video interface, HD-SDI has transmission range length, supports that uncompressed digital video signal, equipment connection can realize the advantages such as smooth upgrade.Typical non-compression video supervisory control system is divided into front-end collection (video camera), transmission (video optical multiplexer) haply, exchanges (video matrix), stores several major part such as (disk array) and display (video wall).The HD video video camera of current support HD-SDI interface is day by day universal, but the solution of HD video transmission corresponding with it and switching part is also more single.
Existing HD-SDI video optical multiplexer is a kind of simple video signal transmission equipment, itself does not have the function of exchange of vision signal.In actual applications, HD-SDI video optical multiplexer often needs to coordinate the high-definition video matrix of same support HD-SDI interface to realize exchange and the control of high-definition digital video signal.Present case it is possible to manufacture supports that the producer of the high-definition video matrix of HD-SDI interface is also fewer, and equipment price is expensive.The exchange agreement that the high-definition video matrix of each manufacturer production adopts producer privately owned mostly, the video monitoring platform built with this certainly exists the shortcoming of system compatibility difference.
In order to address this problem, the high-definition serial digital interface data that high-definition camera can be collected at present, after meeting and carrying out high compression ratio coding under Internet Transmission requirement technical indicator, be packaged into Ethernet data bag again and carry out Internet Transmission, can conveniently utilize existing ethernet switch technology to realize video data exchange and control, but HD-SDI data unavoidably reduce video quality after compressed encoding, cannot really realize video data Lossless transport.
Summary of the invention
In view of the above problems, the invention provides a kind of high-definition serial digital interface data transfer device, be intended to solve the technical problem that the existing technical scheme transmitted again after compressed encoding HD-SDI data reduces video quality.
The present invention is achieved in that the YCbCr video data this respect converting parallel 4:2:0 from the YCbCr video data of parallel 4:2:2 to, and a kind of high-definition serial digital interface data transfer device provided by the invention, comprises the steps:
The most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2 is write in high-order brightness buffer memory, in low 2 write low level brightness buffer memorys;
The chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
By in the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory.
From another point of view, convert the YCbCr video data this respect of parallel 4:2:0 from the YCbCr video data of parallel 4:2:2 to, a kind of high-definition serial digital interface data transfer device provided by the invention, comprises the steps:
The most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
By interval for brightness Y address corresponding for the write of the brightness Y data of described YCbCr video data;
A line video data of chrominance C b data will be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
Another object of the present invention is to provide a kind of high-definition serial digital interface DTU (Data Transfer unit), corresponding, from one side, described device comprises:
Brightness data writing unit, for writing in high-order brightness buffer memory by the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys;
Chroma data writing unit, for the chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
Data storage cell, for writing the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory in memory.
From another point of view, described device comprises:
Data buffer storage unit, for the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
Brightness address space writing unit, for the brightness Y address interval by the brightness Y data of described YCbCr video data write correspondence;
Colourity address space writing unit, for will a line video data of chrominance C b data be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
Pass through technique scheme, the invention has the beneficial effects as follows: the present invention removes a part of chroma data in the YCbCr video data of parallel 4:2:2, convert the YCbCr video data of parallel 4:2:0 to, data total amount is reduced, can transmit in gigabit Ethernet, at opposite side, chrominance C b data in the YCbCr video data of parallel 4:2:0 and chrominance C r data are compensated mutually, make it possible to the YCbCr video data reverting to parallel 4:2:2, can realize like this under the prerequisite of not compressed video data, HD video data being transmitted by gigabit Ethernet, enrich the solution of HD video transmission, ripe ethernet technology can be utilized to complete exchange to HD video data and control simultaneously, improve the system compatibility of video monitoring platform, and compared with existing data compression scheme, the loss of technical solution of the present invention to HD video data is less, time delay is also less.
Accompanying drawing explanation
Fig. 1 is HD video data Ethernet frame basic format schematic diagram;
Fig. 2 is the flow chart of a kind of high-definition serial digital interface data transfer device that first embodiment of the invention provides;
Fig. 3 is the flow chart of a kind of high-definition serial digital interface data transfer device that second embodiment of the invention provides;
Fig. 4 is the HD video transmitting data stream form schematic diagram specified in SMPTE292M standard;
Fig. 5 is the flow chart of a kind of high-definition serial digital interface data transfer device that third embodiment of the invention provides;
Fig. 6 is the flow chart of a kind of high-definition serial digital interface data transfer device that fourth embodiment of the invention provides;
Fig. 7 is the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that fifth embodiment of the invention provides;
Fig. 8 is the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that sixth embodiment of the invention provides;
Fig. 9 is the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that seventh embodiment of the invention provides;
Figure 10 is the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that eighth embodiment of the invention provides;
Figure 11 is the schematic diagram of road HD-SDI HD video transmission system on gigabit Ethernet that ninth embodiment of the invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The data bandwidth of one road HD-SDI high-definition digital video signal is 1.485Gbps, if do not processed it, cannot carry out carrying transmission with a road gigabit Ethernet passage.And thought Shi Jiang mono-road of the present invention walks abreast, the YCbCr video data of 4:2:2, under the prerequisite not affecting video quality, converts the YCbCr video data of the parallel 4:2:0 being less than 1Gbps to, makes it possible to carry out transfer of data in a gigabit Ethernet passage.
From realizing principle, when one frame HD-SDI high clear video image resolution is 1920 × 1080, frame per second per second is 30, after removing the invalid datas such as video blanking, due in the YCbCr video image of 4:2:2, average each pixel 2 sample values, the precision of each sample value is 10bit, and therefore, the total valid data amount of HD video is:
1920×1080×2×30×10bit＝1.24416Gbits
If converted to the YCbCr video data of 4:2:0 by the YCbCr video data of 4:2:2 to effective video data, altogether decrease the chroma data of half, the video data volume generally after conversion only has 3/4 before conversion, and the video data volume therefore after conversion is:
1.24416Gbit×3/4＝933.12Mbits
Conveniently deposit data and reading, if every 10bit video data be divided into most-significant byte and low 2 storages and read, for a line HD video data after conversion, comprise the most-significant byte monochrome information of 1920 bytes, the most-significant byte chrominance information of 960 bytes, and 720 low 2 blended data information of byte, comprise low 2 monochrome informations and chrominance information, total amount of data exceedes maximum load 1478 byte of Ethernet bag, therefore a line HD video data are needed to be divided into multiple Ethernet data bag to transmit, suppose to transmit with 3 Ethernet data bags, the most-significant byte data one of monochrome information and chrominance information reinstate 2 Ethernet data bag transmission, the blended data of low 2 is transmitted with an Ethernet data bag separately, therefore most-significant byte data are on average every
(1920+1920/2)/2＝1440Bytes
The Ethernet data payload package of low 2 blended datas is:
(1920+1920/2)*2/8＝720Bytes
All be less than the maximum load of Ethernet data bag, meet transmission requirement.
HD video valid data are carried out encapsulation packing according to ethernet frame format, and as shown in Figure 1, the bandwidth of the so actual Ethernet utilized is:
The YCbCr video data of the parallel 4:2:0 therefore after conversion can transmit on a gigabit Ethernet line, therefore demonstrates the present invention feasible know-why.
In order to data conversion technique scheme of the present invention is described, be described below by specific embodiment.
embodiment one:
Fig. 2 shows the flow process of a kind of high-definition serial digital interface data transfer device that first embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
The embodiment of the present invention converts this side of YCbCr video data of parallel 4:2:0 to describe technical scheme of the present invention from the YCbCr video data of parallel 4:2:2, comprising:
Step S201, the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2 is write in high-order brightness buffer memory, in low 2 write low level brightness buffer memorys;
Step S202, the chrominance C b data of half line number in described YCbCr video data to be deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
Above-mentioned two steps achieve the every data line by reading in the YCbCr video data of parallel 4:2:2, and brightness data and chroma data are write in corresponding buffer memory, two steps in no particular order.The embodiment of the present invention distributes 4 RAM buffer memorys for storing brightness data and chroma data, is respectively high-order brightness RAM buffer memory, low level brightness RAM buffer memory, high-order colourity RAM buffer memory, low level colourity RAM buffer memory.Concrete, owing to only relating to chroma data in video data transfer process, therefore when reading brightness data, directly the most-significant byte of brightness data is write in high-order brightness RAM buffer memory, low 2 write low level brightness RAM buffer memorys, for chroma data, comprise chrominance C b data and chrominance C r data, remove the chrominance C b data of wherein half line number, and the most-significant byte of chrominance C r data is write in high-order colourity RAM buffer memory, in low 2 bit data write low level colourity buffer memorys, again the chrominance C r data of second half line number are deleted, and the most-significant byte of chrominance C b data is write in high-order colourity RAM buffer memory, in low 2 bit data write low level colourity RAM buffer memorys.
Step S203, by the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory in.
Described 4 RAM buffer memorys are used as buffer memory brightness data and chroma data, as a kind of implementation, described 4 RAM buffer memorys can buffer memory 2 row HD video data, after one group of data encasement, can by the YCbCr video data of ready 4:2:0 write memory, described memory can select various storage medium, adopts SDRAM in the embodiment of the present invention.
Be further used as preferred embodiment, considering effective YCbCr video data, the HD video book that can obtain for lining by line scan, also can be interleaved HD video data, if current YCbCr video data is the HD video data of lining by line scan, then above-mentioned steps S102 is specially:
Chrominance C b data in wherein odd-numbered line are deleted, the most-significant byte of chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in even number line are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
If current YCbCr video data is interleaved HD video data, then above-mentioned steps S102 is specially:
Chrominance C b data in the odd-numbered line of odd field and the even number line of even field are deleted, the most-significant byte of chrominance C r data chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in the even number line of odd field and the odd-numbered line of even field are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
This preferred implementation considers the different video format of video data, and be to line by line scan or interlacing scan carries out corresponding conversion to video data according to video data, when be line by line scan time, judge video data line number, for odd-numbered line, delete chrominance C b data, by in the most-significant byte of chrominance C r data write most-significant byte colourity RAM buffer memory, in low 2 write low level colourity RAM buffer memorys, and the chrominance C r data in even number line are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys; When being interlacing scan, chrominance C b data in the odd-numbered line of odd field and the even number line of even field are deleted, the most-significant byte of chrominance C r data chrominance C r data writes in high-order colourity RAM buffer memory, in low 2 bit data write low level colourity RAM buffer memorys, and the chrominance C r data in the even number line of odd field and the odd-numbered line of even field are deleted, the most-significant byte of chrominance C b data writes in high-order colourity RAM buffer memory, in low 2 bit data write low level colourity RAM buffer memorys.Certainly, in this optimal way, for the situation of lining by line scan, if delete the Cr data of odd-numbered line, the Cb data of even number line; For interlacing scan situation; if delete the chrominance C r data in the odd-numbered line of odd field and the even number line of even field; and the chrominance C b data of deleting in the even number line of odd field and the odd-numbered line of even field, this similar equivalent informal letter is obviously also within protection scope of the present invention.
This side of YCbCr video data that the embodiment of the present invention converts 4:2:0 to from the YCbCr video data of 4:2:2 describes technical solution of the present invention when not affecting video quality, delete the chroma data of a part, generally reduce data volume, transmit in a road gigabit Ethernet passage provide the foundation for realizing HD-SID data.
embodiment two:
Fig. 3 shows a kind of high-definition serial digital interface data transfer device that second embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Step S301, line load equilibrium is carried out to the high-definition serial digital interface data of access, and convert it to a pair high-speed-differential digital signal;
Step S302, serioparallel exchange is carried out to described differential digital signal, obtain the YCbCr video data of parallel 4:2:2, and therefrom extract clock signal and the instruction of corresponding synchronizing information state.
Above-mentioned three steps are the previous step realizing data transaction, and object is the YCbCr video data of the parallel 4:2:2 in order to obtain removing invalid data.First load balance process is carried out to the HD-SDI signal that HD video camera transmissions is come, make it to convert a pair high-speed-differential digital signal to, after serioparallel exchange, obtain the YCbCr video data of parallel 4:2:2 again, and extract clock signal and the instruction of corresponding synchronizing information state.
Step S303, detect the YCbCr video data of described parallel 4:2:2, remove wherein invalid video blanking data, and judge data scanning mode and concrete form and transmission frame per second.
In order to reduce the unnecessary information of transmission, remove video blanking data invalid in video data in this step, the video data of 1.485Gbps is converted to the effective video data of 1.244Gbps, according to the description to HD video transmitting data stream form in SMPTE274M standard and SMPTE292M standard, as shown in Figure 4, the information such as the image timing base code in extraction video data and digital line number.According in image timing base code to the detection of video field number, judge that the high-definition video signal of input belongs to interlacing scan or belongs to and line by line scan.Also can add up the valid data byte number and horizontal blanking byte number that comprise in every row video data, the information such as the valid data line number comprised in every video data and field blanking number of data lines simultaneously, judge the concrete form and the transmission frame per second that input HD video.
Step S304, the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2 is write in high-order brightness buffer memory, in low 2 write low level brightness buffer memorys;
Step S305, the chrominance C b data of half line number in described YCbCr video data to be deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, chrominance C b data most-significant byte writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
Owing to having judged current HD video data scanning mode in step S303, if line by line scan, in this step, chrominance C b data in wherein odd-numbered line are deleted, the most-significant byte of chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in even number line is deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys; If interlacing scan, in this step, chrominance C b data in the odd-numbered line of odd field and the even number line of even field are deleted, the most-significant byte of chrominance C r data chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in the even number line of odd field and the odd-numbered line of even field are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
Step S306, by the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory in;
Step S307, read the YCbCr video data of ready 4:2:0 in described memory, and require that carrying out packing encapsulates, and sends after the Ethernet data bag of buffer memory sufficient amount according to ethernet frame format;
Step S308, by described Ethernet data Packet forwarding on gigabit Ethernet.
After by the YCbCr video data of ready 4:2:0 in high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory, can transmit in ethernet networks to make transformed video audio data, here need video data to be packaged into the packet meeting Ethernet data frame format, concrete encapsulation format as shown in Figure 1.
Embodiments provide a complete video data transfer process, HD-SDI data are obtained from HD video video camera, through equilibrium treatment, serioparallel exchange, removal invalid data, remove half chroma data, again through data encapsulation and forwarding, provide practicable solution for realizing HD-SDI video data nondestructively to transmit in gigabit Ethernet.
embodiment three:
Fig. 5 shows the flow process of a kind of high-definition serial digital interface data transfer device that third embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Inventive embodiments converts this side of YCbCr video data of parallel 4:2:2 to describe technical scheme of the present invention from the YCbCr video data of parallel 4:2:0, comprising:
Step S501, the most-significant byte of the brightness Y data in the YCbCr video data of described parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, low 2 write low level colourity second buffer memorys.
The YCbCr video data getting parallel 4:2:0 was needed before realizing this step, the YCbCr video data of described 4:2:0 is the YCbCr video data of the 4:2:0 be converted to from embodiment one step, and the object of the present embodiment is the YCbCr video data YCbCr video data restoration of described parallel 4:2:0 being become 4:2:2.The present embodiment has prepared 4 RAM buffer memorys equally for brightness data described in buffer memory and chroma data, table tennis read-write operation is adopted to video data, make it possible to realize data write in an orderly manner and read, described 4 RAM buffer memorys specifically comprise high-order brightness second buffer memory, low level brightness second buffer memory, high-order brightness second buffer memory, low level brightness second buffer memory, and this group RAM buffer memory can buffer memory 2 row HD video data equally.
Step S502, by interval for brightness Y address corresponding for the write of the brightness Y data of described YCbCr video data;
Step S503, will only have a line video data of chrominance C b data with only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
Owing to just removing half chroma data when carrying out data transaction in embodiment one, brightness data is constant, therefore, here when data convert, can directly the brightness Y data in the YCbCr video data of described parallel 4:2:0 be extracted, and the brightness Y address interval that write is corresponding; For chroma data, by deleting chrominance C b data, retain a line video data of chrominance C r data and delete chrominance C r data, retain a line video data of chrominance C b data and mutually compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
Be further used as preferred embodiment, if current YCbCr video data is the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data of odd-numbered line write one's own profession, again by the chrominance C b address section of the chrominance C b data of corresponding even number line write one's own profession, simultaneously by the chrominance C b address section of the chrominance C b data of even number line write one's own profession, at the chrominance C r address section by the chrominance C r data of corresponding even number line write one's own profession;
If current YCbCr video data is the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data write one's own profession in the odd-numbered line of odd field and the even number line of even field, again by the chrominance C b address section of the chrominance C b data write one's own profession in the odd-numbered line of the even field of correspondence and the even number line of odd field, simultaneously by the chrominance C b address section of the chrominance C b data write one's own profession in the even number line of odd field and the odd-numbered line of even field, again by the chrominance C r address section of the chrominance C r data write one's own profession in the even number line of the even field of correspondence and the odd-numbered line of odd field.
This preferred implementation is corresponding with the preferred implementation in embodiment one, is to line by line scan or interlacing scan carries out corresponding data reduction to video data according to video data.
The present embodiment is corresponding with embodiment one, the YCbCr video data restoration achieving the parallel 4:2:0 after embodiment one being changed becomes the YCbCr video data of parallel 4:2:2 before conversion, for being realize the YCbCr video data of parallel 4:2:0 to extract to carry out reduction display and provide the foundation.
embodiment four:
Fig. 6 shows the flow chart of a kind of high-definition serial digital interface data transfer device that fourth embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Step S601, receive the Ethernet data bag that transmits from gigabit Ethernet and send.
The Ethernet data bag transmitted from gigabit Ethernet described in this step is the packing of the YCbCr video data of parallel 4:2:0 encapsulated and be sent to the Ethernet data bag transmitted in gigabit Ethernet in embodiment two, and this step receives described Ethernet data bag for subsequent solves process.
Step S602, receive Ethernet data bag and parse YCbCr video data and the packet sequence number of wherein parallel 4:2:0, according to described packet sequence number, the described YCbCr of parsing video data being write in second memory.
After receiving Ethernet data bag, the video data in Frame and packet serial number information can be extracted, be written in second memory according to described packet sequence number by the screen data extracted, as a kind of implementation, second memory also adopts SDRAM here.
Step S603, the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
Step S604, by interval for brightness Y address corresponding for the write of the brightness Y data of described YCbCr video data;
Step S605, will only have a line video data of chrominance C b data with only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
In this step, as concrete implementation, if current YCbCr video data is the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data of odd-numbered line write one's own profession, again by the chrominance C b address section of the chrominance C b data of corresponding even number line write one's own profession, simultaneously by the chrominance C b address section of the chrominance C b data of even number line write one's own profession, at the chrominance C r address section by the chrominance C r data of corresponding even number line write one's own profession;
If current YCbCr video data is the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data write one's own profession in the odd-numbered line of odd field and the even number line of even field, again by the chrominance C b address section of the chrominance C b data write one's own profession in the odd-numbered line of the even field of correspondence and the even number line of odd field, simultaneously by the chrominance C b address section of the chrominance C b data write one's own profession in the even number line of odd field and the odd-numbered line of even field, again by the chrominance C r address section of the chrominance C r data write one's own profession in the even number line of the even field of correspondence and the odd-numbered line of odd field.
Two kinds of data convert modes described here and the two kinds of video data conversion methods adopted according to different scan modes described in embodiment two to, need by delete chroma data is corresponding compensates.
Step S606, the YCbCr video data of described parallel 4:2:2 is carried out parallel-serial conversion, generate high-speed-differential digital signal;
Step S607, described high-speed-differential digital signal is converted to high-definition serial digital interface data.
After the YCbCr video data YCbCr video data restoration of parallel 4:2:0 being become parallel 4:2:2, high-speed-differential digital signal is being generated through parallel-serial conversion, convert described high speed differential data to HD-SDI video data again, the HD-SDI video data after described reduction is sent to by coaxial cable on the display device specifically having HD-SDI interface or other switching equipment carry out data exchange.
The present embodiment step is corresponding with embodiment two, provide a complete video data restoration process, Ethernet data bag is got from gigabit Ethernet, therefrom parse the video data of parallel 4:2:0, restore out the half chroma data deleted in embodiment two, HD-SDI video data is generated after parallel-serial conversion, being undertaken showing or carrying out data exchange in other switching equipment by display device again, providing practicable solution for realizing restoring HD-SDI video data from Ethernet data bag.。
embodiment five:
Fig. 7 shows the structure of a kind of high-definition serial digital interface DTU (Data Transfer unit) that fifth embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Convert this side of YCbCr video data of parallel 4:2:0 to from the YCbCr video data of parallel 4:2:2, the high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides comprises:
Brightness data writing unit 701, for writing in high-order brightness buffer memory by the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys;
Chroma data writing unit 702, for the chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
Data storage cell 703, for writing the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory in memory.
Each functional unit 701-703 correspondence that the present embodiment provides achieves the step S201-S203 in embodiment one.As preferred embodiment mode, described chroma data writing unit 702 comprises:
Colourity writing module 7021 line by line, if for current YCbCr video data be the HD video data of lining by line scan, then the chrominance C b data in wherein odd-numbered line are deleted, the most-significant byte of chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in even number line are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
Interlacing colourity writing module 7022, if be interleaved HD video data for current YCbCr video data, then the chrominance C b data in the odd-numbered line of odd field and the even number line of even field are deleted, the most-significant byte of chrominance C r data chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in the even number line of odd field and the odd-numbered line of even field are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
The high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides provides the solution of the YCbCr video data YCbCr video data of parallel 4:2:2 being converted to parallel 4:2:0, transmits provide the foundation for realizing HD-SID data in a road gigabit Ethernet passage.
During the specific implementation embodiment of the present invention, on hardware configuration, described brightness data writing unit 701, chroma data writing unit 702 and data storage cell 703 can be realized by the programmable logic device comprising FPGA, the method that those skilled in the art can provide according to embodiment one, shows with FPGA or other FPGA (Field Programmable Gate Array) described three functional units that the present embodiment provides.
embodiment six:
Fig. 8 shows the structure of a kind of high-definition serial digital interface DTU (Data Transfer unit) that sixth embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
The high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides comprises:
Video access processing unit 801, for carrying out line load equilibrium to the high-definition serial digital interface data of access, and converts it to a pair high-speed-differential digital signal;
Serial data converting unit 802, for carrying out serioparallel exchange to described differential digital signal, obtain the YCbCr video data of parallel 4:2:2, and therefrom extract clock signal and the instruction of corresponding synchronizing information state.
Data pre-processing unit 803, for detecting the YCbCr video data of described parallel 4:2:2, removes wherein invalid video blanking data, and judges data scanning mode and concrete form and transmit frame per second
Brightness data writing unit 804, for writing in high-order brightness buffer memory by the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys;
Chroma data writing unit 805, for the chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
Data storage cell 806, for writing in memory by the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory;
Data packaging unit 807, for reading the YCbCr video data of ready 4:2:0 in described memory, and requiring to carry out packing encapsulation according to ethernet frame format, sending after the Ethernet data bag of buffer memory sufficient amount;
Ethernet data bag transmitting element 808, for by described Ethernet data Packet forwarding to gigabit Ethernet.
Each functional unit 801-808 correspondence that the present embodiment provides achieves the step S301-S308 in embodiment two.
During specific implementation, on hardware configuration, video access processing unit 801 can be realized by the line conditioning driving chip that HD-SDI HD video is special, serial data converting unit 802 can be realized by the SERDES chip that HD-SDI HD video is special, or realized by the programmable logic device comprising FPGA, described data pre-processing unit 803, brightness data writing unit 804, chroma data writing unit 805, data storage cell 806, data packaging unit 807 can be realized by the programmable logic device comprising FPGA, described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory is the ram cell in FPGA, residing memory is the SDRAM in FPGA, described Ethernet data bag transmitting element 808 can be realized by gigabit Ethernet PHY chip.Described line conditioning driving chip is connected on HD video video camera by the coaxial cable of 75 ohmages, described gigabit Ethernet PHY chip is connected on gigabit optical module, the HD-SDI HD video data of HD video camera acquisition can be realized to transmit on gigabit Ethernet.
embodiment seven:
Fig. 9 shows the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that seventh embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Convert this side of YCbCr video data of parallel 4:2:2 to from the YCbCr video data of parallel 4:2:0, the high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides comprises:
Data buffer storage unit 901, for the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
Brightness address space writing unit 902, for the brightness Y address interval by the brightness Y data of described YCbCr video data write correspondence;
Colourity address space writing unit 903, for will a line video data of chrominance C b data be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
Each functional unit 901-903 correspondence that the present embodiment provides achieves the step S501-S503 in embodiment three, and be further used as preferred embodiment, described colourity address space writing unit 903 comprises:
Colourity address space writing module 9031 line by line, if for current YCbCr video data be the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data of odd-numbered line write one's own profession, again by the chrominance C b address section of the chrominance C b data of corresponding even number line write one's own profession, simultaneously by the chrominance C b address section of the chrominance C b data of even number line write one's own profession, at the chrominance C r address section by the chrominance C r data of corresponding even number line write one's own profession;
Interlacing colourity address space writing module 9032, if for current YCbCr video data be the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data write one's own profession in the odd-numbered line of odd field and the even number line of even field, again by the chrominance C b address section of the chrominance C b data write one's own profession in the odd-numbered line of the even field of correspondence and the even number line of odd field, simultaneously by the chrominance C b address section of the chrominance C b data write one's own profession in the even number line of odd field and the odd-numbered line of even field, again by the chrominance C r address section of the chrominance C r data write one's own profession in the even number line of the even field of correspondence and the odd-numbered line of odd field.
The high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides provides the solution of the YCbCr video data YCbCr video data of parallel 4:2:0 being converted to parallel 4:2:2, carries out reduction display provide the foundation for realizing the YCbCr video data of parallel 4:2:0 to extract.
During the specific implementation embodiment of the present invention, on hardware configuration, described data buffer storage unit 901, brightness address space writing unit 902 and colourity address space writing unit 903 can be realized by the programmable logic device comprising FPGA, the method that those skilled in the art can provide according to embodiment three, shows with FPGA or other FPGA (Field Programmable Gate Array) described three functional units that the present embodiment provides.
embodiment eight:
Figure 10 shows the block diagram of a kind of high-definition serial digital interface DTU (Data Transfer unit) that eighth embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
The high-definition serial digital interface DTU (Data Transfer unit) that the present embodiment provides comprises:
Ethernet data bag receiving element 101, receives the Ethernet data bag that transmits from gigabit Ethernet and sends;
Packet resolution unit 102, for receiving Ethernet data bag and parsing YCbCr video data and the packet sequence number of wherein parallel 4:2:0, writes in second memory according to described packet sequence number by the described YCbCr of parsing video data;
Data buffer storage unit 103, for the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
Brightness address space writing unit 104, for the brightness Y address interval by the brightness Y data of described YCbCr video data write correspondence;
Colourity address space writing unit 105, for will a line video data of chrominance C b data be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2;
Data parallel serial conversion unit 106, for carrying out parallel-serial conversion to the YCbCr video data of described parallel 4:2:2, generates high-speed-differential digital signal;
Video data output unit 107, for being converted to high-definition serial digital interface data by described high-speed-differential digital signal.
Each functional unit 101-107 correspondence that the present embodiment provides achieves the step S601-S606 in embodiment four.
During specific implementation, on hardware configuration, described Ethernet data bag receiving element 101 is realized by gigabit Ethernet PHY chip, described packet resolution unit 102, data buffer storage unit 103, brightness address space writing unit 104, colourity address space writing unit 105 can be realized by the programmable logic device comprising FPGA, wherein said high-order brightness second buffer memory, low level brightness second buffer memory, high-order colourity second buffer memory, high-order colourity second buffer memory is the ram cell in FPGA, described second memory is the SDRAM in FPGA, described data parallel serial conversion unit 106 can be realized by the SERDES chip that HD-SDI HD video is special, or realized by the programmable logic device comprising FPGA, described video data output unit 107 can be realized by the line conditioning driving chip that HD-SDI HD video is special.Described gigabit Ethernet PHY chip is connected on gigabit optical module, the coaxial cable of line conditioning driving chip 75 ohmage is connected on display or switching matrix, gigabit optical module can be realized from the Ethernet data bag that gigabit Ethernet receives, restore HD-SDI HD video data, and show in the display, or display other again shows after switching matrix.
embodiment nine:
Figure 11 shows the schematic diagram of road HD-SDI HD video transmission system on gigabit Ethernet that eighth embodiment of the invention provides, and illustrate only the part relevant to the embodiment of the present invention for convenience of explanation.
Described system comprises the line conditioning driving chip 111 that can realize video access processing unit as described in embodiment six, serial data can be realized and the serioparallel exchange SERDES chip 112 of converting unit, data pre-processing unit can be realized, brightness data writing unit, chroma data writing unit, data storage cell, the coding FPGA113 of data packaging unit, the gigabit Ethernet PHY chip 114 of Ethernet data bag transmitting element can be realized, described system also comprises can realize Ethernet data bag receiving element gigabit Ethernet PHY chip 115 as described in embodiment eight, packet resolution unit can be realized, data buffer storage unit, brightness address space writing unit, the decoding FPGA116 of colourity address space writing unit, the parallel-serial conversion SERDES chip 117 of data parallel serial conversion unit can be realized, the line conditioning driving chip 118 of video data output unit can be realized.Gigabit Ethernet PHY chip is wherein connected with gigabit optical module, and described gigabit optical module is connected by gigabit Ethernet, and described line conditioning driving chip is connected with HD video video camera.
One of ordinary skill in the art will appreciate that, the all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, described storage medium, as ROM/RAM, disk, CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a high-definition serial digital interface data transfer device, is characterized in that, described method comprises:
The most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2 is write in high-order brightness buffer memory, in low 2 write low level brightness buffer memorys;
The chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, chrominance C b data most-significant byte writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
By in the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory.
2. method as claimed in claim 1, it is characterized in that, described the chrominance C b data of half line number in described YCbCr video data to be deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, step in low 2 bit data write low level colourity buffer memorys, specifically comprises:
If current YCbCr video data is the HD video data of lining by line scan, then the chrominance C b data in wherein odd-numbered line are deleted, the most-significant byte of chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in even number line are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
If current YCbCr video data is interleaved HD video data, then the chrominance C b data in the odd-numbered line of odd field and the even number line of even field are deleted, the most-significant byte of chrominance C r data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, and the chrominance C r data in the even number line of odd field and the odd-numbered line of even field are deleted, the most-significant byte of chrominance C b data writes in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys.
3. method as described in any one of claim 1 or 2, is characterized in that:
Write in high-order brightness buffer memory at the described most-significant byte by the brightness Y data in the YCbCr video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys before step, also comprise:
Detect the YCbCr video data of described parallel 4:2:2, remove wherein invalid video blanking data, and judge data scanning mode and concrete form and transmit frame per second;
Described by the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory write memory after step, also comprise:
Read the YCbCr video data of ready 4:2:0 in described memory, and according to requiring with ethernet frame format to carry out packing encapsulation, send after the Ethernet data bag of buffer memory sufficient amount.
4. method as claimed in claim 3, is characterized in that:
Detecting the YCbCr video data of described parallel 4:2:2, remove wherein invalid video blanking data, and before judging data scanning mode and concrete form and transmitting frame per second step, also comprise:
Line load equilibrium is carried out to the high-definition serial digital interface data of access, and converts it to a pair high-speed-differential digital signal;
Serioparallel exchange is carried out to described differential digital signal, obtains the YCbCr video data of parallel 4:2:2, and therefrom extract clock signal and the instruction of corresponding synchronizing information state;
At the described YCbCr video data of described reading and according to requiring that with ethernet frame format carrying out packing encapsulates, and after sending step, also comprises after the Ethernet data bag of buffer memory sufficient amount:
By described Ethernet data Packet forwarding on gigabit Ethernet.
5. a high-definition serial digital interface data transfer device, is characterized in that, described method comprises:
The most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
By interval for brightness Y address corresponding for the write of the brightness Y data of described YCbCr video data;
A line video data of chrominance C b data will be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
6. method as claimed in claim 5, it is characterized in that, described will only have a line video data of chrominance C b data and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, finally be reduced into the YCbCr video data step of parallel 4:2:2, specifically comprise:
If current YCbCr video data is the HD video data of lining by line scan, then by the chrominance C r address section of the chrominance C r data of odd-numbered line write one's own profession, again by the chrominance C b address section of the chrominance C b data of corresponding even number line write one's own profession, simultaneously by the chrominance C b address section of the chrominance C b data of even number line write one's own profession, at the chrominance C r address section by the chrominance C r data of corresponding even number line write one's own profession;
If current YCbCr video data is the HD video data that interlacing s scans, then by the chrominance C r address section of the chrominance C r data write one's own profession in the odd-numbered line of odd field and the even number line of even field, again by the chrominance C b address section of the chrominance C b data write one's own profession in the odd-numbered line of the even field of correspondence and the even number line of odd field, simultaneously by the chrominance C b address section of the chrominance C b data write one's own profession in the even number line of odd field and the odd-numbered line of even field, again by the chrominance C r address section of the chrominance C r data write one's own profession in the even number line of the even field of correspondence and the odd-numbered line of odd field.
7. method as described in any one of claim 5 or 6, it is characterized in that, write in high-order brightness second buffer memory at the described most-significant byte by the brightness Y data in the YCbCr video data of parallel 4:2:0, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys before step, also comprise:
Receive Ethernet data bag and parse YCbCr video data and the packet sequence number of wherein parallel 4:2:0, according to described packet sequence number, the described YCbCr of parsing video data being write in second memory.
8. method as claimed in claim 7, is characterized in that:
Parse YCbCr video data and the packet sequence number of wherein parallel 4:2:0 at described reception Ethernet data bag, according to described packet sequence number, the described YCbCr of parsing video data write in second memory before step, also comprise:
The Ethernet data bag that reception is transmitted from gigabit Ethernet also sends;
To a line video data of chrominance C b data be only had described and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, after being finally reduced into the YCbCr video data step of parallel 4:2:2, also comprise:
The YCbCr video data of described parallel 4:2:2 is carried out parallel-serial conversion, generates high-speed-differential digital signal;
Described high-speed-differential digital signal is converted to high-definition serial digital interface data.
9. a high-definition serial digital interface DTU (Data Transfer unit), is characterized in that, described device comprises:
Brightness data writing unit, for writing in high-order brightness buffer memory by the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:2, in low 2 write low level brightness buffer memorys;
Chroma data writing unit, for the chrominance C b data of half line number in described YCbCr video data are deleted, and chrominance C r data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys, the chrominance C r data of second half line number are deleted, and chrominance C b data most-significant byte is write in high-order colourity buffer memory, in low 2 bit data write low level colourity buffer memorys;
Data storage cell, for writing the YCbCr video data of ready 4:2:0 in described high-order brightness buffer memory, low level brightness buffer memory, high-order colourity buffer memory, low level colourity buffer memory in memory.
10. a high-definition serial digital interface DTU (Data Transfer unit), is characterized in that, described device comprises:
Data buffer storage unit, for the most-significant byte of the brightness Y data in the YCbCr video data of parallel 4:2:0 is write in high-order brightness second buffer memory, in low 2 write low level brightness second buffer memorys, the most-significant byte of chrominance C b data and chrominance C r data writes in high-order colourity second buffer memory, in low 2 write low level colourity second buffer memorys;
Brightness address space writing unit, for the brightness Y address interval by the brightness Y data of described YCbCr video data write correspondence;
Colourity address space writing unit, for will a line video data of chrominance C b data be only had and only have a line video data of chrominance C r data mutually to compensate, and the chrominance C b address space of write correspondence and chrominance C r address space, be finally reduced into the YCbCr video data of parallel 4:2:2.
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