CN211377893U - Power factor correction circuit - Google Patents
Power factor correction circuit Download PDFInfo
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- CN211377893U CN211377893U CN201922388574.1U CN201922388574U CN211377893U CN 211377893 U CN211377893 U CN 211377893U CN 201922388574 U CN201922388574 U CN 201922388574U CN 211377893 U CN211377893 U CN 211377893U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to a power factor correction circuit, belong to power management technical field, be applied to boost converter framework, the circuit includes that power factor corrects the chip, the rectifier bridge, filter capacitor, effective voltage sampling circuit, waveform sampling resistor, chip oscillation cycle control circuit, the inductance, freewheeling diode, the power tube, inductive current sampling resistor, first and second pin resistance, the compensating network is put to electric current fortune, the compensating network is put to voltage fortune, first and second output divider resistance, output capacitor, rectifier bridge's input termination alternating current power supply, the inside biasing unit that connects in order that includes of multiplier, feedforward control unit and multiplier unit, multiplier unit adopts gilbert multiplier structure, for hyperbolic tangent function, feedforward control unit is inverse hyperbolic tangent function. The multiplier of the PFC circuit can eliminate the change of PFC framework gain along with the change of an alternating current power supply by performing feedforward compensation, has strong universality and has larger power factor value.
Description
Technical Field
The utility model relates to a power management technical field especially relates to a power factor correction circuit.
Background
At present, the double camera modules become a mainstream camera of the mobile electronic equipment and are divided in a fixed mode of the modules, and the double camera modules can be divided into a common substrate type and a common bracket type, wherein the common bracket type double camera modules are widely used due to good imaging effect. The existing double-camera module has the defects of complex structure, small size and the like, so that the application requirement of lighter and thinner or miniaturized mobile electronic equipment cannot be met.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a be applied to boost converter framework's power factor correction circuit, this circuit can improve the power factor value greatly, and its commonality is good.
In order to achieve the above object, the present invention adopts the technical solution that, a power factor correction circuit is applied to a Boost converter (Boost) architecture, comprising a power factor correction chip, a rectifier bridge, a filter capacitor, an effective voltage sampling circuit, a waveform sampling resistor, a chip oscillation period control circuit, an inductor, a freewheeling diode, a power tube, an inductor current sampling resistor, a first and a second pin resistor, a current operational amplifier compensation network, a voltage operational amplifier compensation network, a first and a second output divider resistors, and an output capacitor, wherein an input end of the rectifier bridge is connected to an ac power supply, a positive output end and a negative output end of the rectifier bridge are connected to two ends of the filter capacitor, an input end of the effective voltage sampling circuit is connected to a positive output end and a negative output end of the rectifier bridge, an output end of the effective voltage sampling circuit is connected to a Vrms pin of the chip, and one end of the waveform sampling resistor is connected to, the other end of the chip oscillation period control circuit is connected between a Cosc pin and a Rosc pin of the chip, one end of an inductor is connected with a waveform sampling resistor, the other end of the inductor is connected with the anode of a fly-wheel diode, the cathode of the fly-wheel diode is led out to be used as an output load connection port of the circuit, the grid of a power tube is connected with a Gate pin of the chip, the source of the power tube is grounded, the drain of the power tube is connected with the anode of the fly-wheel diode, one end of a first pin resistor is connected with a MULTOUT pin of the chip, the other end of the first pin resistor is connected with the negative output end of a rectifier bridge, one end of a second pin resistor is connected with an Ics pin of the chip, the other end of the second pin resistor is grounded, one end of an inductive current sampling resistor is connected with the negative output end of the rectifier bridge, the other end of the inductive current operational amplifier compensation network is connected between the Ics pin and the CA, the outer end of the first output divider resistor is connected with the negative electrode of the freewheeling diode, the outer end of the second output divider resistor is grounded, the FB pin of the chip is connected between the first output divider resistor and the second output divider resistor, and the output capacitor is connected between the negative electrode of the freewheeling diode and the ground in series.
As an improvement of the utility model, the power factor correction chip is internally provided with a voltage operational amplifier, a multiplier, a current operational amplifier, a comparator, a bias module for generating reference voltage, an oscillator, an RS trigger and a driving module, the first and second input ends of the multiplier are respectively led out as Iac pin and Vrms pin, the output end of the multiplier is led out as MULTOUT pin, the output end of the multiplier is connected with the positive input end of the current operational amplifier, the negative input end of the current operational amplifier is led out as Ics pin, the output end of the current operational amplifier is led out as CAOUT pin, the output end of the current operational amplifier is connected with the negative input end of the comparator, the positive input end of the comparator is connected with the first input end of the oscillator, the first and second input ends of the oscillator are respectively led out as Cosc pin and Rosc pin, the output end of the oscillator is connected with the S end of the RS trigger, the output end of the comparator is connected with the R end of the, the output end of the RS trigger is connected with the input end of the driving module, the output end of the driving module is led out to be used as a Gate pin, the positive input end of the voltage operational amplifier is connected with the output end of the bias module, the negative input end of the voltage operational amplifier is led out to be used as an FB pin, the output end of the voltage operational amplifier is led out to be used as a VAOUT pin, and the output end of the voltage operational amplifier is connected with the third input end of the multiplier.
As an improvement of the utility model, effective voltage sampling circuit includes first resistance, second resistance, first electric capacity, first and second resistance series connection, and a termination rectifier bridge's of first resistance positive output end, a termination rectifier bridge's of second resistance negative output end, and the one end of first electric capacity is connected on the one hand between first and second resistance, and chip's Vrms pin, another termination rectifier bridge's negative output end are connected to on the other hand.
As an improvement of the utility model, chip oscillation period control circuit includes third resistance, second electric capacity, and the both ends of second electric capacity are connect between the Cosc pin of chip and ground, and the both ends of third resistance are connected between the Rosc pin of chip and ground.
As an improvement of the present invention, the gain of the multiplier is increased by
Factor, Vac, is the supply voltage.
As an improvement of the utility model, inside biasing unit, feedforward control unit and the multiplier unit of including of multiplier, biasing unit, feedforward control unit and multiplier unit connect in order, the multiplier unit adopts gilbert multiplier structure, and for hyperbolic tangent function, the feedforward control unit is inverse hyperbolic tangent function.
As an improvement of the present invention, the value range of the filter capacitor is 100 to 200 nF.
As an improvement of the present invention, the value of the inductive current sampling resistor is several tens to several hundreds of milliohms.
As a refinement of the invention, a typical value for the first resistance is 1.5M, a typical value for the second resistance is 33K, a typical value for the first capacitance is 200nF, and a typical value for the waveform sampling resistance is 1.5M.
As an improvement of the utility model, the power tube adopts N type MOS pipe.
Compared with the prior art, the utility model provides a PFC circuit framework overall structure design benefit, rational in infrastructure is stable, can realize corresponding function in, improves power factor value greatly, leads toBy using a feedforward control unit in a multiplier inside a power factor correction chip of the circuit, feedforward compensation for power grid voltage change of an alternating current power supply is realized, and one is added in the gain of the multiplier
The factor effectively ensures that the gain of the circuit system is not influenced by the change of the alternating current power supply, and simultaneously enlarges the universality of the PFC circuit architecture.
Drawings
Fig. 1 is a diagram of a power factor correction circuit according to a preferred embodiment of the present invention.
Fig. 2 is a circuit diagram of the internal implementation of the multiplier in the preferred embodiment of the present invention.
Detailed Description
For the purposes of promoting an understanding and appreciation of the invention, the invention will be further described and illustrated in connection with the accompanying drawings.
For a PFC circuit with Boost architecture, the open loop gain (Gloop) of the system is proportional to the square of the supply voltage Vac and the gain (Km) of the load (Rload) and the multiplier inside the power factor correction chip from the stability point of view, that is:
in general, the multiplier gain Km is a fixed value, and the load Rload is fixed, the open-loop gain Gloop of the system varies with the variation of the supply voltage Vac. For example, for a 220Vac grid in our country, the system gain is a value, and for a 110Vac grid in some countries, the system gain varies too much.
The utility model discloses a power factor correction circuit that preferred embodiment shows, as shown in FIG. 1, be applied to Boost converter (Boost) framework, correct the chip including the power factor, the rectifier bridge, filter capacitor C1, effective voltage sampling circuit, wave form sampling resistance R3, chip oscillation period control circuit, inductance L, freewheeling diode D5, power tube MOS, inductive current sampling resistance Rcs, first and second pin resistance R6, compensation network is put to electric current fortune, compensation network is put to voltage fortune, first and second output divider resistance, output capacitor C6. The rectifier bridge is composed of diodes D1-D4, the input end of the rectifier bridge is connected with an alternating current power supply AC, and the positive output end and the negative output end of the rectifier bridge are connected with the two ends of a filter capacitor C1. The value range of the filter capacitor C1 is 100-200 nF.
The input end of the effective voltage sampling circuit is connected with the positive output end and the negative output end of the rectifier bridge, and the output end of the effective voltage sampling circuit is connected with the Vrms pin of the chip. Specifically, the effective voltage sampling circuit comprises a first resistor R1, a second resistor R2 and a first capacitor C2, wherein the first resistor R1 and the second resistor R2 are connected in series, one end of the first resistor R1 is connected with a positive output end of a rectifier bridge, one end of the second resistor R2 is connected with a negative output end of the rectifier bridge, one end of the first capacitor C2 is connected between the first resistor R and the second resistor R, the other end of the first capacitor C2 is connected with a Vrms pin of a chip, and the other end of the first capacitor C2 is connected with the negative output end of the. A typical value for the first resistor R1 is 1.5M, a typical value for the second resistor R2 is 33K, and a typical value for the first capacitor C2 is 200 nF.
One end of the waveform sampling resistor R3 is connected with the positive output end of the rectifier bridge, and the other end is connected with the Iac pin of the chip. A typical value for the waveform sampling resistor R3 is 1.5M. The waveform sampling resistor R3 is used for ensuring that the current waveform flowing into the Iac pin of the chip follows the voltage waveform after the rectifier bridge.
The chip oscillation period control circuit is connected between a Cosc pin and a Rosc pin of the chip. Specifically, the chip oscillation period control circuit comprises a third resistor R4 and a second capacitor C3, wherein two ends of the second capacitor C3 are connected between a Cosc pin of the chip and the ground, and two ends of the third resistor R4 are connected between a Rosc pin of the chip and the ground. The second capacitor C3 is continuously charged and discharged and takes a triangular wave shape.
One end of the inductor L is connected with the waveform sampling resistor R3, and the other end is connected with the anode of the freewheeling diode D5.
And the negative electrode of the freewheeling diode D5 is led out to serve as an output load connection port VOUT of the circuit and is used for being connected with a load Rload. The grid of the power tube MOS is connected with a Gate pin of the chip, the source is grounded, and the drain is connected with the anode of the current diode D5. The power tube MOS adopts an N-type MOS tube.
One end of the first pin resistor R5 is connected with a MULTOUT pin of the chip, the other end of the first pin resistor R5 is connected with a negative output end of the rectifier bridge, one end of the second pin resistor R6 is connected with an Ics pin of the chip, and the other end of the second pin resistor R6 is grounded.
One end of the inductive current sampling resistor Rcs is connected with the negative output end of the rectifier bridge, and the other end of the inductive current sampling resistor Rcs is grounded. The value of the inductive current sampling resistor Rcs is dozens to hundreds of milliohms.
The current operational amplifier compensation network is connected between the Ics pin and the CAOUT pin of the chip.
The voltage operational amplifier compensation network is connected between the FB pin and the VAOUT pin of the chip.
The first output voltage-dividing resistor and the second output voltage-dividing resistor are connected in series, the outer end of the first output voltage-dividing resistor R9 is connected with the cathode of the freewheeling diode D5, and the outer end of the second output voltage-dividing resistor R10 is grounded. The FB pin of the chip is connected between the first output voltage-dividing resistor R9 and the second output voltage-dividing resistor R10, and the output capacitor C6 is connected in series between the negative electrode of the freewheeling diode D5 and the ground. Various output voltage values can be designed by adjusting the ratio of the first output voltage-dividing resistor and the second output voltage-dividing resistor.
The power factor correction chip is internally provided with a voltage operational amplifier VoltageAMP, a multiplier MULT, a Current operational amplifier Current AMP, a comparator PWM, a BIAS module LDO & BIAS for generating reference voltage, an oscillator OSC, an RS trigger and a driving module Driver, wherein a first input end and a second input end of the multiplier MULT are respectively led out to be used as an Iac pin and a Vrms pin and respectively receive Iac signals and Vrms signals. The output end of the multiplier MULT is led out to be used as a MULTOUT pin, the output end of the multiplier MULT is connected with the positive input end of a Current operational amplifier (CURRENT AMP), the negative input end of the Current operational amplifier (CURRENT AMP) is led out to be used as an Ics pin, the output end of the Current operational amplifier (CURRENT AMP) is connected with the negative input end of a comparator PWM, the positive input end of the comparator PWM is connected with the first input end of an oscillator OSC, the first input end and the second input end of the oscillator OSC are respectively led out to be used as a Cosc pin and a Rosc pin, the oscillation period is controlled by an external chip oscillation period control circuit, the output end of the oscillator OSC is connected with the S end of an RS trigger, the oscillator OSC outputs continuous square wave signals, the chip is controlled to be conducted by the rising edge of the square wave, the output end of the comparator PWM is connected with the R end of the RS trigger, and the. The output end of the RS trigger is connected with the input end of a driving module Driver, the driving module Driver is used for controlling the on and off of an external power tube MOS, and the output end of the driving module Driver is led out to be used as a Gate pin. The positive input end of the voltage operational amplifier VoltageAMP is connected with the output end of the BIAS module LDO & BIAS, and the BIAS module LDO & BIAS generates a voltage reference signal to be output. The output end of the voltage operational amplifier VoltageAMP is connected with the third input end of the multiplier MULT to receive an output signal of the voltage operational amplifier VoltageAMP.
The working principle of the PFC circuit of the preferred embodiment described above is: after passing through the rectifier bridge, the alternating current power supply AC presents a half sine wave shape, as shown in fig. 1, when the power transistor MOS is turned on, the half sine wave charges the inductor L, the current returns to the negative output end of the rectifier bridge through the inductor current sampling resistor Rcs, and the current of the inductor L rises during the period; when the power tube MOS is turned off, the inductor L discharges, and the discharged current is output to the load and the inductor current sampling resistor Rcs through the freewheeling diode D5, and then returns to the negative output end of the rectifier bridge, during which the inductor L current decreases. Therefore, the inductor L current takes a triangular wave shape during one switching period.
In addition, the PFC circuit system includes two negative feedback loops, namely a voltage loop and a current loop, during operation.
Working principle of the voltage loop: if the output voltage rises, the voltage of the chip feedback pin FB rises, the output voltage of the voltage operational amplifier VoltageAMP is reduced, one multiplication factor of the multiplier MULT is reduced, the output voltage of the multiplier MULT is reduced, and therefore the output voltage of the Current operational amplifier Current AMP is reduced. And the voltage of the negative input end of the comparator PWM is reduced, the rising time of the triangular wave of the positive input end of the comparator PWM is shorter, the chip controls the MOS of the power tube to be turned off more quickly, namely the duty ratio output by the comparator PWM is reduced, and the output voltage is reduced, so that the voltage negative feedback is formed.
The working principle of the current loop is as follows: the Current operational amplifier Current AMP and a peripheral Current operational amplifier compensation network form a Current loop, the function of the Current loop is equivalent to a voltage follower, the output voltage of the Current operational amplifier Current AMP follows the voltage of the positive input end, when the voltage of the positive input end becomes high, the output voltage of the Current operational amplifier Current AMP becomes high, and vice versa. Therefore, the output voltage of the Current operational amplifier Current AMP determines the magnitude of the duty cycle of the output of the comparator PWM, i.e., if the output voltage of the Current operational amplifier Current AMP is high, the duty cycle of the output of the comparator PWM is large.
For the boost converter, the input voltage is half sine wave voltage after the rectifier bridge, the input current is the average current passing through the inductor L (because the resistances of the first resistor R1, the second resistor R2 and the waveform sampling resistor R3 are large, the current is ignored), the boost converter is to ensure that the input voltage is in direct proportion to the input current, and the core of the boost converter is the function of the multiplier MULT. For example, when the input voltage is at a peak, the current of the chip Iac is large, the output voltage of the multiplier MULT is large, the duty ratio of the output of the comparator PWM is large in one switching period, and for the inductance L, the peak value of the inductance L is larger in one switching period, and the average value is larger. The rest is analogized in turn.
In order to avoid that the gain of the circuitry varies with the supply voltage, the multiplier MULT has an increased gain
Factor, Vac, is the supply voltage.
Meanwhile, a feedforward compensation design is made in an internal circuit structure of the multiplier MULT, and particularly, the input of the multiplier MULT comprises Iac, Vrms and the output of a voltage operational amplifier VoltageAMP. As shown in FIG. 2, the multiplier MULT internally includes a left offset unit, a middle feedforward control unit 1/V2 and a right multiplier MULT, and the offset unit, feedforward control unit 1/V2 and multiplier MULT are connected in sequence.
The multiplier unit MULT adopts a gilbert multiplier MULT structure, is a hyperbolic tangent function, and the output current can be expressed as:
V1-V4 are differential inputs of input terminals of the multiplier MULT, Iee is tail current, equivalent to Iac in the circuit, and VT is thermal voltage constant.
The feedforward control unit 1/V2 is an inverse hyperbolic tangent function, and the feedforward control unit 1/V2 is used for compensating the influence of an alternating current power supply AC on the open-loop gain of the PFC framework. V1-V2, V3-V4 can be expressed as:
wherein, Vb1, Vb2 and Vb3 are bias voltages, I1 is a current mirror current, and VAOUT is an output signal of the voltage operational amplifier VoltageAMP.
I1 can be expressed as:
thus, the output of the multiplier MULT can be restated as:
therefore, the multiplier MULT comprises
The factor, Vrms, is derived from the ac power source Vac through a voltage dividing resistor. In particular toVrms is obtained by integrating a first resistor R1 and a second resistor R2 through a first capacitor C2, the capacitance value of the first capacitor C2 is large, and the voltage value actually obtained by Vrms is directly proportional to the effective value of the alternating current power supply Vac and is not followed in real time. For example, for a 220Vac AC power supply, the supply waveform after the rectifier bridge assumes a half sine wave shape, but the Vrms voltage value is a fixed value, such as 4V; similarly, for an AC power source AC of 110Vac, the Vrms voltage value is fixed, such as 2V.
Therefore, the utility model provides a PFC circuit can effectively guarantee that system gain does not change along with alternating current power supply AC changes to this PDC framework's commonality has also been enlarged.
The technical means disclosed by the scheme of the present invention is not limited to the technical means disclosed by the above embodiments, but also includes the technical scheme formed by the arbitrary combination of the above technical features. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also considered as the protection scope of the present invention.
Claims (10)
1. A power factor correction circuit, characterized by: applied to a boost converter framework, comprising a power factor correction chip, a rectifier bridge, a filter capacitor, an effective voltage sampling circuit, a waveform sampling resistor, a chip oscillation period control circuit, an inductor, a fly-wheel diode, a power tube, an inductive current sampling resistor, a first pin resistor, a second pin resistor, a current operational amplifier compensation network, a voltage operational amplifier compensation network, a first output divider resistor, a second output divider resistor and an output capacitor, wherein the input end of the rectifier bridge is connected with an alternating current power supply, the positive output end and the negative output end of the rectifier bridge are connected with two ends of the filter capacitor, the input end of the effective voltage sampling circuit is connected with the positive output end and the negative output end of the rectifier bridge, the output end of the effective voltage sampling circuit is connected with a Vrms pin of the chip, one end of the waveform sampling resistor is connected with the positive output end of the rectifier bridge, the other end of the waveform sampling resistor is connected with, one end of the inductor is connected with the waveform sampling resistor, the other end of the inductor is connected with the anode of the fly-wheel diode, the cathode of the fly-wheel diode is led out to be used as an output load connection port of the circuit, the grid of the power tube is connected with a Gate pin of the chip, the source of the power tube is grounded, the drain of the power tube is connected with the anode of the fly-wheel diode, one end of the first pin resistor is connected with a MULTOUT pin of the chip, the other end of the first pin resistor is connected with a negative output end of the rectifier bridge, one end of the second pin resistor is connected with an Ics pin of the chip, the other end of the second pin resistor is grounded, one end of the inductor current sampling resistor is connected with the negative output end of the rectifier bridge, the other end of the inductor current sampling resistor is grounded, the current operational amplifier compensation network is connected between the Ics pin and the CAOUT pin of the chip, the voltage operational amplifier compensation network is connected between the, the FB pin of the chip is connected between the first output voltage-dividing resistor and the second output voltage-dividing resistor, and the output capacitor is connected between the negative electrode of the freewheeling diode and the ground in series.
2. The power factor correction circuit of claim 1, wherein the power factor correction chip is internally provided with a voltage operational amplifier, a multiplier, a current operational amplifier, a comparator, a bias module, an oscillator, an RS flip-flop and a driving module, wherein a first input end and a second input end of the multiplier are respectively led out as an Iac pin and a Vrms pin, an output end of the multiplier is led out as a MULTOUT pin, an output end of the multiplier is connected with a positive input end of the current operational amplifier, a negative input end of the current operational amplifier is led out as an Ics pin, an output end of the current operational amplifier is led out as a CAOUT pin, an output end of the current operational amplifier is connected with a negative input end of the comparator, a positive input end of the comparator is connected with a first input end of the oscillator, a first input end and a second input end of the oscillator are respectively led out as a Cosc pin and a Rosc pin, an output end of the oscillator is connected with an S end of the RS flip-flop, and an, the output end of the RS trigger is connected with the input end of the driving module, the output end of the driving module is led out to be used as a Gate pin, the positive input end of the voltage operational amplifier is connected with the output end of the bias module, the negative input end of the voltage operational amplifier is led out to be used as an FB pin, the output end of the voltage operational amplifier is led out to be used as a VAOUT pin, and the output end of the voltage operational amplifier is connected with the third input end of the multiplier.
3. A power factor correction circuit as claimed in claim 2, wherein the effective voltage sampling circuit comprises a first resistor, a second resistor, and a first capacitor, the first and second resistors being connected in series, one end of the first resistor being connected to the positive output terminal of the rectifier bridge, one end of the second resistor being connected to the negative output terminal of the rectifier bridge, one end of the first capacitor being connected between the first and second resistors, on the one hand, and the Vrms pin of the chip, on the other hand, and the other end being connected to the negative output terminal of the rectifier bridge.
4. The circuit for correcting power factor of claim 3, wherein the chip oscillation period control circuit comprises a third resistor and a second capacitor, the second capacitor is connected between the Cosc pin of the chip and the ground, and the third resistor is connected between the Rosc pin of the chip and the ground.
5. The power factor correction circuit of claim 4, wherein the gain of the multiplier is set by
Factor, Vac, is the supply voltage.
6. The power factor correction circuit according to claim 5, wherein the multiplier includes a bias unit, a feedforward control unit and a multiplier unit, the bias unit, the feedforward control unit and the multiplier unit are connected in sequence, the multiplier unit adopts a gilbert multiplier structure and is a hyperbolic tangent function, and the feedforward control unit is an inverse hyperbolic tangent function.
7. A power factor correction circuit according to claim 6, wherein the filter capacitance has a value in the range of 100 to 200 nF.
8. The power factor correction circuit of claim 7, wherein the inductor current sampling resistor has a value of several tens to several hundreds of milliohms.
9. A power factor correction circuit according to claim 8, wherein the first resistance has a typical value of 1.5M, the second resistance has a typical value of 33K, the first capacitance has a typical value of 200nF, and the waveform sampling resistance has a typical value of 1.5M.
10. The circuit for correcting power factor of claim 9, wherein the power transistor is an N-type MOS transistor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313678A (en) * | 2019-12-26 | 2020-06-19 | 苏州锴威特半导体股份有限公司 | Power factor correction circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313678A (en) * | 2019-12-26 | 2020-06-19 | 苏州锴威特半导体股份有限公司 | Power factor correction circuit |
| CN111313678B (en) * | 2019-12-26 | 2024-07-30 | 苏州锴威特半导体股份有限公司 | Power factor correction circuit |
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