CN218771769U - A Bridgeless PFC Converter System Without Current Sampling - Google Patents

Abstract

The utility model discloses a no bridge PFC converter system of no current sampling specifically comprises a plurality of modules, is totem pole no bridge PFC circuit module, input voltage sampling module, input zero cross detection module, output voltage sampling module, microprocessor control module, PWM generation module and first, second keep apart drive module and auxiliary power supply respectively, has got rid of input current sampling circuit in the system. The utility model provides a no bridge PFC converter system of no current sampling solves under the condition of not sampling current and not all components and parts parameters and parasitic parameter among the measuring circuit, utilizes the DSP chip to carry out digital control, realizes power factor correction and constant voltage output, the technical problem of the complexity and the circuit cost of lowering system.

Description

A bridgeless PFC converter system without current sampling

Technical Field

The utility model relates to the technical field of switching power supplies, in particular to a bridgeless PFC converter system without current sampling.

Background Art

With the development and changes of the times, the use of wireless communication has become more and more deeply integrated into people's daily lives, such as technologies such as Bluetooth, wireless LAN (WIFI) and global satellite positioning system. Transceivers are important devices for wireless communication, and power amplifiers play an extremely important role in transceivers.

The current mainstream power amplifier design process is GaAs and GaN, because they have good RF performance and can withstand high-power output. However, it is difficult to integrate the entire transceiver chip using the mainstream design process, and it faces the problem of high cost. Silicon-based process design has the advantage of high integration, but the design of power amplifiers using silicon-based processes is still a challenging task. First of all, the use of silicon-based process design will face the problem of high passive device loss, which will lead to a decrease in the efficiency of the power amplifier. Secondly, in order to increase the operating frequency of silicon-based process transistors, it is necessary to improve their RF performance by reducing the characteristic size of the transistor. This will cause the breakdown voltage of silicon-based transistors to further decrease, making it difficult for power amplifiers based on silicon-based processes to achieve the effect of high-power output. The use of stacked power amplifiers and power synthesis technology is currently a method that can effectively solve the problem.

The current mainstream dual-channel power synthesis method is the Wilkinson synthesizer, but the Wilkinson synthesizer occupies a large area. If more channels are synthesized, the occupied area will be even larger. Using on-chip transformers for multi-channel synthesis is an effective way to save area, and on-chip transformers have greater design freedom. However, using on-chip transformers for multi-channel synthesis will face the problem of high loss. The widespread use of power electronic equipment in power systems and daily life has brought convenience while also causing serious current harmonic pollution problems. Since the grid voltage is directly connected to power electronic equipment, the AC voltage is converted into DC voltage for power electronic equipment through an uncontrolled rectifier bridge circuit structure. This circuit structure not only has a low power factor but also brings current harmonic pollution to the grid, while reducing the ability of the line to transmit active power, accelerating the aging of distribution cables and substation transformers. In order to achieve efficient energy saving of electrical equipment, as well as safe operation and life extension of power grid equipment, AC-DC converters with power factor correction (PFC) have become a research hotspot in recent years. Among bridgeless PFC converters, the totem pole topology has attracted much attention in power factor correction circuit topologies due to its advantages such as small number of components, low common-mode interference, low conduction loss and high efficiency.

With the emergence of third-generation wide bandgap semiconductor devices such as gallium nitride (GaN) and silicon carbide (SiC), the diode reverse recovery problem, the first major obstacle that restricts the operation of the totem pole topology in the continuous current mode, will be solved. The switching device using this material has the advantages of fast switching speed and small on-resistance, making it possible to apply the totem pole bridgeless PFC converter in high-power occasions in the continuous current mode. At present, the bridgeless PFC converter of the totem pole topology often uses a digital processor chip to realize digital control. In order to achieve effective circuit control, voltage and current sampling of the bridgeless PFC converter is essential, including input voltage sampling and input current sampling on the AC side and output voltage sampling on the DC side. These samplings not only increase the circuit manufacturing cost and the complexity of control, but also reduce the power transmission efficiency of the bridgeless PFC converter for current sampling, and also introduce switching noise and ringing due to unreasonable circuit board wiring methods.

In many high-power applications, in order to improve the power transmission efficiency of the PFC converter, the bridgeless PFC topology is the preferred topology solution. Among them, in order to solve the input current sampling problem of the bridgeless PFC converter, there are currently several current sampling-free control methods applied to different bridgeless PFC topologies.

In the paper “Digital Current Sensorless Control for Dual-Boost Half-Bridge PFC Converter With Natural Capacitor Voltage Balancing” published in 2017 by IEEE Transactions on Power Electronics, a current sensorless control method for a dual-boost half-bridge PFC converter is introduced. The equivalent single-switch model is obtained by using the average state space method, and the duty cycle of each switching cycle is calculated under the condition that the on-state voltage drop of the switch tube and the internal resistance of the inductor are known, and finally the power factor is corrected. Patent CN202010778540.8, published in 2020, "A Current Sensorless Bridgeless PFC Circuit", introduces a current sensorless control method for a dual-boost bridgeless PFC converter, and proposes to use the time averaging method to calculate the inductor voltage of each switching cycle. Similarly, under the condition of knowing the switch tube conduction voltage drop and the inductor internal resistance, the duty cycle of each switching cycle is derived according to the inductor voltage to achieve power factor correction without current sensor. Both methods assume that the switch tube conduction voltage drop and the inductor internal resistance are known to achieve power factor correction, but because the parasitic parameters such as the inductor internal resistance, the switch tube internal resistance and the diode voltage drop are difficult to measure, and their voltage drops change with time, so when calculating the duty cycle, only an approximate value can be estimated, which makes the calculated inductor voltage deviate from the actual inductor voltage, resulting in a decrease in the power factor. When the input voltage and load change, it is difficult to maintain a high power factor.

In the article "Current-Sensorless Power Factor Correction With Predictive Controllers" published in 2019 by IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, it is proposed to use a phase-locked loop to calculate the phase angle between the grid voltage and the midpoint voltage of the bridgeless topology, and calculate the duty cycle of each switching cycle by continuously correcting the phase angle, thereby achieving power factor correction. This method ignores the loss part of the circuit in the process of calculating the phase angle, and uses the inductance of the boost inductor and the capacity of the output capacitor to participate in the calculation process. These loss power and component parameters will change during the operation of the circuit, so this method is difficult to adapt to these changes, resulting in a decrease in the power factor. In addition, the article also uses expensive analog-to-digital conversion (ADC) chips and digital signal processor (DSP) chips, which increases the cost.

It can be seen from this that the above-mentioned non-current sampling bridgeless PFC converter can only achieve constant voltage output and power factor correction by measuring some component parameters and parasitic parameters in the circuit with the help of high-performance and expensive ADC chips and DSP chips, which not only limits the improvement of power factor, but also increases the circuit cost.

Utility Model Content

The purpose of the utility model is to provide a bridgeless PFC converter system without current sampling, aiming to solve the following problems: without sampling current and measuring all component parameters and parasitic parameters in the circuit, using relatively cheap ADC chips and DSP chips to achieve constant voltage output and power factor correction, thereby reducing circuit complexity and circuit cost.

To this end, the utility model discloses a bridgeless PFC converter system without current sampling, which is composed of a main circuit module and multiple sub-modules, wherein the main circuit module is a totem pole bridgeless PFC circuit module, and the sub-modules include an auxiliary power supply, a microprocessor control module, a PWM generation module, an isolation drive circuit, an input voltage sampling module, an input zero-crossing detection module, and an output voltage sampling module;

Preferably, the totem pole bridgeless PFC circuit module is connected to the output ends of the first and second isolation drive modules, the input end of the input voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the output voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the input zero-crossing detection module is connected to the output end of the input voltage sampling module, the microprocessor control module is connected to the output ends of the input voltage sampling module, the input zero-crossing detection module and the output voltage sampling module, the PWM generation module is connected to the output end of the microprocessor control module, the first isolation drive module is connected to the output end of the PWM generation module, and the second isolation drive module is connected to the output end of the PWM generation module.

Preferably, the totem pole bridgeless PFC circuit module includes an input AC power supply _vin , a high-frequency power MOS tube Q1, a high-frequency power MOS tube Q2, a rectifier power MOS tube Q3, a rectifier power MOS tube Q4, a boost inductor L, an output filter capacitor C and a load resistor R, wherein:

The source of the high-frequency power MOS tube Q1 is respectively connected to the drain of the high-frequency power MOS tube Q2 and one end of the boost inductor L, the drain of the high-frequency power MOS tube Q1 is respectively connected to the drain of the rectifier power MOS tube Q3, the positive electrode of the output filter capacitor C, and one end of the load resistor R, the source of the high-frequency power MOS tube Q2 is respectively connected to the source of the rectifier power MOS tube Q4, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, the source of the rectifier power MOS tube Q3 is respectively connected to one end of the input AC power supply _vin and the drain of the rectifier power MOS tube Q4, the source of the rectifier power MOS tube Q4 is respectively connected to the source of the high-frequency power MOS tube Q2, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, and the other end of the boost inductor L is connected to the other end of the input AC power supply _vin ;

The two ends of the input AC power source _vin are also connected to the input end of the input voltage sampling module, and the two ends of the output filter capacitor are also connected to the input end of the output voltage sampling module.

Preferably, the connection sequence in the input voltage sampling module is the first isolated differential operational amplifier circuit, the first filter circuit, the first follower circuit, the second filter circuit and the first limiter circuit, wherein:

The input end of the first isolated differential operational amplifier circuit is connected to both ends of the input AC power supply _vin , the input end of the first filter circuit is connected to the output end of the first isolated differential operational amplifier circuit, the input end of the first follower circuit is connected to the output end of the first filter circuit, the input end of the second filter circuit is connected to the output end of the first follower circuit, and the input end of the first limiter circuit is connected to the output end of the second filter circuit;

The output end of the first limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the connection sequence in the input zero-crossing detection module is linear module circuit, comparison circuit, first resistor voltage divider circuit, third filter circuit and second amplitude limiting circuit, wherein:

The input end of the linear module circuit is connected to a 5V DC power supply, the input end of the comparison circuit is connected to the output end of the linear module circuit, the other input end of the comparison circuit is connected to the output end of the first limiter circuit, the input end of the first resistor voltage divider circuit is connected to the output end of the comparison circuit, the input end of the third filter circuit is connected to the output end of the first resistor voltage divider circuit, and the input end of the second limiter circuit is connected to the output end of the third filter circuit;

The output end of the second limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the connection order in the output voltage sampling module is the second isolated differential operational amplifier circuit, the fourth filter circuit, the second follower circuit, the second resistor voltage divider circuit, the fifth filter circuit, and the third limiter circuit, wherein:

The input end of the second isolation differential operational amplifier circuit is connected to the two ends of the output filter capacitor, the input end of the fourth filter circuit is connected to the output end of the second isolation differential operational amplifier circuit, the input end of the second follower circuit is connected to the output end of the fourth filter circuit, the input end of the second resistor voltage divider circuit is connected to the output end of the second follower circuit, the input end of the fifth filter circuit is connected to the output end of the second resistor voltage divider circuit, and the input end of the third limiter circuit is connected to the output end of the fifth filter circuit;

The output end of the third limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the microprocessor control module includes a DSP chip circuit, a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit and an overvoltage sampling protection circuit, wherein:

The DSP chip circuit is respectively connected to a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit, and an overvoltage sampling protection circuit. The DSP chip circuit serves as the core of a microprocessor control module and works in coordination with the other circuits. The output end of the DSP chip circuit is also connected to a PWM generation module.

Preferably, the connection sequence of the PWM generation module is PWM enabling circuit, buffer circuit and pull-up circuit, wherein:

The input end of the PWM enabling circuit is connected to the output end of the microprocessor control module, the input end of the buffer circuit is connected to the output end of the PWM enabling circuit, the other input end of the buffer circuit is connected to the DSP chip circuit, the input end of the pull-up circuit is connected to the output end of the buffer circuit, and the output end of the pull-up circuit is respectively connected to the first isolation driving module and the second isolation driving module.

Preferably, the first isolation driving module and the second isolation driving module have the same structure, and the modules include an isolation driving chip circuit, a bootstrap circuit, and a MOS tube driving circuit, wherein:

The input end of the isolation driving chip circuit is respectively connected to the output end of the PWM generating module, 5V and 12V DC power supplies, the input end of the bootstrap circuit is connected to the 12V DC power supply, the output end of the bootstrap circuit is connected to the output end of the isolation driving chip circuit, the input end of the MOS tube driving circuit is connected to the output end of the isolation driving chip circuit, the output end of the MOS tube driving circuit is respectively connected to the totem pole bridgeless PFC circuit module, the first isolation driving module is connected to the gates of the MOS tubes Q1 and Q2 in the totem pole bridgeless PFC circuit module, and the second isolation driving module is connected to the gates of the MOS tubes Q3 and Q4 in the totem pole bridgeless PFC circuit module.

Preferably, the auxiliary power supply is composed of a plurality of linear power chip circuits, which respectively provide 3.3V DC power supply, 5V DC power supply and 12V DC power supply.

The totem pole bridgeless PFC converter system provided by the utility model reduces the sampling circuit of the input current compared with the traditional bridgeless PFC converter, and reduces the complexity of the entire system while reducing the circuit cost. Since the current sampling circuit is not used, not only the volume of the converter is reduced, but also the conversion efficiency of the system is improved to a certain extent. In addition, the introduction of noise caused by the current sampling circuit is avoided, and the stability of the system is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the utility model, and together with the description, are used to explain the principles of the utility model.

In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a block diagram of a bridgeless PFC converter system without current sampling according to the present invention;

FIG2 is a diagram of an input voltage sampling module of the present utility model;

FIG3 is a diagram of an input zero-crossing detection module of the present utility model;

FIG4 is a diagram of an output voltage sampling module of the present invention;

FIG5 is a diagram of a microprocessor control circuit module and a PWM generation circuit module of the present utility model;

FIG6 is a block diagram of an isolation drive circuit of the present utility model;

FIG7 is a totem pole bridgeless PFC circuit topology structure of the utility model;

FIG8 is a diagram showing the first stage of operation of the totem pole bridgeless PFC circuit of the present invention;

FIG9 is a diagram showing the second stage of operation of the totem pole bridgeless PFC circuit of the present invention;

FIG10 is a diagram showing the third stage of operation of the totem pole bridgeless PFC circuit of the present invention;

FIG11 is a fourth stage of operation of the totem pole bridgeless PFC circuit of the present invention;

FIG12 is a control flow chart of a bridgeless PFC converter system without current sampling according to the present invention;

FIG13 is a flowchart of the adaptive correction of the average inductance compensation voltage in the nth to n+1th power frequency cycles of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

FIG1 of the present utility model is a block diagram of a bridgeless PFC converter system without current sampling, which is composed of a main circuit module and multiple sub-modules, wherein the main circuit module is a totem pole bridgeless PFC circuit module, and the sub-modules include an auxiliary power supply, a microprocessor control module, a PWM generation module, an isolation drive circuit, an input voltage sampling module, an input zero-crossing detection module, and an output voltage sampling module;

The totem pole bridgeless PFC circuit module is connected to the output ends of the first and second isolation drive modules, the input end of the input voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the output voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the input zero-crossing detection module is connected to the output end of the input voltage sampling module, the microprocessor control module is connected to the output ends of the input voltage sampling module, the input zero-crossing detection module and the output voltage sampling module, the PWM generation module is connected to the output end of the microprocessor control module, the first isolation drive module is connected to the output end of the PWM generation module, and the second isolation drive module is connected to the output end of the PWM generation module.

Preferably, the totem pole bridgeless PFC circuit module includes an input AC power supply _vin , a high-frequency power MOS tube Q1, a high-frequency power MOS tube Q2, a rectifier power MOS tube Q3, a rectifier power MOS tube Q4, a boost inductor L, an output filter capacitor C and a load resistor R, wherein:

The source of the high-frequency power MOS tube Q1 is respectively connected to the drain of the high-frequency power MOS tube Q2 and one end of the boost inductor L, the drain of the high-frequency power MOS tube Q1 is respectively connected to the drain of the rectifier power MOS tube Q3, the positive electrode of the output filter capacitor C, and one end of the load resistor R, the source of the high-frequency power MOS tube Q2 is respectively connected to the source of the rectifier power MOS tube Q4, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, the source of the rectifier power MOS tube Q3 is respectively connected to one end of the input AC power supply _vin and the drain of the rectifier power MOS tube Q4, the source of the rectifier power MOS tube Q4 is respectively connected to the source of the high-frequency power MOS tube Q2, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, and the other end of the boost inductor L is connected to the other end of the input AC power supply _vin ;

The two ends of the input AC power source _vin are also connected to the input end of the input voltage sampling module, and the two ends of the output filter capacitor are also connected to the input end of the output voltage sampling module.

Preferably, the connection sequence in the input voltage sampling module is the first isolated differential operational amplifier circuit, the first filter circuit, the first follower circuit, the second filter circuit and the first limiter circuit, wherein:

The input end of the first isolated differential operational amplifier circuit is connected to both ends of the input AC power supply _vin , the input end of the first filter circuit is connected to the output end of the first isolated differential operational amplifier circuit, the input end of the first follower circuit is connected to the output end of the first filter circuit, the input end of the second filter circuit is connected to the output end of the first follower circuit, and the input end of the first limiter circuit is connected to the output end of the second filter circuit;

The output end of the first limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the connection sequence in the input zero-crossing detection module is linear module circuit, comparison circuit, first resistor voltage divider circuit, third filter circuit and second amplitude limiting circuit, wherein:

The input end of the linear module circuit is connected to a 5V DC power supply, the input end of the comparison circuit is connected to the output end of the linear module circuit, the other input end of the comparison circuit is connected to the output end of the first limiter circuit, the input end of the first resistor voltage divider circuit is connected to the output end of the comparison circuit, the input end of the third filter circuit is connected to the output end of the first resistor voltage divider circuit, and the input end of the second limiter circuit is connected to the output end of the third filter circuit;

The output end of the second limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the connection order in the output voltage sampling module is the second isolated differential operational amplifier circuit, the fourth filter circuit, the second follower circuit, the second resistor voltage divider circuit, the fifth filter circuit, and the third limiter circuit, wherein:

The input end of the second isolation differential operational amplifier circuit is connected to the two ends of the output filter capacitor, the input end of the fourth filter circuit is connected to the output end of the second isolation differential operational amplifier circuit, the input end of the second follower circuit is connected to the output end of the fourth filter circuit, the input end of the second resistor voltage divider circuit is connected to the output end of the second follower circuit, the input end of the fifth filter circuit is connected to the output end of the second resistor voltage divider circuit, and the input end of the third limiter circuit is connected to the output end of the fifth filter circuit;

The output end of the third limiting circuit is also connected to the input end of the microprocessor control module.

Preferably, the microprocessor control module includes a DSP chip circuit, a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit and an overvoltage sampling protection circuit, wherein:

The DSP chip circuit is respectively connected to a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit, and an overvoltage sampling protection circuit. The DSP chip circuit serves as the core of a microprocessor control module and works in coordination with the other circuits. The output end of the DSP chip circuit is also connected to a PWM generation module.

Preferably, the connection sequence of the PWM generation module is PWM enabling circuit, buffer circuit and pull-up circuit, wherein:

The input end of the PWM enabling circuit is connected to the output end of the microprocessor control module, the input end of the buffer circuit is connected to the output end of the PWM enabling circuit, the other input end of the buffer circuit is connected to the DSP chip circuit, the input end of the pull-up circuit is connected to the output end of the buffer circuit, and the output end of the pull-up circuit is respectively connected to the first isolation driving module and the second isolation driving module.

Preferably, the first isolation driving module and the second isolation driving module have the same structure, and the modules include an isolation driving chip circuit, a bootstrap circuit, and a MOS tube driving circuit, wherein:

The input end of the isolation driving chip circuit is respectively connected to the output end of the PWM generating module, 5V and 12V DC power supplies, the input end of the bootstrap circuit is connected to the 12V DC power supply, the output end of the bootstrap circuit is connected to the output end of the isolation driving chip circuit, the input end of the MOS tube driving circuit is connected to the output end of the isolation driving chip circuit, and the output end of the MOS tube driving circuit is respectively connected to the totem pole bridgeless PFC circuit module. The first isolation driving module is connected to the gates of the MOS tubes Q1 and Q2 in the totem pole bridgeless PFC circuit module, and the second isolation driving module is connected to the gates of the MOS tubes Q3 and Q4 in the totem pole bridgeless PFC circuit module.

Preferably, the auxiliary power supply is composed of a plurality of linear power chip circuits, which respectively provide 3.3V DC power supply, 5V DC power supply and 12V DC power supply.

The utility model further discloses the working principles of the corresponding modules on the basis of the module connection relationship.

FIG2 is a diagram of an input voltage sampling module. Vin ₊ and Vin- are connected to the upper and lower ends of the input AC voltage source in FIG8, _respectively , and the input AC voltage is converted to a 0-3.3V voltage through the first isolated differential op amp circuit, and a 1.5V DC voltage bias is added to the first isolated differential op amp circuit to achieve undistorted negative input voltage sampling. The converted 0-3.3V voltage is then sent to the first filter circuit for filtering, and then to the first follower circuit to reduce the output impedance. Finally, it is sent to the second filter circuit and the first limiter circuit to obtain the input sampling voltage _{Vin_adc} .

FIG3 is a diagram of an input zero-crossing detection module. The positive input terminal of the comparison circuit is connected to the input sampling voltage V _{in_adc} , and the negative input terminal is connected to the 1.5V output DC voltage of the linear power supply chip. The comparison circuit outputs 0V and 5V level signals, which are sent to the first resistor divider circuit, the third filter circuit, and the second limiter circuit to obtain the input voltage zero-crossing detection voltage level signal V _priority .

FIG4 is a diagram of an output voltage sampling module, in which V _o+ and V _o- are respectively connected to the positive and negative electrodes of the output capacitor C in FIG8 , and the voltage between the two points is the output voltage of the totem pole bridgeless PFC circuit. The output voltage is sent to the second isolated differential operational amplifier circuit, the output voltage is converted into a 0-5V voltage and sent to the fourth filter circuit for filtering, and then the filtered voltage is sent to the second follower circuit and the second resistor voltage divider circuit to obtain a 0-3.3V sampling voltage, and finally sent to the fifth filter circuit and the third limiter circuit to obtain the output sampling voltage V _{o_adc} .

The left part of Figure 5 is a module diagram of the microprocessor control circuit, with the DSP chip circuit as the center and sub-circuits with their own functions around it. Among them, the chip power supply circuit provides power for the DSP chip, the reset circuit is an external circuit that can manually reset the DSP program, the JTAG downloader circuit is a program download communication circuit between the computer and the DSP chip, the external ADC reference voltage circuit provides an accurate 3V reference power supply for the ADC sampling module in the DSP, the button circuit and the display circuit are external functional circuits of the DSP to realize button interrupt triggering and display of necessary information, and the overvoltage sampling protection provides a safe input voltage for the ADC pin of the DSP to protect the safe operation of the DSP.

The right part of Figure 5 is a block diagram of the PWM generation circuit. The input end of the PWM enable circuit is connected to the two output IO pins of the DSP chip, so that the DSP can control the output level of the PWM enable circuit through the program. The output level signal is connected to the buffer chip enable pin in the buffer circuit, so as to control the output pin of the buffer chip to generate an output PWM signal. In addition, the input of the buffer chip is connected to the four PWM output IO pins of the DSP chip. The four-channel PWM signal is controlled by the buffer chip to be output. At the same time, the four-channel PWM output signals of the buffer chip are output with 0V and 5V level signals after passing through the pull-up circuit, so as to meet the PWM level requirements of the isolation driver chip.

Figure 6 is a diagram of the isolation drive circuit module, in which U7 is a half-bridge isolation drive chip. While the VIA and VIB pins of the chip are respectively connected to R28 and R29 to form a forced low-level pull-down circuit, they are also respectively connected to the PWM generating circuit module, and the output signals PWMxA and PWMxB of the PWM generating circuit module are determined by the DSP, where x is 1 or 2. When x is 1, Figure 7 is the first isolation drive circuit and is connected to the power switch tube of the high-frequency bridge arm. When x is 2, Figure 7 is the second isolation drive circuit and is connected to the power switch tube of the low-frequency bridge arm.

In Figure 6, the 12V DC power supply is connected to the VDDA pin of the chip after passing through the bootstrap circuit to provide driving power for the upper tubes Q1 and Q3 in the high and low frequency bridge arms, and the 12V power supply is directly used to provide driving power for the lower tubes Q2 and Q4 in the high and low frequency bridge arms. VOA and VOB are driving signals and are connected to the driving circuit, GNDxA and GNDxB are connected to the GNDA and GNDB of the chip respectively, and GxA and GxB are connected to the gate control terminal of the upper tube and the gate control terminal of the lower tube of the bridge arm respectively to drive the switch tube to turn on and off.

Based on the working principle of the above circuit module diagram, the present invention further discloses and explains the control method in the microprocessor control module.

FIG7 is a totem pole bridgeless PFC circuit topology structure of the utility model, which includes: high-frequency power MOS tubes Q1 and Q2, low-frequency rectifier power MOS tubes Q3 and Q4, and internal parallel diodes D1, D2 and D3, D4 of Q1, Q2, Q3, Q4, in addition to a power boost inductor L, an output filter capacitor C, an input AC voltage source _vin and an output load resistor R, and considering the parasitic parameters that may exist in the actual circuit, there are also an inductor internal resistance _rL and a MOS tube conduction internal resistance _rds ; Q1 and Q2 form a high-frequency bridge arm, Q3 and Q4 form a low-frequency rectifier bridge arm, the input AC voltage source is connected in series with the boost inductor, and is connected to the midpoint of the two bridge arms to form a closed loop of the input part; the two bridge arms are connected in parallel with the filter capacitor C and the output load resistor R to form a closed loop of the output part; the common component of the two closed loops is composed of two groups of bridge arms, namely the AC-DC conversion part.

Preferably, referring to Figures 8-11, when the input AC voltage is in the positive half cycle, Q2 and Q4 are turned on, Q1 and Q3 are turned off, and the current flows from left to right through the boost inductor L. The voltage on the inductor is positive on the left and negative on the right. This process stores energy in the boost inductor L; the current flows from the positive electrode of the capacitor C to the load resistor R, and finally returns to the negative electrode of the capacitor C. In this process, the capacitor provides energy for the load and maintains the output voltage constant;

When the input AC voltage is still in the positive half cycle, Q1 and Q4 are turned on, Q2 and Q3 are turned off, and the current flows from left to right through the boost inductor L. The voltage on the inductor is negative on the left and positive on the right. In this process, the boost inductor L releases energy; part of the freewheeling current flows into the output filter capacitor C to charge and store energy for the capacitor C; the other part of the current flows into the output load resistor R to provide energy for the load and maintain the constant output voltage;

When the input AC voltage is in the negative half cycle, Q1 and Q3 are turned on, Q2 and Q4 are turned off, and the current flows from right to left through the boost inductor L. The voltage on the inductor is negative on the left and positive on the right. This process stores energy in the boost inductor L. The current flows from the positive electrode of the capacitor C to the load resistor R, and finally returns to the negative electrode of the capacitor C. In this process, the capacitor provides energy for the load and maintains the output voltage constant.

The input AC voltage is still in the negative half cycle, Q2 and Q3 are turned on, Q1 and Q4 are turned off, and the current flows from right to left through the boost inductor L. The voltage on the inductor is positive on the left and negative on the right. During this process, the boost inductor L releases energy. At the same time, part of the freewheeling current flows into the output filter capacitor C to charge and store energy for the capacitor C. The other part of the current flows into the output load resistor R to provide energy for the load and maintain the output voltage constant.

The utility model discloses a control of a bridgeless PFC converter system, referring to FIGS. 12-13 , including:

Step 100, establishing a mathematical model of the average inductor voltage in the totem pole bridgeless PFC circuit using a time averaging method;

Step 200, the sampled output voltage is sent to the DSP to calculate the actual output voltage, the difference between the output voltage and the reference voltage is input to the PID controller, and the output of the PID controller is the average inductor peak voltage;

Step 300, setting a compensation item to compensate for the average inductor voltage, the compensation item being the average inductor compensation voltage, so that the average inductor voltage calculated at any time is the same as the average inductor voltage during actual circuit operation;

Step 400, the compensation item is adaptively corrected and controlled; by comparing the average inductance compensation peak voltage with the average inductance reference compensation peak voltage, it is determined whether the output voltage ripple phase angle is zero. If it is not zero, the average inductance reference compensation peak voltage is used as the average inductance compensation peak voltage of the next power frequency cycle. After a finite number of power frequency cycles, the average inductance compensation peak voltage is equal to the average inductance reference compensation peak voltage, that is, the output voltage ripple phase angle tends to zero within a finite time, so that the power factor of the totem pole bridgeless PFC circuit tends to 1, thereby realizing adaptive correction of the average inductance compensation peak voltage.

Step 500, the duty cycle in each switching cycle is calculated according to the calculation results of the average inductance peak voltage and the average inductance compensation peak voltage, and the corresponding control signal is output through the PWM driving module to control the circuit.

The totem pole bridgeless PFC converter system provided by the utility model uses a totem pole bridgeless PFC circuit topology structure. Under the condition of considering parasitic parameters such as inductor internal resistance and switch tube internal resistance, a mathematical model of the circuit topology is modeled. The expression of the inductor voltage is calculated by the time averaging method, and a reasonable compensation voltage is added to the expression to compensate for the deviation between the calculated inductor voltage and the inductor voltage in the actual circuit, so as to further improve the power factor. Then, the corresponding compensation reference voltage is calculated by the phase information of the output voltage ripple, so that the compensation voltage approaches the compensation reference voltage until the compensation voltage is stabilized at the compensation reference voltage in the steady state, so as to realize the correction of the power factor and reduce the influence of parasitic parameters on the power factor. The advantages include the following: (1) The sampling circuit of the input current is reduced, and the complexity of the whole system is reduced. (2) Since the current sampling circuit is not used, not only the volume of the converter is reduced, but also the conversion efficiency of the system is improved to a certain extent. (3) The introduction of noise caused by the current sampling circuit is avoided, and the stability of the system is improved. (4) No high-precision ADC sampling chip is used to sample the input voltage and output voltage, so as to save circuit cost.

Preferably, step 100, using a time averaging method to establish a mathematical model of the average inductor voltage in the totem pole bridgeless PFC circuit, includes: four working stages of the totem pole bridgeless PFC circuit topology, t represents the t-th moment in a power frequency cycle, and lists the inductor voltages v _L (t) in the four stages:

The first stage: v _L (t) = v _in (t) - i _L (t) × (r _L + r _ds );

The second stage: v _L (t) = v _in (t) - i _L (t) × (r _L + r _ds ) - v _o (t);

The third stage: v _L (t) = v _in (t) - i _L (t) × (r _L + r _ds );

The fourth stage: v _L (t) = v _in (t)-i _L (t) × (r _L + r _ds ) + v _o (t);

Where i _L (t) represents the inductor current corresponding to the output voltage DC value V _dc , which is also the input current.

Let x _Ts represent the average value of variable x in one switching cycle. Let the on-time in one switching cycle be T _on and the switching cycle be T _s . Then the average values of input AC voltage and input AC current in one switching cycle are expressed as:

Combining the inductor voltage v _L (t) in the four phases, the average inductor voltage in one switching cycle is obtained as:

v _L (t) _Ts ＝v _in (t) _Ts -i _L (t) _Ts (r _L +r _ds )-sign(v _in (t))(1-d(t))v _o (t)( 1)

The duty cycle d(t) is the ratio of the on-time to the switching period, and sign( _vin ) is the sign function of _vin :

Preferably, step 200 sends the sampled output voltage to DSP to calculate the actual output voltage, and the difference between the output voltage and the reference voltage is input to the PID controller, and the output of the PID controller is the average inductor peak voltage; including: using an isolated differential sampling circuit to sample the input and output voltages, converting the sampled signal into a voltage signal of 0 to 3.3V through a resistor voltage divider circuit, and transmitting it to the DSP chip; then the DSP chip converts the feedback output voltage through ADC, calculates the actual output voltage v _o , subtracts the set reference output voltage V _ref from the output voltage v _o to obtain the output voltage error value v _err , and then inputs v _err into the PID controller for calculation, and the output result is used as the average peak voltage V _m of the inductor; after the output voltage is stable, the output DC voltage V _dc is equal to the reference output voltage V _ref .

Assume that the power frequency period is _Tg . When the input AC voltage and the input AC current are both sinusoidal waves with the same phase, calculate the average value of the inductor current in one switching cycle:

表示正弦输入电流的平均电流峰值。设电感的阻抗为ωL，根据欧姆定律，求出平均电感电压的峰值V_m，并代入式(2)可得：in

Represents the average current peak value of the sinusoidal input current. Assuming the impedance of the inductor is ωL, according to Ohm's law, the peak value of the average inductor voltage V _m is calculated and substituted into formula (2) to obtain:

求出平均电感电压：According to the inductor voltage formula

Find the average inductor voltage:

Assume _Vin is the peak value of the input AC voltage, _Io is the output load current, when the circuit conversion efficiency is 100%, the input power is equal to the output power: Combined with formula (3), the expression of the output voltage DC quantity is derived:

维持输出电压V_dc不变；当输入交流电压减小或负载电流增大时，可通过增大

维持输出电压V_dc不变。It can be seen from formula (5) that when the input AC voltage increases or the load current decreases,

Maintain the output voltage V _dc unchanged; when the input AC voltage decreases or the load current increases,

Maintain the output voltage V _dc unchanged.

在输出电压稳定后，输出直流电压V_dc等于参考输出电压V_ref。According to the above formula, the corresponding PID voltage controller is designed: the input and output voltages are sampled using an isolated differential sampling circuit, and the sampled signals are converted into voltage signals of 0 to 3.3V through a resistor voltage divider circuit and transmitted to the DSP chip. Then the DSP chip converts the feedback output voltage through an ADC, calculates the actual output voltage v _o , and subtracts the output voltage v _o from the set reference output voltage V _ref to obtain the output voltage error value v _err , and then inputs v _err into the PID program for calculation, and the output result is used as the average peak voltage of the inductor.

After the output voltage is stabilized, the output DC voltage V _dc is equal to the reference output voltage V _ref .

为零，并有推导的等式为：Preferably, step 300 sets a compensation item to compensate the average inductor voltage, and the compensation item is the average inductor compensation voltage, so that the average inductor voltage calculated at any time is the same as the average inductor voltage when the actual circuit is running, including: in order to make the input current a sinusoidal current, that is, the power factor is 1, the phase angle

is zero, and the derived equation is:

At the input voltage peak moment _ta , the instantaneous value of the output voltage is V _dc , and the corresponding duty cycle at this time is d _a . Substituting it into equation (6) to obtain the reference value of the average compensation peak voltage of the inductor is:

即为下一个工频周期的平均电感补偿电压参考值，根据

的计算结果，可在下一个工频周期对

做出相应的校正。In the above formula

That is the average inductance compensation voltage reference value of the next power frequency cycle.

The calculation results can be used in the next power frequency cycle

Make corresponding corrections.

Specifically, since there are always various losses in the circuit, it is difficult for the circuit conversion efficiency to reach 100%, and these losses are mainly caused by various parasitic parameters. Without reducing the output power, it is necessary to increase the input power to compensate for the power lost in the circuit. Therefore, in formula (1), there will be a deviation between the calculated average inductor voltage and the average inductor voltage of the actual circuit.

In order to improve the power factor and make the input AC current present a standard sine wave, the average inductor voltage of each switching cycle needs to be compensated so that the calculated average inductor voltage is the same as the actual average inductor voltage.

Assume that the average compensated inductor voltage <Δv _L (t)> _Ts is:

<Δv _L (t)> _Ts = (r _L +r _ds ) <Δi _L (t)> _Ts (9)

为补偿的平均电感电压峰值，则<Δi_L(t)>_Ts可表示为：Where <Δi _L (t)> _Ts is the corresponding average inductor compensation current.

is the average inductor voltage peak value to be compensated, then <Δi _L (t)> _Ts can be expressed as:

Adding equation (10) to equation (1), we can get a new expression for the average inductor voltage:

<v _L (t)> _Ts ＝<v _in (t)> _Ts -(<i _L (t)> _Ts +<Δi _L (t)> _Ts )(r _L +r _ds )-(1-d( t))v _o (t) (11)

By transforming the above formula, the actual duty cycle d _real (t) is obtained as:

Assuming the sum of the inductor internal resistance and the MOS tube internal resistance is r _par , the above formula includes a term of internal resistance, that is, the average sum of the voltages across the inductor internal resistance and the MOS tube internal resistance in the actual circuit <v _par (t)> _Ts can be expressed as:

Analyzing equations (1) and (11), when a suitable average inductor compensation voltage <Δv _L (t)> _Ts is added, the calculated average inductor voltage is equal to the actual average inductor voltage, making the input AC current present a standard sine wave.

However, since the input current is not sampled in the actual circuit, the information about the input current is unknown, and it is impossible to directly determine whether the input AC current is a standard sine wave. In order to solve this problem, information about the input AC current can be found from the low-frequency ripple phase of the output voltage, and whether the input current is a standard sine wave can be determined, thereby indirectly controlling the input AC current.

The low-frequency ripple of the output voltage is derived. The output low-frequency ripple voltage v _ripple (t) is obtained as:

因此实际的输出电压v_o(t)为：From the above formula, we can see that when the power factor is equal to 1, the phase angle of the low-frequency ripple of the output voltage is zero. When there is component loss in the circuit, the power factor is less than 1, and the low-frequency ripple of the output voltage produces a phase angle

Therefore, the actual output voltage v _o (t) is:

为零，因此，将式(15)和

代入式(11)，化简求出以下等式：Comparing equations (14) and (15), we can see that in order to make the input current a sinusoidal current, that is, the power factor is 1, the phase angle

is zero, therefore, we can transform equation (15) and

Substituting into equation (11), we can simplify and obtain the following equation:

At the input voltage peak moment _ta , the instantaneous value of the output voltage is V _dc , and the corresponding duty cycle at this time is d _a . Substituting it into equation (12), the reference value of the average compensation peak voltage of the inductor is obtained as equation (8):

即为下一个工频周期的平均电感补偿电压参考值，根据

的计算结果，可在下一个工频周期对

做出相应的校正。In formula (8)

That is the average inductance compensation voltage reference value of the next power frequency cycle.

The calculation results can be used in the next power frequency cycle

Make corresponding corrections.

Preferably, the compensation item in step 400 is adaptively corrected and controlled, including: assuming that the circuit is in the nth power frequency cycle, substituting the sampled input voltage v _in (t) and output voltage v _o (t) into the formula to calculate the duty cycle of each switching cycle, and controlling the circuit until the end of the last switching cycle, substituting the duty cycle d _a [n] corresponding to the time t _a [n] in the nth power frequency cycle into the formula (8) to calculate the average compensation reference peak voltage of the inductor

与

是否相等，若相等则不需要修正

若不相等则根据

与

的差值计算第n个工频周期的修正量α，并在第n+1个工频周期使

经过有限个工频周期的修正，使得

逐渐逼近于

最终电路进入稳态后满足

Then judge

and

Are they equal? If they are equal, no correction is needed.

If not equal, then according to

and

The difference between the two is used to calculate the correction value α for the nth power frequency cycle, and the correction value α is used for the n+1th power frequency cycle.

After a finite number of power frequency cycles,

Gradually approaching

Finally, the circuit enters a steady state and satisfies

和

的公式推导以及

与功率因数之间的关系，可以得出以下结论：当平均电感补偿峰值电压

等于平均电感参考补偿峰值电压

时，功率因数等于1，输入交流电流为标准的正弦波。Specifically, according to the above

and

The formula derivation and

The relationship between the average inductance and the power factor leads to the following conclusion: when the average inductance compensates the peak voltage

Equal to the average inductor reference compensation peak voltage

When the power factor is equal to 1, the input AC current is a standard sine wave.

Preferably, step 500 includes: calculating the duty cycle in each switching cycle according to the calculation results of the average inductance peak voltage and the average inductance compensation peak voltage, and outputting a corresponding control signal through the PWM drive module to control the circuit, including: duty cycle expression (12).

使得补偿后的平均电感电压等于实际电路的平均电感电压即可实现功率因数的校正，因此避免了元件参数和寄生参数对功率因数的影响。In the case of the positive and negative half cycles of the input AC voltage, the above duty cycle is applicable. Therefore, in DSP, the duty cycle of each switching cycle can be directly calculated using formula (12). Although L, r _L and r _ds are unknown in the formula, it can be seen from the above analysis that only the adjustment

The power factor can be corrected by making the average inductor voltage after compensation equal to the average inductor voltage of the actual circuit, thereby avoiding the influence of component parameters and parasitic parameters on the power factor.

和输入电流校正模块的输出

共同参与占空比的计算，将计算出的占空比经过PWM模块转换成对应的方波信号，再通过驱动芯片输出驱动信号对开关管Q1和Q2进行控制。与此同时，通过输入电压过零检测电平信号分别对开关管Q3和Q4给与驱动信号，即在输入交流电压正半周时，Q4导通，Q3关断，在输入交流电压负半周时，Q3导通，Q4关断。Preferably, in the DSP program, a reasonable initial value can be set for L, r _L and r _ds , such as L = 1mH, r _L = 0.1Ω and r _ds = 1Ω, and then the output voltage of the output control module is

and the output of the input current correction module

They participate in the calculation of the duty cycle together, convert the calculated duty cycle into a corresponding square wave signal through the PWM module, and then output the drive signal through the driver chip to control the switch tubes Q1 and Q2. At the same time, the input voltage zero-crossing detection level signal is used to give drive signals to the switch tubes Q3 and Q4, that is, when the input AC voltage is in the positive half cycle, Q4 is turned on and Q3 is turned off, and when the input AC voltage is in the negative half cycle, Q3 is turned on and Q4 is turned off.

The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features applied herein.

Claims (9)

1. A bridgeless PFC converter system without current sampling, characterized in that the system is composed of a main circuit module and a plurality of sub-modules, wherein the main circuit module is a totem pole bridgeless PFC circuit module, and the sub-modules include an auxiliary power supply, a microprocessor control module, a PWM generation module, an isolation drive circuit, an input voltage sampling module, an input zero-crossing detection module and an output voltage sampling module; The totem pole bridgeless PFC circuit module is connected to the output ends of the first and second isolation drive modules, the input end of the input voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the output voltage sampling module is connected to the totem pole bridgeless PFC circuit module, the input end of the input zero-crossing detection module is connected to the output end of the input voltage sampling module, the microprocessor control module is connected to the output ends of the input voltage sampling module, the input zero-crossing detection module and the output voltage sampling module, the PWM generation module is connected to the output end of the microprocessor control module, the first isolation drive module is connected to the output end of the PWM generation module, and the second isolation drive module is connected to the output end of the PWM generation module. 2. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the totem pole bridgeless PFC circuit module comprises an input AC power supply _vin , a high-frequency power MOS tube Q1, a high-frequency power MOS tube Q2, a rectifier power MOS tube Q3, a rectifier power MOS tube Q4, a boost inductor L, an output filter capacitor C and a load resistor R, wherein: The source of the high-frequency power MOS tube Q1 is respectively connected to the drain of the high-frequency power MOS tube Q2 and one end of the boost inductor L, the drain of the high-frequency power MOS tube Q1 is respectively connected to the drain of the rectifier power MOS tube Q3, the positive electrode of the output filter capacitor C, and one end of the load resistor R, the source of the high-frequency power MOS tube Q2 is respectively connected to the source of the rectifier power MOS tube Q4, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, the source of the rectifier power MOS tube Q3 is respectively connected to one end of the input AC power supply _vin and the drain of the rectifier power MOS tube Q4, the source of the rectifier power MOS tube Q4 is respectively connected to the source of the high-frequency power MOS tube Q2, the negative electrode of the output filter capacitor C, and the other end of the load resistor R, and the other end of the boost inductor L is connected to the other end of the input AC power supply _vin ; The two ends of the input AC power source _vin are also connected to the input end of the input voltage sampling module, and the two ends of the output filter capacitor are also connected to the input end of the output voltage sampling module. 3. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the connection order in the input voltage sampling module is the first isolation differential operational amplifier circuit, the first filter circuit, the first follower circuit, the second filter circuit and the first limiter circuit, wherein: The input end of the first isolated differential operational amplifier circuit is connected to both ends of the input AC power supply _vin , the input end of the first filter circuit is connected to the output end of the first isolated differential operational amplifier circuit, the input end of the first follower circuit is connected to the output end of the first filter circuit, the input end of the second filter circuit is connected to the output end of the first follower circuit, and the input end of the first limiter circuit is connected to the output end of the second filter circuit; The output end of the first limiting circuit is also connected to the input end of the microprocessor control module. 4. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the connection sequence in the input zero-crossing detection module is a linear module circuit, a comparison circuit, a first resistor voltage divider circuit, a third filter circuit and a second limiter circuit, wherein: The input end of the linear module circuit is connected to a 5V DC power supply, the input end of the comparison circuit is connected to the output end of the linear module circuit, the other input end of the comparison circuit is connected to the output end of the first limiter circuit, the input end of the first resistor voltage divider circuit is connected to the output end of the comparison circuit, the input end of the third filter circuit is connected to the output end of the first resistor voltage divider circuit, and the input end of the second limiter circuit is connected to the output end of the third filter circuit; The output end of the second limiting circuit is also connected to the input end of the microprocessor control module. 5. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the connection order in the output voltage sampling module is the second isolated differential operational amplifier circuit, the fourth filter circuit, the second follower circuit, the second resistor voltage divider circuit, the fifth filter circuit, and the third limiter circuit, wherein: The input end of the second isolation differential operational amplifier circuit is connected to the two ends of the output filter capacitor, the input end of the fourth filter circuit is connected to the output end of the second isolation differential operational amplifier circuit, the input end of the second follower circuit is connected to the output end of the fourth filter circuit, the input end of the second resistor voltage divider circuit is connected to the output end of the second follower circuit, the input end of the fifth filter circuit is connected to the output end of the second resistor voltage divider circuit, and the input end of the third limiter circuit is connected to the output end of the fifth filter circuit; The output end of the third limiting circuit is also connected to the input end of the microprocessor control module. 6. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the microprocessor control module includes a DSP chip circuit, a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit and an overvoltage sampling protection circuit, wherein: The DSP chip circuit is respectively connected to a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit, and an overvoltage sampling protection circuit. The DSP chip circuit serves as the core of a microprocessor control module and works in coordination with the other circuits. The output end of the DSP chip circuit is also connected to a PWM generation module. 7. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the connection sequence of the PWM generation module is PWM enabling circuit, buffer circuit and pull-up circuit, wherein: The input end of the PWM enabling circuit is connected to the output end of the microprocessor control module, the input end of the buffer circuit is connected to the output end of the PWM enabling circuit, the other input end of the buffer circuit is connected to the DSP chip circuit, the input end of the pull-up circuit is connected to the output end of the buffer circuit, and the output end of the pull-up circuit is respectively connected to the first isolation driving module and the second isolation driving module. 8. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the first isolation driving module and the second isolation driving module have the same structure, and the modules include an isolation driving chip circuit, a bootstrap circuit, and a MOS tube driving circuit, wherein: The input end of the isolation driving chip circuit is respectively connected to the output end of the PWM generating module, 5V and 12V DC power supplies, the input end of the bootstrap circuit is connected to the 12V DC power supply, the output end of the bootstrap circuit is connected to the output end of the isolation driving chip circuit, the input end of the MOS tube driving circuit is connected to the output end of the isolation driving chip circuit, the output end of the MOS tube driving circuit is respectively connected to the totem pole bridgeless PFC circuit module, the first isolation driving module is connected to the gates of the MOS tubes Q1 and Q2 in the totem pole bridgeless PFC circuit module, and the second isolation driving module is connected to the gates of the MOS tubes Q3 and Q4 in the totem pole bridgeless PFC circuit module. 9. A bridgeless PFC converter system without current sampling according to claim 1, characterized in that the auxiliary power supply is composed of a plurality of linear power chip circuits, which respectively provide 3.3V DC power supply, 5V DC power supply and 12V DC power supply.

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