CN218771769U

CN218771769U - Bridgeless PFC converter system without current sampling

Info

Publication number: CN218771769U
Application number: CN202222386937.XU
Authority: CN
Inventors: 李志忠; 姚润峰; 刘焕彬; 卢智轩; 谭乐彬
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2023-03-28
Anticipated expiration: 2032-09-05

Abstract

The utility model discloses a no bridge PFC converter system of no current sampling specifically comprises a plurality of modules, is totem pole no bridge PFC circuit module, input voltage sampling module, input zero cross detection module, output voltage sampling module, microprocessor control module, PWM generation module and first, second keep apart drive module and auxiliary power supply respectively, has got rid of input current sampling circuit in the system. The utility model provides a no bridge PFC converter system of no current sampling solves under the condition of not sampling current and not all components and parts parameters and parasitic parameter among the measuring circuit, utilizes the DSP chip to carry out digital control, realizes power factor correction and constant voltage output, the technical problem of the complexity and the circuit cost of lowering system.

Description

Bridgeless PFC converter system without current sampling

Technical Field

The utility model relates to a switching power supply technical field, in particular to no bridge PFC converter system of no current sampling.

Background

With the development and change of the times, the use of wireless communication is getting deeper into people's daily life, such as bluetooth, wireless local area network (WIFI), and global positioning satellite (gps) technologies. A transceiver is an important device for implementing wireless communication, and a power amplifier plays an extremely important role in the transceiver.

The current mainstream power amplifier design process is GaAs and GaN because they have good radio frequency performance and can withstand high power output. However, the integration of the whole transceiver chip is difficult by adopting the mainstream design process, and the problem of high cost is faced. Silicon-based process design has the advantage of high integration, but designing a power amplifier using silicon-based process is still a challenging task. Firstly, the power amplifier efficiency is reduced because the silicon-based process design faces a problem of large loss of a passive device. Secondly, in order to increase the operating frequency of the silicon-based process transistor, the rf performance of the transistor needs to be improved by reducing the feature size of the transistor. This will cause the breakdown voltage of the silicon-based transistor to further decrease, making it difficult for the power amplifier based on the silicon-based technology to achieve the effect of outputting high power. The use of stacked power amplifiers and the use of power combining techniques are currently one way to effectively solve the problem.

At present, the mainstream two-way power synthesis mode is a Wilkinson synthesizer, but the Wilkinson synthesizer occupies a large area, and if synthesis is carried out by more paths, the occupied area is larger. The on-chip transformer is used for carrying out multi-path synthesis, which is a method capable of effectively saving area, and has larger design freedom. However, the use of on-chip transformers for multiplexing would suffer from high losses. The wide use of power electronic equipment in power systems and daily life has also had serious current harmonic pollution problem when having brought conveniently. Because the power grid voltage is directly connected with the power electronic equipment, the alternating voltage is converted into the direct voltage for the power electronic equipment to use through an uncontrolled rectifier bridge circuit structure, the circuit structure has low power factor and can bring current harmonic pollution to the power grid, and simultaneously, the capacity of the line for transmitting active power is reduced, so that the power distribution cable and the transformer of the transformer substation are accelerated to age. In order to save energy and improve the efficiency of power-consuming devices and to extend the safe operation and life of power grid devices, in recent years, ac-dc converters with Power Factor Correction (PFC) have become a research focus, wherein in bridgeless PFC converters, totem-pole topologies are focused on power factor correction circuit topologies due to the advantages of small number of components, low common-mode interference, low conduction loss, high efficiency, and the like.

With the emergence of third-generation wide-bandgap semiconductor devices such as gallium nitride (GaN) and silicon carbide (SiC), the problem of diode reverse recovery, which is the first large resistance that restricts the operation of totem-pole topology in a continuous current mode, is readily solved, and a switching device using the material has the advantages of high switching speed, small on-resistance and the like, so that the totem-pole bridgeless PFC converter can be applied in a high-power occasion in the continuous current mode. At present, a totem-pole topological bridgeless PFC converter usually uses a digital processor chip to realize digital control, and in order to realize effective circuit control, voltage and current sampling of the bridgeless PFC converter is indispensable, wherein the voltage and current sampling comprises input voltage sampling at an alternating current side, input current sampling and output voltage sampling at a direct current side, the sampling not only increases the manufacturing cost of a circuit and the complexity of control, but also reduces the electric energy transmission efficiency of the bridgeless PFC converter through the current sampling, and also introduces switching noise and ringing due to an unreasonable circuit board wiring mode.

In many high-power applications, a bridgeless PFC topology is a preferred topology for improving the power transmission efficiency of the PFC converter. In order to solve the problem of sampling the input current of the bridgeless PFC converter, several control methods without current sampling are applied to different bridgeless PFC topologies.

In the document "Digital Current sensor Control of a double Boost Half Bridge PFC Converter With Natural capacitance and Voltage balance", published in 2017 by IEEE Transactions on Power Electronics, a currentless sensor Control method of a double Boost PFC Half Bridge Converter is introduced, an equivalent single switch mode is obtained by using an average state space method, and under the condition that no Voltage drop and no inductance knowledge are available in a switch, the duty ratio of each switch period is calculated, and finally the Power factor is corrected. The patent CN202010778540.8 discloses a "bridgeless PFC circuit without current sensor" in 2020, which introduces a method for controlling a bridgeless PFC converter without current sensor with double boost, and proposes to calculate an inductor voltage in each switching period by using a time averaging method, and derive a duty cycle in each switching period according to the inductor voltage under the condition that a conduction voltage drop and an inductor internal resistance of a switching tube are known, so as to implement power factor correction of the bridgeless PFC converter. Both methods can achieve power factor correction only under the assumption of the known conditions of the switch tube conduction voltage drop and the inductor internal resistance, but because parasitic parameters of the inductor internal resistance, the switch tube internal resistance and the diode voltage drop are difficult to measure and the voltage drops of the parasitic parameters change along with time, only an approximate value can be estimated when calculating the duty ratio, so that the calculated inductor voltage deviates from the actual inductor voltage, the power factor is reduced, and when the input voltage and the load change, the high power factor is difficult to maintain all the time.

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRICICS (IEEE POWER ELECTRONIC NEW AND SUITORED SUBJECT JOURNAL) IN 2019, IN a document "Current-Sensorless Power Factor Correction With Predictive Controllers" [ use OF a Predictive controller for POWER Factor Correction without a Current sensor ], it is proposed to calculate a phase angle between a grid voltage AND a point voltage IN a bridgeless topology by using a phase-locked loop, AND calculate a duty ratio OF each switching period by continuously correcting the phase angle, thereby realizing the Correction OF the POWER Factor. The method ignores the loss part of the circuit in the process of calculating the phase angle, simultaneously utilizes the inductance of the boost inductor and the capacity of the output capacitor to participate in the calculation process, the power and element parameters of the loss change when the circuit runs, and therefore the method is difficult to adapt to the changes, so that the power factor is reduced. Expensive analog-to-digital conversion (ADC) chips and Digital Signal Processor (DSP) chips are also used, increasing cost.

Therefore, the current-sampling-free bridgeless PFC converter can realize constant voltage output and power factor correction by means of a high-performance and expensive ADC chip and a DSP chip only under the condition of measuring partial component parameters and parasitic parameters in a circuit, so that the improvement of the power factor is limited, and the circuit cost is increased.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a no bridge PFC converter system of no current sampling aims at solving following problem: under the conditions of not sampling current and not measuring all component parameters and parasitic parameters in the circuit, the ADC chip and the DSP chip which are relatively cheap are used for realizing the correction of constant voltage output and power factor, and the complexity and the cost of the circuit are reduced.

Therefore, the utility model discloses a no bridge PFC converter system of no current sampling, this system comprises a main circuit module and a plurality of submodule piece jointly, and its main circuit module is totem pole no bridge PFC circuit module, and the submodule piece includes auxiliary power supply, microprocessor control module, PWM generation module, keeps apart drive circuit, input voltage sampling module, input zero cross detection module and output voltage sampling module;

preferably, the totem-pole bridgeless PFC circuit module is connected to output terminals of the first and second isolation driving modules, an input terminal of the input voltage sampling module is connected to the totem-pole bridgeless PFC circuit module, an input terminal of the output voltage sampling module is connected to the totem-pole bridgeless PFC circuit module, an input terminal of the input zero-cross detection module is connected to an output terminal of the input voltage sampling module, the microprocessor control module is connected to output terminals of the input voltage sampling module, the input zero-cross detection module, and the output voltage sampling module, the PWM generation module is connected to an output terminal of the microprocessor control module, the first isolation driving module is connected to an output terminal of the PWM generation module, and the second isolation driving module is connected to an output terminal of the PWM generation module.

Preferably, the totem-pole bridgeless PFC circuit module comprises an input alternating current power supply v _in High-frequency power MOS pipe Q1, high-frequency power MOS pipe Q2, rectification power MOS pipe Q3, rectification power MOS pipe Q4, boost inductance L, output filter capacitor C and load resistance R, wherein:

the source electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of the high-frequency power MOS tube Q2 and one end of a boosting inductor L, the drain electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of a rectification power MOS tube Q3, the anode of an output filter capacitor C and one end of a load resistor R, the source electrode of the high-frequency power MOS tube Q2 is respectively connected with the source electrode of a rectification power MOS tube Q4, the cathode of the output filter capacitor C and the other end of the load resistor R, and the source electrode of the rectification power MOS tube Q3 is respectively connected with an input alternating current power supply v _in The source electrode of the rectification power MOS tube Q4 is respectively connected with the source electrode of the high-frequency power MOS tube Q2, the cathode of the output filter capacitor C and the other end of the load resistor R, and the other end of the boosting inductor L is connected with the input alternating current power supply v _in The other end of the connecting rod is connected;

the input AC power supply v _in The two ends of the output filter capacitor are also connected with the input end of the input voltage sampling module, and the two ends of the output filter capacitor are also connected with the input end of the output voltage sampling module.

Preferably, the input voltage sampling module is connected with a first isolation differential operational amplifier circuit, a first filter circuit, a first follower circuit, a second filter circuit and a first amplitude limiting circuit in sequence, wherein:

the input end of the first isolation differential operational amplifier circuit and an input alternating current power supply v _in Is connected with the input end of the first filter circuit and the first isolation differential operational amplifierThe output end of the circuit is connected, the input end of the first following circuit is connected with the output end of the first filter circuit, the input end of the second filter circuit is connected with the output end of the first following circuit, and the input end of the first amplitude limiting circuit is connected with the output end of the second filter circuit;

the output end of the first amplitude limiting circuit is also connected with the input end of the microprocessor control module.

Preferably, the input zero-crossing detection module is connected with a linear module circuit, a comparison circuit, a first resistance voltage-dividing circuit, a third filter circuit and a second amplitude limiting circuit in sequence, wherein:

the input end of the linear module circuit is connected with a 5V direct-current power supply, the input end of the comparison circuit is connected with the output end of the linear module circuit, the other input end of the comparison circuit is connected with the output end of the first amplitude limiting circuit, the input end of the first resistance voltage division circuit is connected with the output end of the comparison circuit, the input end of the third filter circuit is connected with the output end of the first resistance voltage division circuit, and the input end of the second amplitude limiting circuit is connected with the output end of the third filter circuit;

and the output end of the second amplitude limiting circuit is also connected with the input end of the microprocessor control module.

Preferably, the output voltage sampling module is connected with a second isolation differential operational amplifier circuit, a fourth filter circuit, a second follower circuit, a second resistance voltage divider circuit, a fifth filter circuit and a third amplitude limiting circuit in sequence, wherein:

the input end of the second isolation differential operational amplifier circuit is connected with two ends of the output filter capacitor, the input end of the fourth filter circuit is connected with the output end of the second isolation differential operational amplifier circuit, the input end of the second follower circuit is connected with the output end of the fourth filter circuit, the input end of the second resistance voltage-dividing circuit is connected with the output end of the second follower circuit, the input end of the fifth filter circuit is connected with the output end of the second resistance voltage-dividing circuit, and the input end of the third amplitude limiting circuit is connected with the output end of the fifth filter circuit;

and the output end of the third amplitude limiting circuit is also connected with the input end of the microprocessor control module.

Preferably, the microprocessor control module includes a DSP chip circuit, a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit, and an overvoltage sampling protection circuit, wherein:

the DSP chip circuit is respectively connected with the chip power supply circuit, the reset circuit, the JTAG downloader circuit, the external ADC reference voltage circuit, the key circuit, the display screen circuit and the overvoltage sampling protection circuit, the DSP chip circuit is used as the core of the microprocessor control module to work in cooperation with other circuits, and the output end of the DSP chip circuit is also connected with the PWM generation module.

Preferably, the PWM generation module is connected in sequence to a PWM enable circuit, a buffer circuit and a pull-up circuit, wherein:

the input end of the PWM enabling circuit is connected with the output end of the microprocessor control module, the input end of the buffer circuit is connected with the output end of the PWM enabling circuit, the other input end of the buffer circuit is connected with the DSP chip circuit, the input end of the pull-up circuit is connected with the output end of the buffer circuit, and the output end of the pull-up circuit is connected with the first isolation driving module and the second isolation driving module respectively.

Preferably, the first isolation driving module and the second isolation driving module have the same structure, and the inside of the first isolation driving module and the second isolation driving module includes an isolation driving chip circuit, a bootstrap circuit and a MOS transistor driving circuit, wherein:

the input end of the isolation driving chip circuit is respectively connected with the output end of the PWM generation module, the 5V direct-current power supply and the 12V direct-current power supply, the input end of the bootstrap circuit is connected with the 12V direct-current power supply, the output end of the bootstrap circuit is connected with the output end of the isolation driving chip circuit, the input end of the MOS tube driving circuit is connected with the output end of the isolation driving chip circuit, the output end of the MOS tube driving circuit is respectively connected with the totem pole bridgeless PFC circuit module, the first isolation driving module is connected with the grid electrodes of MOS tubes Q1 and Q2 in the totem pole bridgeless PFC circuit module, and the second isolation driving module is connected with the grid electrodes of MOS tubes Q3 and Q4 in the totem pole bridgeless PFC circuit module.

Preferably, the auxiliary power supply consists of a plurality of linear power supply chip circuits, and provides a 3.3V dc power supply, a 5V dc power supply and a 12V dc power supply respectively.

The utility model provides a totem pole does not have bridge PFC converter system compares with traditional no bridge PFC converter, and the sampling circuit that the invention has reduced input current when reducing entire system complexity has still reduced the circuit cost, owing to do not use current sampling circuit, has not only reduced the volume of converter, has still improved the conversion efficiency of system to a certain extent, has still avoided the noise that current sampling circuit caused to introduce in addition, has improved the stability of system.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

Fig. 1 is a block diagram of a bridgeless PFC converter system without current sampling according to the present invention;

fig. 2 is a block diagram of the input voltage sampling module of the present invention;

fig. 3 is a block diagram of the input zero-crossing detection module of the present invention;

fig. 4 is a block diagram of the output voltage sampling module of the present invention;

fig. 5 is a block diagram of the microprocessor control circuit module and the PWM generation circuit module of the present invention;

fig. 6 is a block diagram of the isolation driving circuit of the present invention;

fig. 7 is a totem pole bridgeless PFC circuit topology of the present invention;

fig. 8 is a first stage of the operation of the totem-pole bridgeless PFC circuit of the present invention;

fig. 9 is a second stage of the operation of the totem-pole bridgeless PFC circuit of the present invention;

fig. 10 is a third stage of the operation of the totem-pole bridgeless PFC circuit of the present invention;

fig. 11 is a fourth stage of the operation of the totem-pole bridgeless PFC circuit of the present invention;

fig. 12 is a control flow chart of the bridgeless PFC converter system without current sampling according to the present invention;

fig. 13 is a flow chart of the adaptive correction of the average inductance compensation voltage in the nth to n +1 power frequency cycles of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as up, down, left, right, front, back \8230;) in the embodiments of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

The utility model discloses a figure 1 is no bridge PFC converter system block diagram of current sampling, and this system block diagram comprises a main circuit module and a plurality of submodule pieces jointly, and its main circuit module is totem pole no bridge PFC circuit module, and the submodule piece includes auxiliary power supply, microprocessor control module, PWM generation module, isolation drive circuit, input voltage sampling module, input zero cross detection module and output voltage sampling module;

the totem-pole bridgeless PFC circuit module is connected with the output ends of the first and second isolation driving modules, the input end of the input voltage sampling module is connected with the totem-pole bridgeless PFC circuit module, the input end of the output voltage sampling module is connected with the totem-pole bridgeless PFC circuit module, the input end of the input zero-crossing detection module is connected with the output end of the input voltage sampling module, the microprocessor control module is connected with the output ends of the input voltage sampling module, the input zero-crossing detection module and the output voltage sampling module, the PWM generation module is connected with the output end of the microprocessor control module, the first isolation driving module is connected with the output end of the PWM generation module, and the second isolation driving module is connected with the output end of the PWM generation module.

the source electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of the high-frequency power MOS tube Q2 and one end of the boost inductor L, the drain electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of the rectification power MOS tube Q3, the anode of the output filter capacitor C and one end of the load resistor R, the source electrode of the high-frequency power MOS tube Q2 is respectively connected with the source electrode of the rectification power MOS tube Q4, the cathode of the output filter capacitor C and the other end of the load resistor R, and the source electrode of the rectification power MOS tube Q3 is respectively connected with the drain electrode of the rectification power MOS tube Q2, the cathode of the output filter capacitor C and the other end of the load resistor RInput AC power v _in One end of the boost inductor L is connected with a drain electrode of a rectification power MOS tube Q4, a source electrode of the rectification power MOS tube Q4 is respectively connected with a source electrode of a high-frequency power MOS tube Q2, a negative electrode of an output filter capacitor C and the other end of a load resistor R, and the other end of the boost inductor L is connected with an input alternating current power supply v _in The other end of the first and second connecting rods is connected;

the input end of the first isolation differential operational amplifier circuit and an input alternating current power supply v _in The input end of the first filter circuit is connected with the output end of the first isolation differential operational amplifier circuit, the input end of the first follower circuit is connected with the output end of the first filter circuit, the input end of the second filter circuit is connected with the output end of the first follower circuit, and the input end of the first amplitude limiting circuit is connected with the output end of the second filter circuit;

the output end of the first amplitude limiting circuit is further connected with the input end of the microprocessor control module.

Preferably, the first isolation driving module and the second isolation driving module have the same structure, and the module includes an isolation driving chip circuit, a bootstrap circuit, and an MOS transistor driving circuit, wherein:

the input end of the isolation driving chip circuit is connected with the output end of the PWM generation module, the 5V direct-current power supply and the 12V direct-current power supply respectively, the input end of the bootstrap circuit is connected with the 12V direct-current power supply, the output end of the bootstrap circuit is connected with the output end of the isolation driving chip circuit, the input end of the MOS tube driving circuit is connected with the output end of the isolation driving chip circuit, and the output end of the MOS tube driving circuit is connected with the totem pole bridgeless PFC circuit module respectively. The first isolation driving module is connected with the grids of MOS (metal oxide semiconductor) tubes Q1 and Q2 in the totem-pole bridgeless PFC circuit module, and the second isolation driving module is connected with the grids of MOS tubes Q3 and Q4 in the totem-pole bridgeless PFC circuit module.

The utility model discloses on the basis of formula module relation of connection, continue to disclose the theory of operation of corresponding module.

FIG. 2 is a block diagram of input voltage sampling, V _in+ And V _in- The input AC voltage source in FIG. 8 is connected to the upper end and the lower end respectively, and is converted into a voltage of 0-3.3V by the first isolation differential operational amplifier circuit, and a DC voltage bias of 1.5V is added to the first isolation differential operational amplifier circuit, so as to realize undistorted sampling of the negative input voltage. Then the converted 0-3.3V voltage is sent to a first filter circuit for filtering, and then is sent to a first follower circuit to reduce the output impedance. Finally, the input sampling voltage V is obtained after the input sampling voltage V is sent to a second filter circuit and a first amplitude limiting circuit _{in_adc} 。

FIG. 3 is a block diagram of the input zero crossing detection, positive input of the comparison circuitInput terminal and input sampling voltage V _{in_adc} The negative input end of the linear power supply chip is connected with the 1.5V output direct current voltage of the linear power supply chip, the comparison circuit outputs 0V and 5V level signals, and the 0V and 5V level signals are sent to the first resistance voltage division circuit, the third filter circuit and the second amplitude limiting circuit to obtain a zero crossing point detection voltage level signal V of the input voltage _priority 。

FIG. 4 is a block diagram of an output voltage sampling module, where V _o+ And V _o- The output voltage between the two points is the output voltage of a totem-pole bridgeless PFC circuit, the output voltage is sent to a second isolation differential operational amplifier circuit, the output voltage is converted into the voltage of 0-5V and sent to a fourth filter circuit for filtering, then the filtered voltage is sent to a second following circuit and a second resistance voltage division circuit to obtain the sampling voltage of 0-3.3V, and finally the sampling voltage is sent to a fifth filter circuit and a third amplitude limiting circuit to obtain the output sampling voltage V _{o_adc} 。

The left part of figure 5 is a module diagram of a microprocessor control circuit, a DSP chip circuit is taken as a center, and sub-circuits with respective functions are arranged on the periphery, wherein a chip power supply circuit provides a power supply for a DSP chip, a reset circuit is a circuit capable of manually resetting a DSP program outside, a JTAG downloader circuit is a program downloading communication circuit between a computer and the DSP chip, an external ADC reference voltage circuit provides an accurate 3V reference power supply for an ADC sampling module in the DSP, a key circuit and a display screen circuit are external functional circuits of the DSP to realize key interruption triggering and necessary information display, and overvoltage sampling protection provides safe input voltage for an ADC pin of the DSP to protect the safe operation of the DSP.

The right part of fig. 5 is a block diagram of the PWM generating circuit, and the input terminals of the PWM enabling circuit are respectively connected to two output IO pins of the DSP chip, so that the DSP can control the output level of the PWM enabling circuit through a program, and the output level signals are respectively connected to the enable pins of the buffer chip in the buffer circuit, so as to control the output pins of the buffer chip to generate the output PWM signals. In addition, the input of the buffer chip is connected with four PWM output IO pins of the DSP chip, whether four paths of PWM signals are output or not is controlled by the buffer chip, and meanwhile, the four paths of PWM output signals of the buffer chip are output by level signals of 0V and 5V after passing through a pull-up circuit, so that the PWM level requirement of the isolation driving chip is met.

Fig. 6 is a block diagram of an isolation driving circuit, in which U7 is a half-bridge isolation driving chip, pins VIA and VIB of the chip are respectively connected to R28 and R29 to form a forced low-level pull-down circuit, and are also respectively connected to a PWM generating circuit module, and output signals PWMxA and PWMxB of the PWM generating circuit module are determined by a DSP, where x is 1 or 2, fig. 7 is a first isolation driving circuit and is connected to a power switching tube of a high-frequency bridge arm when x is 1, and fig. 7 is a second isolation driving circuit and is connected to a power switching tube of a low-frequency bridge arm when x is 2.

In fig. 6, a 12V dc power supply is connected to the VDDA pin of the chip after passing through the bootstrap circuit to provide a driving power supply for the upper tubes Q1 and Q3 in the high-frequency and low-frequency bridge arms, and at the same time, the 12V power supply is directly used to provide a driving power supply for the lower tubes Q2 and Q4 in the high-frequency and low-frequency bridge arms. VOA and VOB are driving signals and are connected with a driving circuit, GNDxA and GNDxB are respectively connected with GNDA and GNDB of the chip, and GxA and GxB are respectively connected with an upper tube grid control end and a lower tube grid control end of the bridge arm so as to drive the switching tube to be switched on and switched off.

The utility model discloses on the theory of operation basis of above circuit module diagram, continue to disclose the control method among the microprocessor control module and explain.

Fig. 7 is the utility model discloses a totem-pole bridgeless PFC circuit topology, it includes: high-frequency power MOS tubes Q1 and Q2, low-frequency rectification power MOS tubes Q3 and Q4, diodes D1, D2, D3 and D4 connected in parallel in the body of Q1, Q2, Q3 and Q4, a power boosting inductor L, an output filter capacitor C and an input alternating voltage source v _in And an output load resistor R, considering parasitic parameters possibly existing in the actual circuit, and an inductance internal resistance R _L And the conduction internal resistance r of the MOS tube _ds (ii) a Q1 and Q2 form a high-frequency bridge arm, Q3 and Q4 form a low-frequency rectifying bridge arm, an input alternating-current voltage source is connected with a boost inductor in series and is connected with the middle point of the two bridge arms to form a closed loop of an input part; the two bridge arms are connected with the filter capacitor C and the output load resistor R in parallel to form a closed loop of an output part; two-part closed loopThe same component is composed of two groups of bridge arms, namely an alternating current-direct current conversion part.

Preferably, referring to fig. 8-11, when the input ac voltage is in the positive half cycle, Q2 and Q4 are turned on, Q1 and Q3 are turned off, the current flows through the boost inductor L from left to right, the voltage on the inductor is positive left to right negative, and the process stores energy in the boost inductor L; the current flows from the anode of the capacitor C to the load resistor R and finally returns to the cathode of the capacitor C, the capacitor provides energy for the load in the process, and the output voltage is kept constant;

the input alternating voltage is still in the positive half cycle, Q1 and Q4 are switched on, Q2 and Q3 are switched off, current flows through a boosting inductor L from left to right, the voltage on the inductor is left negative and right positive, and the boosting inductor L releases energy in the process; part of follow current flows into an output filter capacitor C to charge and store energy for the capacitor C; the other part of current flows into an output load resistor R to provide energy for a load and maintain the constant of output voltage;

when the input alternating voltage is in the negative half cycle, Q1 and Q3 are conducted, Q2 and Q4 are turned off, current flows through a boosting inductor L from right to left, the voltage on the inductor is left negative and right positive, and the boosting inductor L is subjected to energy storage in the process; the current flows from the anode of the capacitor C to the load resistor R and finally returns to the cathode of the capacitor C, the capacitor provides energy for the load in the process, and the output voltage is kept constant;

the input alternating voltage is still in the negative half cycle, Q2 and Q3 are conducted, Q1 and Q4 are turned off, current flows through the boosting inductor L from right to left, the voltage on the inductor is left positive and right negative, and the boosting inductor L releases energy in the process; meanwhile, part of follow current flows into an output filter capacitor C to charge and store energy for the capacitor C; the other part of the current flows into an output load resistor R to provide energy for the load and maintain the constant output voltage.

The utility model discloses a control of no bridge PFC converter system, refer to fig. 12-13, include:

step 100, establishing a mathematical model of average inductive voltage in a totem-pole bridgeless PFC circuit by using a time averaging method;

step 200, sending the sampled output voltage into a DSP (digital signal processor) to calculate actual output voltage, inputting the difference value of the output voltage and reference voltage into a PID (proportion integration differentiation) controller, wherein the output of the PID controller is average inductance peak voltage;

step 300, setting a compensation term to compensate the average inductance voltage, wherein the compensation term is the average inductance compensation voltage, so that the calculated average inductance voltage at any time is the same as the average inductance voltage when the actual circuit operates;

step 400, the compensation item carries out self-adaptive correction control; whether the ripple phase angle of the output voltage is zero or not is judged by comparing the average inductance compensation peak voltage with the average inductance reference compensation peak voltage, if not, the average inductance reference compensation peak voltage is taken as the average inductance compensation peak voltage of the next power frequency period, after a limited power frequency period, the average inductance compensation peak voltage is equal to the average inductance reference compensation peak voltage, namely, the ripple phase angle of the output voltage tends to zero in a limited time, so that the power factor of the totem-pole bridgeless PFC circuit tends to 1, and the self-adaptive correction of the average inductance compensation peak voltage is realized.

And 500, calculating the duty ratio in each switching period according to the average inductance peak voltage calculation result and the average inductance compensation peak voltage calculation result, and outputting a corresponding control signal to control the circuit through a PWM (pulse-width modulation) driving module.

The utility model provides a totem pole does not have bridge PFC converter system uses totem pole does not have bridge PFC circuit topological structure, is considering parasitic parameter, like under the condition of inductance internal resistance, switch tube internal resistance, carries out the mathematical model of circuit topology and models, utilizes the time averaging method to calculate inductive voltage's expression down to increase reasonable compensating voltage on this expression and remove the inductive voltage who compensates the calculation and the deviation between inductive voltage in the actual circuit, further improve power factor. And calculating corresponding compensation reference voltage according to the phase information of the output voltage ripple, so that the compensation voltage approaches the compensation reference voltage until the compensation voltage is stabilized at the compensation reference voltage in a steady state, thereby realizing the correction of the power factor and reducing the influence of parasitic parameters on the power factor. The method has the following advantages: (1) The sampling circuit of the input current is reduced, and the complexity of the whole system is reduced. (2) Because a current sampling circuit is not used, the size of the converter is reduced, and the conversion efficiency of the system is improved to a certain extent. (3) The noise introduction caused by the current sampling circuit is avoided, and the stability of the system is improved. (4) And a high-precision ADC sampling chip is not used for sampling the input voltage and the output voltage, so that the circuit cost is saved.

Preferably, step 100, establishing a mathematical model of an average inductor voltage in the totem-pole bridgeless PFC circuit by using a time averaging method, includes: four working stages of totem-pole bridgeless PFC circuit topology, t represents the t-th time in a power frequency period, and the inductive voltages v of the four stages are listed _L (t)：

The first stage is as follows: v. of _L (t)＝v _in (t)-i _L (t)×(r _L +r _ds )；

And a second stage: v. of _L (t)＝v _in (t)-i _L (t)×(r _L +r _ds )-v _o (t)；

And a third stage: v. of _L (t)＝v _in (t)-i _L (t)×(r _L +r _ds )；

A fourth stage: v. of _L (t)＝v _in (t)-i _L (t)×(r _L +r _ds )+v _o (t)；

In the formula i _L (t) represents the DC component of the output voltage as V _dc The corresponding inductor current is also the input current.

By x _Ts Represents the average value of variable x in a switching period, and sets the conduction time in a switching period as T _on With a switching period of T _s Then, the average values of the input ac voltage and the input ac current for one switching period are respectively expressed as:

combining four stages of inductor voltage v _L (t), obtaining an average inductor voltage of one switching period as:

v _L (t) _Ts ＝v _in (t) _Ts -i _L (t) _Ts (r _L +r _ds )-sign(v _in (t))(1-d(t))v _o (t)(1)

wherein the duty cycle d (t) is the ratio of the on-time to the switching period, sign (v) _in ) To relate to v _in The sign function of (c):

preferably, step 200 sends the sampled output voltage to the DSP to calculate the actual output voltage, the difference between the output voltage and the reference voltage is input to the PID controller, and the output of the PID controller is the average inductance peak voltage; the method comprises the following steps: the method comprises the steps that an isolation differential sampling circuit is used for sampling input and output voltages, sampling signals are converted into voltage signals of 0-3.3V through a resistance voltage division circuit, and the voltage signals are transmitted into a DSP chip; then the DSP chip calculates the actual output voltage v after the feedback output voltage is converted by the ADC _o With a set reference output voltage V _ref And the output voltage v _o Subtracting to obtain an error value v of the output voltage _err Then v is further determined _err Inputting the average peak voltage V of the inductor into a PID controller for operation, and obtaining an output result as the average peak voltage V of the inductor _m (ii) a After the output voltage is stabilized, the direct current voltage V is output _dc Is equal to the reference output voltage V _ref 。

Let the power frequency period be T _g When the input alternating voltage and the input alternating current are both sine waves and have the same phase, the average value of the inductive current in one switching period is calculated as follows:

wherein

Representing a sineAverage current peak of the input current. The impedance of the inductor is set to be omega L, and the peak value V of the average inductor voltage is obtained according to ohm's law _m And substituting the formula (2) to obtain:

according to the inductance voltage formula

Calculating the average inductance voltage:

let V _in For input of a peak value of the AC voltage, I _o To output the load current, when the circuit conversion efficiency is 100%, there is input power equal to output power: and (4) combining the formula (3) to derive an expression of the output voltage direct current quantity:

as can be seen from equation (5), when the input AC voltage increases or the load current decreases, the voltage can be decreased

Maintaining the output voltage V _dc The change is not changed; by increasing when the input AC voltage decreases or the load current increases>

Maintaining the output voltage V _dc And is not changed.

And deducing and designing a corresponding PID voltage controller according to the formula: the input and output voltages are sampled by using an isolated differential sampling circuit, and a sampling signal is converted into a voltage signal of 0 to 3.3V through a resistance voltage division circuitAnd transmitted to the DSP chip. Then the DSP chip calculates the actual output voltage v after the feedback output voltage is converted by the ADC _o With a set reference output voltage V _ref And the output voltage v _o Subtracting to obtain an error value v of the output voltage _err Then v is added _err Inputting PID program for operation, and taking the obtained output result as average peak voltage of inductor

After the output voltage is stabilized, the direct current voltage V is output _dc Is equal to the reference output voltage V _ref 。

Preferably, the step 300 of setting a compensation term to compensate the average inductor voltage, where the compensation term is the average inductor compensation voltage, so that the average inductor voltage calculated at any time is the same as the average inductor voltage when the actual circuit operates, includes: in order to make the input current sinusoidal, i.e. the power factor is 1, the phase angle is required

Is zero and the derived equation is:

at the time t of peak input voltage _a At an instantaneous value of the output voltage of V _dc At this time, the corresponding duty ratio is d _a And substituting the average compensation peak voltage into the formula (6) to obtain a reference value of the average compensation peak voltage of the inductor:

in the above formula

Is the average inductance compensation voltage reference value of the next power frequency period according to->

Can be calculated in the next workingFrequency period pair->

A corresponding correction is made.

In particular, the conversion efficiency of the circuit is difficult to reach 100% because various losses always exist in the circuit, and the losses are mainly caused by various parasitic parameters. Without reducing the output power, the input power needs to be increased to compensate for the power lost in the circuit. Therefore, in equation (1), the calculated average inductor voltage may deviate from the average inductor voltage of the actual circuit.

In order to improve the power factor, the input ac current is made to present a standard sine wave, and the average inductor voltage in each switching period needs to be compensated, so that the calculated average inductor voltage is the same as the actual average inductor voltage.

Average inductance voltage with compensation<Δv _L (t)> _Ts Comprises the following steps:

<Δv _L (t)> _Ts ＝(r _L +r _ds )<Δi _L (t)> _Ts (9)

in the formula<Δi _L (t)> _Ts To compensate the current for the corresponding average inductance, let

To compensate for the average inductor voltage peak, then<Δi _L (t)> _Ts Can be expressed as:

adding equation (10) to equation (1), a new average inductor voltage expression can be obtained:

<v _L (t)> _Ts ＝<v _in (t)> _Ts -(<i _L (t)> _Ts +<Δi _L (t)> _Ts )(r _L +r _ds )-(1-d(t))v _o (t) (11)

the above formula is modified to obtain the actual duty ratio d _real (t) is:

the sum of the inductance internal resistance and the MOS tube internal resistance is r _par The above formula includes one term of the internal resistance, i.e. the sum of the average voltage of the internal resistance of the inductor and the internal resistance of the MOS transistor in the actual circuit<v _par (t)> _Ts Can be expressed as:

analyzing the formula (1) and the formula (11), when adding a proper average inductance compensation voltage<Δv _L (t)> _Ts In the process, the calculated average inductance voltage is equal to the actual average inductance voltage, so that the input alternating current presents a standard sine wave.

However, since the input current is not sampled in an actual circuit, information on the input current is unknown, and it is not possible to directly determine whether or not the input ac current is a standard sine wave. To solve this problem, it is possible to find information about the input alternating current from the low-frequency ripple phase of the output voltage and determine whether the input current is a standard sine wave, thereby indirectly controlling the input alternating current.

A low frequency ripple of the output voltage is derived. Determining the low-frequency ripple voltage v of the output _ripple (t) is:

from the above formula, when the power factor is equal to 1, the phase angle of the low-frequency ripple of the output voltage is zero, and when there is component loss in the circuit, the power factor is less than 1, and the low-frequency ripple of the output voltage generates a phase angle

Thus the actual output voltage v _o (t) is:

comparing the equations (14) and (15), it can be seen that in order to make the input current sinusoidal, i.e., to make the power factor 1, the phase angle needs to be set

Is zero, and therefore the formulae (15) and +>

Substituting equation (11), we simplify to find the following equation:

at the time t of peak input voltage _a At an instantaneous value of the output voltage of V _dc At this time, the corresponding duty ratio is d _a The reference value for obtaining the average compensation peak voltage of the inductance by substituting the average compensation peak voltage into the formula (12) is formula (8):

in the formula (8)

The calculation result of (4) can be paired in the next power frequency period>

A corresponding correction is made.

Preferably, the step 400 of adaptively correcting the control by the compensation term includes: setting the circuit in the nth power frequency period to sample the input voltage v _in (t) and output voltage v _o (t) calculating the duty ratio of each switching period only by substituting formula, controlling the circuit, and controlling the time t in the nth power frequency period until the last switching period is finished _a [n]Corresponding duty cycle d _a [n]Formula (8) is replaced to calculate average compensation reference peak voltage of inductance

Then, judge

And/or>

Whether or not equal, and if equal, no correction is required>

If not equal, based on>

And/or>

Calculating a correction quantity alpha of the nth power frequency period, and enabling the device to be in or out of the nth +1 power frequency period>

After the correction of a limited number of power frequency periods, the signal is enabled to be greater or less>

Gradually approaches->

Finally the circuit enters a steady state and satisfies->

In particular, according to the above

And &>

Is derived and->

The relationship with the power factor can be concluded as follows: when the average inductance compensates for the peak voltage->

Equals the average inductance reference compensation peak voltage->

When the power factor is equal to 1, the input alternating current is a standard sine wave.

Preferably, step 500 comprises: the method for calculating the duty ratio under each switching period according to the calculation result of the average inductance peak voltage and the calculation result of the average inductance compensation peak voltage and outputting the corresponding control signal to control the circuit through the PWM driving module comprises the following steps: duty ratio expression (12).

Since the above-described duty ratio applies to both positive and negative half cycles of the input ac voltage, the DSP can calculate the duty ratio for each switching cycle by directly using equation (12), where L and r are expressed _L And r _ds Are unknown, but as can be seen from the above analysis, only adjustment is required

The power factor can be corrected by making the compensated average inductance voltage equal to the average inductance voltage of the actual circuit, so that the influence of element parameters and parasitic parameters on the power factor is avoided.

Preferably, in the DSP program, L and r can be selected _L And r _ds Setting a reasonable initial value, such as L =1mH, r _L =0.1 Ω and r _ds =1 Ω, and then the output of the module is controlled by the output voltage

And the output of the input current correction module

The driving chip is used for outputting a driving signal to control the switching tubes Q1 and Q2. Meanwhile, the driving signals are respectively given to the switching tubes Q3 and Q4 through the input voltage zero-crossing detection level signals, namely when the input alternating voltage is in positive half cycle,q4 is conducted, Q3 is turned off, and when the input alternating voltage is in a negative half cycle, Q3 is conducted, and Q4 is turned off.

The above description is only exemplary of the invention, and is intended to enable those skilled in the art to understand and implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bridgeless PFC converter system without current sampling is characterized by comprising a main circuit module and a plurality of sub-modules, wherein the main circuit module is a totem-pole bridgeless PFC circuit module, and the sub-modules comprise an auxiliary power supply, a microprocessor control module, a PWM (pulse width modulation) generation module, an isolation driving circuit, an input voltage sampling module, an input zero-crossing detection module and an output voltage sampling module;

2. The bridgeless PFC converter system without current sampling of claim 1, wherein the totem-pole bridgeless PFC circuit module comprises an input AC power source v _in High-frequency power MOS pipe Q1, high-frequency power MOS pipe Q2, rectification power MOS pipe Q3, rectification power MOS pipe Q4, boost inductance L, output filter capacitor C and load resistance R, wherein:

the source electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of the high-frequency power MOS tube Q2 and one end of a boosting inductor L, the drain electrode of the high-frequency power MOS tube Q1 is respectively connected with the drain electrode of a rectification power MOS tube Q3, the anode of an output filter capacitor C and one end of a load resistor R, the source electrode of the high-frequency power MOS tube Q2 is respectively connected with the source electrode of a rectification power MOS tube Q4, the cathode of the output filter capacitor C and the other end of the load resistor R, and the source electrode of the rectification power MOS tube Q3 is respectively connected with an input alternating current power supply v _in The source electrode of the rectification power MOS tube Q4 is respectively connected with the source electrode of the high-frequency power MOS tube Q2, the cathode of the output filter capacitor C and the other end of the load resistor R, and the other end of the boosting inductor L is connected with the input alternating current power supply v _in The other end of the first and second connecting rods is connected;

3. The bridgeless PFC converter system without current sampling according to claim 1, wherein a first isolated differential operational amplifier circuit, a first filter circuit, a first follower circuit, a second filter circuit and a first limiter circuit are connected in sequence in the input voltage sampling module, wherein:

4. The bridgeless PFC converter system without current sampling according to claim 1, wherein the input zero-crossing detection module comprises a linear module circuit, a comparison circuit, a first resistance voltage division circuit, a third filter circuit and a second amplitude limiting circuit in sequence, wherein:

5. The bridgeless PFC converter system without current sampling according to claim 1, wherein a second isolated differential operational amplifier circuit, a fourth filter circuit, a second follower circuit, a second resistance voltage divider circuit, a fifth filter circuit and a third amplitude limiting circuit are connected in sequence in the output voltage sampling module, wherein:

6. The bridgeless PFC converter system without current sampling of claim 1, wherein the microprocessor control module comprises a DSP chip circuit, a chip power supply circuit, a reset circuit, a JTAG downloader circuit, an external ADC reference voltage circuit, a key circuit, a display screen circuit, and an over-voltage sampling protection circuit, wherein:

7. The bridgeless PFC converter system without current sampling according to claim 1, wherein the PWM generation module is connected with a PWM enabling circuit, a buffer circuit and a pull-up circuit in sequence, wherein:

8. The bridgeless PFC converter system without current sampling according to claim 1, wherein the first isolation driving module and the second isolation driving module have the same structure, and the inside of the first isolation driving module and the second isolation driving module comprises an isolation driving chip circuit, a bootstrap circuit and a MOS tube driving circuit, wherein:

9. The bridgeless PFC converter system without current sampling according to claim 1, wherein the auxiliary power supply is composed of a plurality of linear power chip circuits, and provides a 3.3V DC power supply, a 5V DC power supply and a 12V DC power supply respectively.