CN211151921U

CN211151921U - Low-phase-noise frequency division time service module

Info

Publication number: CN211151921U
Application number: CN201921558653.6U
Authority: CN
Inventors: 吴炜
Original assignee: Shenzhen Zhongqiang Electronic Co ltd
Current assignee: Shenzhen Zhongqiang Electronic Co ltd
Priority date: 2019-09-19
Filing date: 2019-09-19
Publication date: 2020-07-31
Anticipated expiration: 2029-09-19

Abstract

The utility model discloses a low-phase noise frequency division time service module, which comprises a local oscillator, a DAC, an MCU, a phase discriminator, a first frequency divider and a second frequency divider; the first frequency divider is divided into a frequency division 1-1, a frequency division 1-2, a frequency division 1-3, a frequency division 1-4 and a frequency division 1-5; the second frequency divider is divided into a frequency division 2-1, a frequency division 2-2 and a frequency division 2-3; the MCU is connected with the frequency divider 1 and the frequency divider 2 through the SPI bus; the MUC is connected with the DAC and the phase discriminator, and the DAC is connected with the local oscillator; the local oscillator is connected with the first frequency divider. The utility model relates to a compactness, function are nimble, and the interface is abundant. Besides being used as a universal time service module, the PTM100 also supports the selection of multiple high-frequency local oscillators, such as 50MHz/100MHz/200MHz and the like, and two-stage frequency division is built in, so that multiple different frequency division outputs are realized, and the requirement of outputting various frequencies by time system equipment at the same time is met.

Description

Low-phase-noise frequency division time service module

Technical Field

The utility model relates to a communication base station field, concretely relates to low phase noise frequency division time service module.

Background

At present, the common time service module scheme can only use crystal oscillators with fundamental frequency (such as 10MHz) or high frequency (such as 100MHz) for disciplinary calibration, and two crystal oscillators with frequencies different greatly cannot be compatible for use in the same scheme.

At present, the output frequency point of the time service module is very limited, and for some special frequencies, or lower frequencies (such as 100KHz), the output cannot be output, or the output is output through a DDS scheme and the like, the phase noise is very poor, and the DDS scheme is completely unrelated to the used crystal oscillator.

Disclosure of Invention

The utility model aims to solve the technical problem that a can solve the low phase noise frequency division time service module of above-mentioned problem.

The utility model discloses a realize through following technical scheme: a low-phase noise frequency division time service module comprises a local oscillator, a DAC, an MCU, a phase discriminator, a first frequency divider and a second frequency divider; the first frequency divider is divided into a frequency division 1-1, a frequency division 1-2, a frequency division 1-3, a frequency division 1-4 and a frequency division 1-5; the second frequency divider is divided into a frequency division 2-1, a frequency division 2-2 and a frequency division 2-3; the MCU is connected with the frequency divider 1 and the frequency divider 2 through the SPI bus; the MUC is connected with the DAC and the phase discriminator, and the DAC is connected with the local oscillator; the local oscillator is connected with the first frequency divider.

As a preferred technical scheme, the frequency division 1-1 is a frequency not higher than 25 MHz; the frequency division 1-2, the frequency division 1-3, the frequency division 1-4 and the frequency division 1-5 are one-fourth of the local oscillator 1-192; the frequency division 2-1, the frequency division 2-2 and the frequency division 2-3 are 1-192 times of the frequency division 1_ 2.

As a preferred technical scheme, the frequency division multiples of the first frequency divider and the second frequency divider are preset by the MCU, and each channel can be set with different output frequencies.

The utility model has the advantages that: the utility model relates to a compactness, function are nimble, and the interface is abundant. Besides being used as a universal time service module, the PTM100 also supports the selection of multiple high-frequency local oscillators, such as 50MHz/100MHz/200MHz and the like, and two-stage frequency division is built in, so that multiple different frequency division outputs are realized, and the requirement of outputting various frequencies by time system equipment at the same time is met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a system diagram of the present invention.

Detailed Description

All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.

Any feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.

In the description of the present invention, it is to be understood that the terms "one end", "the other end", "the outside", "upper", "inside", "horizontal", "coaxial", "central", "end", "length", "outer end", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Furthermore, in the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

The use of terms herein such as "upper," "above," "lower," "below," and the like in describing relative spatial positions is for the purpose of facilitating description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative positional terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the present invention, unless otherwise explicitly specified or limited, the terms "set", "coupled", "connected", "penetrating", "plugging", and the like are to be understood in a broad sense, and may be, for example, fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

As shown in fig. 1, the digital signal processing circuit comprises a local oscillator, a DAC, an MCU, a phase discriminator, a first frequency divider, and a second frequency divider; the first frequency divider is divided into a frequency division 1-1, a frequency division 1-2, a frequency division 1-3, a frequency division 1-4 and a frequency division 1-5; the second frequency divider is divided into a frequency division 2-1, a frequency division 2-2 and a frequency division 2-3; the MCU is connected with the frequency divider 1 and the frequency divider 2 through an SPI bus (used for configuring parameters of a frequency dividing chip and reading the state of the frequency dividing chip); the MUC is connected with the DAC and the phase discriminator, and the DAC is connected with the local oscillator; the local oscillator is connected with the first frequency divider.

The frequency division 1-1 is a frequency not higher than 25MHz (because the input frequency of the MCU has limitation, the local oscillator with the frequency higher than 25MHz can be adopted by adopting the design); the frequency division 1-2, the frequency division 1-3, the frequency division 1-4 and the frequency division 1-5 are one-fourth of the local oscillator 1-192; the frequency division 2-1, the frequency division 2-2 and the frequency division 2-3 are 1-192 times of the frequency division 1_ 2.

The frequency division multiples of the first frequency divider and the second frequency divider are preconfigured by the MCU, and each channel can be set with different output frequencies.

The working principle is as follows: 1. firstly, selecting a suitable local oscillator which can carry out frequency division to generate the frequency according to a frequency point needing to be output; the MCU can only access clock reference input (frequency division 1-1) of <25MHz, so the design is compatible with most applications, and the local oscillator output is divided and then input to the MCU.

2. After the MCU starts working, the PPS (pulse per second) clock output by frequency division of the MCU is originated from a local oscillator, and the phase difference calculated by the phase discriminator at the moment reflects the deviation between the local oscillator and the reference; and then the MCU sends the parameters to be adjusted to the DAC, and the DAC generates a corresponding voltage value to be loaded to the voltage control end of the local oscillator to realize the frequency adjustment of the local oscillator. The general external PPS is derived from an atomic clock and a Beidou navigation system, the precision is high, and the frequency accuracy of a local oscillator can be calibrated to-10 and-11 orders (7 and 8 orders) of magnitude.

3. The frequency division multiples of the first frequency divider and the second frequency divider are pre-configured by the MCU, and each channel can be set with different output frequencies. If the local oscillator is 100MHz, 10 frequency division can be carried out and then sent to the MCU and the second frequency divider; after 20 frequency division, 5MHz is output to 1-3 frequency division. Likewise, the divider 2 may continue on the basis of the first division, thereby dividing smaller frequency values, or frequencies that cannot be generated by other individual dividers, or may divide by only 1, with only a multiplexing function.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the creative work should be covered within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope defined by the claims.

Claims

1. The utility model provides a low phase noise frequency division time service module which characterized in that: the frequency divider comprises a local oscillator, a DAC, an MCU, a phase discriminator, a first frequency divider and a second frequency divider; the first frequency divider is divided into a frequency division 1-1, a frequency division 1-2, a frequency division 1-3, a frequency division 1-4 and a frequency division 1-5; the second frequency divider is divided into a frequency division 2-1, a frequency division 2-2 and a frequency division 2-3; the MCU is connected with the first frequency divider through an SPI bus, and the first frequency divider is connected with the second frequency divider; the MUC is connected with the DAC and the phase discriminator, and the local oscillator is connected with the first frequency divider.

2. The low-phase-noise frequency-division time service module of claim 1, characterized in that: the frequency division 1-1 is the frequency not higher than 25 MHz; the frequency division 1-2, the frequency division 1-3, the frequency division 1-4 and the frequency division 1-5 are one-fourth of the local oscillator 1-192; the frequency division 2-1, the frequency division 2-2 and the frequency division 2-3 are 1-192 times of the frequency division 1_ 2.

3. The low-phase-noise frequency-division time service module of claim 1, characterized in that: the frequency division multiples of the first frequency divider and the second frequency divider are pre-configured by the MCU, and each channel can be set with different output frequencies.