CN211125653U - L ED display panel and L ED display - Google Patents
L ED display panel and L ED display Download PDFInfo
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- CN211125653U CN211125653U CN202020400023.2U CN202020400023U CN211125653U CN 211125653 U CN211125653 U CN 211125653U CN 202020400023 U CN202020400023 U CN 202020400023U CN 211125653 U CN211125653 U CN 211125653U
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Abstract
The utility model provides an L ED display panel and L ED display, including the display backplate that is provided with L0 ED array, L1 ED array includes a plurality of L ED chips, L ED chip includes vertical emergent type luminescence chip and slope emergent type luminescence chip, L ED array's inside is provided with vertical emergent type luminescence chip, the direction of the principal ray that vertical emergent type luminescence chip sent is perpendicular to the direction that shows the backplate, L ED array's edge is provided with slope emergent type luminescence chip, the direction of the principal ray that slope emergent type luminescence chip sent is kept away from the geometric center's that shows the backplate direction, be provided with vertical emergent type luminescence chip in L ED array's inside, and be provided with slope emergent type luminescence chip at L ED array's edge, the principal ray of keeping away from the direction of showing the geometric center through slope emergent type luminescence chip sent, form spotlight effect between adjacent L ED display panel, thereby avoid producing the dark line between the adjacent L display panel, promote holistic display effect.
Description
Technical Field
The utility model relates to a light emitting diode preparation technical field and L ED display screen preparation technical field relate to a L ED display panel and L ED display, especially relate to a L ED display panel and L ED display that can eliminate dark line.
Background
L ED, namely the light emitting diode, through the electron and the hole recombination release energy luminescence, can high-efficiently convert the electric energy into the light energy, has small, the color is abundant, the energy consumption is low, long service life and so on multiple advantages, is considered as the next generation enters the new solid state light source of the general illumination field, based on L ED manufactured L ED display, has high stability, long service life and low operating temperature and so on many advantages, simultaneously also has born L ED low power consumption, color saturation, reaction rate is fast, contrast strong and so on the advantage, has very big application prospect.
Generally, a L ED display is formed by splicing a plurality of L ED display panels, and a L ED display panel includes a display area and a peripheral area, wherein the display area includes L ED chips arranged in an array, and the peripheral area includes some driving circuits and driving chips, etc. by the structure, the edge portion of the L ED display panel cannot be provided with L ED chips, but a certain blank area is left, and when two adjacent L ED display panels are spliced together, the blank area can cause dark stripes to be generated visually between the adjacent L ED display panels, which affects the overall display effect.
Accordingly, the prior art is yet to be improved and developed.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to prior art's above-mentioned defect, provide an L ED display panel and L ED display, can guarantee can not produce the dark line between the adjacent L ED display panel, promote holistic display effect.
The utility model provides a technical scheme that technical problem adopted as follows:
an L ED display panel, comprising a display backplane having disposed thereon a L ED array, the L ED array comprising L ED chips arranged side-by-side;
the L ED chip comprises a vertical emission type light-emitting chip and an inclined emission type light-emitting chip;
at least one vertical emergent light-emitting chip is arranged inside the L ED array, and the direction of a main ray emitted by the vertical emergent light-emitting chip is perpendicular to the direction of the display back plate;
the edge of the L ED array is provided with at least one inclined emission type light-emitting chip, and the main light emitted by the inclined emission type light-emitting chip faces away from the geometric center of the display back plate;
the display back plate comprises a substrate, a circuit layer and a planarization layer which are sequentially arranged; a plurality of first contact electrodes and second contact electrodes are arranged on the planarization layer;
the vertical emission type light-emitting chip and the inclined emission type light-emitting chip are both vertical L ED chips, and each of the vertical emission type light-emitting chip and the inclined emission type light-emitting chip comprises a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a second electrode which are sequentially stacked;
the vertical emission type light emitting chip and the oblique emission type light emitting chip are both disposed on the planarization layer, and a first electrode and a second electrode of the L ED chip are respectively soldered to the first contact electrode and the second contact electrode;
in the vertical emergent light-emitting chip, the side surface deviating from the display back plate is a straight plane, and the straight plane is parallel to the surface of the display back plate;
in the inclined emission type light emitting chip, a side surface deviating from the display back plate is an inclined plane, and the inclined plane is inclined to a side edge of the display back plate.
Compared with the prior art, the technical scheme has the advantages that the vertical emergent light-emitting chips are arranged inside the L ED array, the inclined emergent light-emitting chips are arranged at the edge of the L ED array, and the main light rays emitted by the inclined emergent light-emitting chips and facing away from the geometric center direction of the display backboard form a light condensation effect between the adjacent L ED display panels, so that dark stripes between the adjacent L ED display panels are avoided, and the overall display effect is improved.
Further, a groove is arranged on the planarization layer, the groove is arranged between the first contact electrode and the second contact electrode, the epitaxial part of the L ED chip is arranged in the groove, and a gap is formed between the L ED chip and the bottom of the groove.
The scheme has the advantages that the grooves are formed in the planarization layer, the L ED chips are arranged on the display back panel through the grooves, so that the structure of the L ED display panel is firmer, meanwhile, the L ED array is formed by arranging the L ED chips according to a set pattern, in addition, gaps are formed between the L ED chips and the bottoms of the grooves by properly deepening the grooves, and other devices on the L ED display panel are prevented from being damaged by pressure when the L ED chips are installed.
Further, the vertical emission type light emitting chip and the inclined emission type light emitting chip are L ED chips of the same size and model.
The scheme has the advantages that L ED chips with the same size and model are used as the vertical emission type light-emitting chip and the inclined emission type light-emitting chip, only one L ED chip needs to be arranged on one L ED display panel, and production cost is reduced.
Further, the display back plate is a rectangular plate-shaped structure, the L ED array is arranged on the display back plate, and the edges of the L ED array are located at the four sides of the display back plate;
the oblique emission type light emitting chip is arranged on at least one side edge of the display back plate.
The scheme has the advantages that the oblique-emission type light-emitting chips are selectively arranged on one or more side edges of the display back plate according to the position of the display back plate, so that the L ED display spliced by L ED display panels is better in display effect.
Further, the circuit layer comprises a buffer layer, a gate insulating layer and an interlayer insulating layer;
the buffer layer is disposed on the substrate, and the planarization layer is disposed on the interlayer insulating layer.
The beneficial effect who adopts above-mentioned scheme is: a flat surface can be provided above the substrate by the buffer layer, the gate and the active layer can be isolated by the gate insulating layer, and the source and the gate, the drain and the gate can be isolated by the interlayer insulating layer.
Furthermore, thin film transistors are arranged in the circuit layer and correspond to the L ED chips one by one;
the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected with the active layer, and the thin film transistor is connected with the L ED chip through the drain electrode;
the grid insulating layer is used for isolating the grid electrode on the thin film transistor from the active layer;
the interlayer insulating layer is used for isolating the source electrode and the grid electrode on the thin film transistor and isolating the drain electrode and the grid electrode on the thin film transistor.
The scheme has the advantages that the thin film transistors corresponding to the L ED chips one by one are arranged, so that the L ED chips can be driven one by one, high speed, high brightness and high contrast of the L ED display panel are facilitated, and the performance of the L ED display panel is improved.
The first contact electrode is connected with a drain electrode on the thin film transistor, the second contact electrode is connected with the power grounding wire, and the first contact electrode and the second contact electrode are also respectively connected with a first electrode and a second electrode of the L ED chip.
The L ED chip is respectively connected with the drain electrode on the thin film transistor and the power grounding wire arranged in the circuit layer through the first contact electrode and the second contact electrode on the planarization layer, so that the connection reliability can be ensured.
Further, in the vertical emission type light emitting chip, the first side surface is a straight plane, the second side surface is a straight plane or an inclined plane, and a principal ray of the vertical emission type light emitting chip is emitted from the first side surface;
in the oblique emission type light emitting chip, the first side surface is a straight plane, the second side surface is an oblique plane, and a principal ray of the oblique emission type light emitting chip is emitted from the second side surface.
The scheme has the advantages that in the inclined emission type light-emitting chip, the light rays are emitted through the inclined plane, the emitting direction of the principal light rays of the L ED chip is changed, and in the vertical emission type light-emitting chip, the second side surface can be set to be the inclined plane, so that the production cost is reduced.
An L ED display, wherein the L ED display is formed by splicing at least two L ED display panels;
in the L ED display panel, the chief rays emitted by the oblique-emission light-emitting chips on the L ED display panel of the first block and the chief rays emitted by the oblique-emission light-emitting chips on the L ED display panel of the second block are mutually staggered.
Compared with the prior art, the technical scheme has the advantages that in an L ED display panel, the L ED array is internally provided with vertical emergent light-emitting chips, the edge of the L ED array is provided with inclined emergent light-emitting chips, and principal rays which face the direction far away from the geometric center direction of a display backboard are emitted by the inclined emergent light-emitting chips, the L ED display panel adopting the structure is spliced to form a L ED display, so that a light condensation effect can be formed between adjacent L ED display panels, dark stripes between the adjacent L ED display panels are avoided, and the integral display effect is improved.
Drawings
Fig. 1 is a schematic front view of the L ED display panel assembly.
Fig. 2 is a front detail view of the L ED display panel assembly of the present invention.
Fig. 3 is a schematic side view of a L ED display panel according to a first embodiment of the present invention.
Fig. 4 is a schematic side view of a L ED display panel according to a second embodiment of the present invention.
Fig. 5 is a schematic side view of a L ED display panel according to a third embodiment of the present invention.
Fig. 6 is a schematic view of a first structure of an L ED display panel in which a L ED chip is engaged with a display back plate.
Fig. 7 is a schematic diagram of a first structure of an L ED display panel in which a L ED chip is mated with a thin film transistor.
Fig. 8 is a schematic diagram of a second structure of the L ED display panel in which a L ED chip is engaged with a display backplane.
Fig. 9 is a schematic diagram of a second structure of a L ED chip and a tft in an L ED display panel according to the present invention.
Fig. 10 is a schematic structural diagram of a L ED chip with a straight planar second side surface in an L ED display panel according to the present invention.
Fig. 11 is a schematic structural diagram of a L ED chip with a slanted plane second side surface in an L ED display panel according to the present invention.
Fig. 12 is an exploded schematic view of a L ED display panel with a vertical emission type light emitting chip having an inclined plane and a groove.
Fig. 13 is a schematic diagram of a combination of a vertical emission type light emitting chip with an inclined plane and a groove in an L ED display panel of the present invention.
Fig. 14 is an exploded view of an L ED display panel with a tilted-emission light-emitting chip and a groove.
Fig. 15 is a schematic diagram of the combination of the oblique-emission light-emitting chip and the groove in the L ED display panel of the present invention.
In the figures, the list of components represented by the various reference numbers is as follows:
a substrate 101, a circuit layer 102, a planarization layer 103, a buffer layer 104, a gate insulating layer 105, an interlayer insulating layer 106, a first contact electrode 107, and a second contact electrode 108;
a vertical emission type light emitting chip 301, an oblique emission type light emitting chip 302, a first electrode 303, a first semiconductor layer 304, a light emitting layer 305, a second semiconductor layer 306, a second electrode 307, a first side surface 308, and a second side surface 309;
an active layer 601, a gate electrode 602, a source electrode 603, and a drain electrode 604.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or assembly referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may for example be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. When an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The specific meaning of the above terms in the present invention can be understood in specific cases for those skilled in the art.
Correspondingly, in order to obtain a large L ED display, a plurality of smaller L ED display panels are generally adopted to form a larger L ED display in a splicing manner, however, the realization mode has a very obvious defect that dark stripes formed between adjacent L ED display panels greatly influence the display effect of a L ED display.
As shown in FIGS. 1 and 2, an L ED display is formed by splicing at least two L ED display panels, and a L0 ED display includes a display area and a peripheral area, wherein the display area includes L1 ED chips arranged in an array, and the peripheral area refers to an area where L2 ED chips are not arranged, and may be provided with a plurality of driving circuits and driving chips, etc. generally, in the same L3 ED display panel, the distance between adjacent L ED chips in the display area is D, and when two L ED display panels are spliced with each other, the distance between L ED chips on the edges of two adjacent L ED display panels at the splice is D, generally, L ED chips can be arranged more densely, and the blank area on the edges of L ED display panels is wider, so D > D, and also because D > D, the splicing between two L ED display panels can generate dark stripes visually, and further affect the display effect of L ED display panels.
In order to solve the above problem, the utility model provides an L ED display panel and a L ED display aims at making some improvements through the L ED chip that is in the marginal portion to avoid forming the dark line between two L ED display panels, and then improve L ED display panel's display effect.
As shown in fig. 3, 4 and 5, a L ED display panel includes a display backplane 1, an L ED array 2 is disposed on the display backplane 1, and the L ED array 2 includes L ED chips 3 disposed side by side, the present invention creatively adopts two kinds of light emitting chips, namely a vertical emission type light emitting chip 301 and an oblique emission type light emitting chip 302, as L ED chips 3, specifically, at least one vertical emission type light emitting chip 301 is disposed inside the L ED array 2, a principal ray emitted by the vertical emission type light emitting chip 301 faces a direction perpendicular to the display backplane 1, at least one oblique emission type light emitting chip 302 is disposed at an edge of the L ED array 2, and a principal ray emitted by the oblique emission type light emitting chip 302 faces a direction away from a geometric center of the display backplane 1, in fig. 3, 4 and 5, a direction indicated by an arrow is L ED chip 3.
More than one light ray is emitted from each L ED chip, and of the light rays emitted from L ED chips, there are more strongly directionally coherent light rays which constitute the principal rays of the L ED chip.
Generally, the principal ray emitted by the L ED chip 3 is directed in a direction perpendicular to the display back plate 1, while in the above technical solution, the principal ray emitted by the oblique-emission type light emitting chip 302 is directed away from the geometric center of the display back plate 1, and the principal ray direction problem of the oblique-emission type light emitting chip 302 is specifically described in the following three embodiments.
As shown in FIG. 3, in the first embodiment, two L ED display panels are arranged on the left and right, a vertical emission type light emitting chip 301 is arranged near the center of the L ED display panel, the main light emitted by the vertical emission type light emitting chip 301 is oriented perpendicular to the direction of the display backplane 1, and an inclined emission type light emitting chip 302 is arranged on the rightmost edge of the vertical emission type light emitting chip, the main light emitted by the inclined emission type light emitting chip 302 is inclined to the right with respect to the vertical direction, correspondingly, in the L ED display panel on the right, the main light emitted by the inclined emission type light emitting chip 301 is inclined to the left with respect to the vertical direction, the main light emitted by the inclined emission type light emitting chip 302 is inclined to the left with respect to the vertical direction, and the light condensing effect of the adjacent display panels is avoided by the adjacent light emitting chips 36 of the display panels, thus avoiding the generation of the integral dim effect between adjacent display panels.
As shown in FIG. 4, in the second embodiment, the L ED display panel has the same structure and operation principle as the first embodiment, and is not repeated herein, and the different points are focused here.
In addition, after installation, a gap exists between the bottom of the groove 4 and the L ED chip 3, and the pressure applied to the L ED chip 3 during bonding can be prevented from damaging devices on the L ED display panel.
The epitaxial part of the L ED chip specifically comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer, and after holes and electrons come out of the first semiconductor layer and the second semiconductor layer, the holes and the electrons are combined at the light emitting layer and release energy in the form of photons, so that light is emitted.
In the implementation of the technical solution of the present invention, the L ED display panel may have a circular, triangular, trapezoidal, rectangular and irregular shape, preferably, the display backplate 1 has a rectangular plate-shaped structure, the L ED array 2 is disposed on the display backplate 1, the edges of the L ED array 2 are located on four sides of the display backplate 1, the oblique-emission-type light emitting chips 302 are disposed on at least one side of the display backplate 1, specifically, the display backplate 1 may have the oblique-emission-type light emitting chips 302 disposed on one side, the oblique-emission-type light emitting chips 302 may be disposed on two sides, or the oblique-emission-type light emitting chips 302 may be disposed on three or four sides.
For example, when three or more L ED display panels are tiled end-to-end side-by-side to obtain a L ED display panel, the L ED display panel at the two ends need only have oblique-emitting light-emitting chips 302 on one side, while the L ED display panel in the middle needs to have oblique-emitting light-emitting chips 302 on two opposite sides, and for example, when four L ED display panels are tiled side-by-side to obtain a2 x 2L ED display panel, the L ED display panel needs to have oblique-emitting light-emitting chips 302 on two adjacent sides, and for example, when a 3 x 3L ED display panel is tiled side-by-side to obtain a 3 x 3ED display panel, the L ED display panel at the middle needs to have oblique-emitting light-emitting chips 302 on four sides, and the other L ED display panels need to have oblique-emitting light-emitting chips 302 on three adjacent sides, or two adjacent sides, and the oblique-emitting chips 302 are positioned on two adjacent sides to improve the overall effect of the oblique-emitting light-emitting chips L ED display panel.
As shown in fig. 6, 7, 8 and 9, the display back plate 1 includes a substrate 101, a circuit layer 102 and a planarization layer 103, wherein the circuit layer 102 is disposed on the substrate 101, and the planarization layer 103 is disposed on the circuit layer 102. Specifically, the vertical emission type light emitting chip 301 and the oblique emission type light emitting chip 302 are disposed on the planarization layer 103, and the vertical emission type light emitting chip 301 and the oblique emission type light emitting chip 302 are connected to the circuit layer 102, respectively.
Specifically, the substrate 101 mainly serves as a structural support. The substrate 101 comprises a transparent glass material, such as silicon dioxide. The substrate 101 may also comprise a transparent plastic material, such as: polyether sulfone, polyacrylate, polyether imide, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose propionate, or other organic materials.
As shown in fig. 7 and 9, preferably, the circuit layer 102 includes a driving circuit for driving L ED chips 3, such as a thin film transistor 6, the thin film transistor 6 includes an active layer 601, a gate 602, a source 603, and a drain 604, the source 603 and the drain 604 are respectively connected to the active layer 601, the thin film transistor 6 is connected to the L ED chip 3 through the drain 604, the gate insulating layer 105 is used for isolating the gate 602 and the active layer 601 on the thin film transistor 6, the interlayer insulating layer 106 is used for isolating the source 603 and the gate 602 on the thin film transistor 6, and is used for isolating the drain 604 and the gate 602 on the thin film transistor 6, by providing the thin film transistor 6 corresponding to the L ED chips 3 one by one, each L ED chip 3 can be driven one by one, which helps to achieve high speed, high brightness, and high contrast of a L ED display panel, and improve the performance of a L ED display panel.
The thin film transistor 6 is preferably a top gate thin film transistor, but may be a bottom gate thin film transistor. The top gate type thin film transistor can significantly reduce the parasitic capacitance formed between the source/drain 604 and the gate 602, thereby increasing the on-state current of the thin film transistor, further increasing the operating speed of the device, and facilitating the reduction of the size of the device.
The active layer 601 on the thin film transistor 6 may be comprised of a semiconductor material such as amorphous silicon or polysilicon. The active layer 601 may also include other materials, such as: an organic semiconductor material or an oxide semiconductor material. The gate 602, the source 603, and the drain 604 may include a low resistance metal material such as aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten, copper, or the like.
Specifically, the planarization layer 103 covers the circuit layer 102, so that the height difference formed by the sizes of various devices on the circuit layer 102 can be eliminated and planarized. One of the main functions of the planarization layer 103 is to make the layers above the planarization layer 103 uniform in flatness. The color shift problem can be improved to some extent by increasing the thickness of the planarization layer 103, which can improve the flatness of the metal anode, so that the upper layers are more flat and easier to correct the color shift.
The planarization layer 103 specifically includes an organic material such as polymethyl methacrylate or polystyrene, and may further include a polymer derivative having a phenol group, a propylene-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any combination thereof.
As shown in fig. 7 and 9, more specifically, the circuit layer 102 includes a buffer layer 104, a gate insulating layer 105, and an interlayer insulating layer 106 disposed from bottom to top, the buffer layer 104 is disposed on the substrate 101, and the planarization layer 103 is disposed on the interlayer insulating layer 106, a thin film transistor 6 is further disposed in the circuit layer 102, and the thin film transistor 6 corresponds to the L ED chip 3 one to one, wherein the buffer layer 104 is disposed above the substrate 101 to provide a substantially flat surface above the substrate 101, thereby reducing or preventing foreign materials or moisture from penetrating the substrate 101, the buffer layer 104 specifically includes an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride, the buffer layer 104 may also include an organic material, such as polyimide, polyester, or acrylic, the gate insulating layer 105 may insulate the gate 602 from the active layer 601, the gate insulating layer 105 may include an inorganic material, such as SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO 5, or ZnO2, the gate insulating layer 106 may further include an inorganic material, such as SiO 36387, SiO 3, SiO2, a SiO 3, a SiO2, a SiO 387, a SiO 3, a SiO 6335.
As shown in fig. 6 and 8, preferably, the planarization layer 103 is further provided with a first contact electrode 107 and a second contact electrode 108, the circuit layer 102 is provided with a power ground line therein, the first contact electrode 107 is connected to the drain electrode 604 of the thin film transistor 6, the second contact electrode 108 is connected to the power ground line, and the first contact electrode 107 and the second contact electrode 108 are further connected to the L ED chip 3, the L ED chip 3 is connected to the drain electrode 604 of the thin film transistor 6 and the power ground line provided in the circuit layer 102 through the first contact electrode 107 and the second contact electrode 108 of the planarization layer 103, respectively, so that the reliability of connection can be ensured.
As shown in fig. 6 and 8, in particular, a first contact electrode 107 and a second contact electrode 108 are disposed on the surface of the planarization layer 103, a through hole 5 is disposed on the planarization layer 103, the first contact electrode 107 is connected to the thin film transistor 6 in the circuit layer 102 through the filling material in the through hole 5, and the second contact electrode 108 is connected to the power ground in the circuit layer 102, correspondingly, the first contact electrode 107 and the second contact electrode 108 are respectively bonded to the first electrode 303 and the second electrode 307 on the L ED chip 3, the filling material in the through hole 5 and the connected material may include aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten, copper, or the like.
As shown in fig. 10 and 11, each of the vertical emission type light emitting chip 301 and the oblique emission type light emitting chip 302 includes a first electrode 303, a first semiconductor layer 304, a light emitting layer 305, a second semiconductor layer 306, and a second electrode 307, which are sequentially disposed. Two sides of the first semiconductor layer 304, the light emitting layer 305 and the second semiconductor layer 306 form a first side surface 308 and a second side surface 309 which are oppositely arranged.
The utility model discloses pioneering ground in perpendicular emergent type luminescence chip 301, will first side 308 sets up to straight plane, will second side 309 sets up to straight plane or inclined plane, and makes perpendicular emergent type luminescence chip 301's chief ray is followed first side 308 outgoing. The utility model discloses still pioneering ground in slope emission type luminescence chip 302, will first side 308 sets up to the straight plane, will second side 309 sets up to the inclined plane, and makes slope emission type luminescence chip 302's chief ray is followed second side 309 outgoing.
The vertical emission type light emitting chip 301 may be provided with two kinds of similarities. In the first type of vertical emission light-emitting chip 301, the first side surface 308 is a straight plane, the second side surface 309 is also a straight plane, the first side surface 308 and the second side surface 309 are parallel to each other, and the other side surfaces except the first side surface 308 are provided with mirror-like reflective layers for condensing light. In the second type of vertical emission light-emitting chip 301, the first side surface 308 is a straight plane, the second side surface 309 is an inclined plane, an inclined angle is formed between the first side surface 308 and the second side surface 309, and the other side surfaces except the first side surface 308 are provided with mirror-like reflective layers for condensing light. The vertical emission type light emitting chip 301 is used to emit a principal ray perpendicular to the display back plate 1, and therefore, in the above two similar vertical emission type light emitting chips 301, the principal ray is emitted from the first side surface 308 and is perpendicular to the display back plate 1.
Correspondingly, in the oblique-emission type light emitting chip 302, the first side 308 is set to be a straight plane, and the second side 309 is set to be an oblique plane, which is the utility model of changing L the emergent direction of the principal ray of the ED chip 3 by using the refraction effect of the oblique plane to the light.
As shown in fig. 12 and 13, when the vertical emission type light emitting chip whose second side is an inclined plane is mounted, the second side faces down into the groove 4, and the first contact electrode 107 is connected to the first electrode 303 of the L ED chip 3 and the second contact electrode 108 is connected to the second electrode 307 of the L ED chip 3.
As shown in fig. 14 and 15, when the oblique-emission type light-emitting chip is mounted, the first side 308 is recessed downward into the groove 4, and the first contact electrode 107 is connected to the first electrode 303 of the L ED chip 3, and the second contact electrode 108 is connected to the second electrode 307 of the L ED chip 3.
As shown in fig. 5, in the third embodiment, the vertical emission type light emitting chip 301 with the second side surface 309 being an inclined plane is adopted, and the L ED chip 3 with the same structure can be respectively used as the vertical emission type light emitting chip 301 and the inclined emission type light emitting chip 302 to manufacture a L ED display panel, which is convenient for the manufacturer to manufacture and can reduce the manufacturing cost.
Correspondingly, the utility model also provides a L ED display, the L ED display is formed by the concatenation of at least two above-mentioned L0 ED display panels, in adjacent L1 ED display panel, the chief ray that the slope emission type luminescence chip 302 on the first piece of L2 ED display panel sent and the chief ray that the slope emission type luminescence chip 302 on the second piece of L ED display panel sent are crisscross each other in L ED display panel, L ED array 2's inside is provided with vertical emission type luminescence chip 301, and L ED array 2's edge is provided with slope emission type luminescence chip 302, send the chief ray towards keeping away from the display backplate 1 geometric center direction through slope emission type luminescence chip 302, adopt the concatenation of L ED display panel of above-mentioned structure to obtain L ED display, can form the spotlight effect between adjacent L ED display panel to avoid producing the dark line between the adjacent L ED display panel, promote holistic display effect.
To sum up, the utility model provides an L ED display panel and be provided with this kind of L ED display panel's L ED display can guarantee to produce the dark line between the adjacent L ED display panel, promotes holistic display effect among the prior art, because L ED chip 3's interval is too big and produce the dark line between the adjacent display backplate 1, and then lead to the display effect not good, the problem that will solve of the utility model is how to eliminate the dark line, the utility model discloses the technical scheme who adopts is provided with a slope plane on L ED chip 3, changes the outgoing direction of principal ray through this slope plane to form crossing light at the edge of two backplates, and then eliminate the dark line, the utility model discloses the point has two, one, is provided with the L ED chip 3 that the slope light-emitting at the edge of display backplate 1 overall, is provided with the slope plane on two, L ED chip 3 for change the outgoing direction of light.
It is to be understood that the invention is not limited to the above-described embodiments, and that modifications and variations may be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
Claims (9)
1. An L ED display panel, comprising a display backplane having a L ED array disposed thereon, the L ED array comprising a plurality of L ED chips, wherein:
the L ED chip comprises a vertical emission type light-emitting chip and an inclined emission type light-emitting chip;
at least one vertical emergent light-emitting chip is arranged inside the L ED array, and the direction of a main ray emitted by the vertical emergent light-emitting chip is perpendicular to the direction of the display back plate;
the edge of the L ED array is provided with at least one inclined emission type light-emitting chip, and the main light emitted by the inclined emission type light-emitting chip faces away from the geometric center of the display back plate;
the display back plate comprises a substrate, a circuit layer and a planarization layer which are sequentially arranged; a plurality of first contact electrodes and second contact electrodes are arranged on the planarization layer;
the vertical emission type light-emitting chip and the inclined emission type light-emitting chip are both vertical L ED chips, and each of the vertical emission type light-emitting chip and the inclined emission type light-emitting chip comprises a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a second electrode which are sequentially stacked;
the vertical emission type light emitting chip and the oblique emission type light emitting chip are both disposed on the planarization layer, and a first electrode and a second electrode of the L ED chip are respectively soldered to the first contact electrode and the second contact electrode;
in the vertical emergent light-emitting chip, the side surface deviating from the display back plate is a straight plane, and the straight plane is parallel to the surface of the display back plate;
in the inclined emission type light emitting chip, a side surface deviating from the display back plate is an inclined plane, and the inclined plane is inclined to a side edge of the display back plate.
2. The L ED display panel of claim 1, wherein the planarization layer has a groove disposed between the first and second contact electrodes, the epitaxial portion of the L ED chip is disposed in the groove, and a gap is formed between the L ED chip and the bottom of the groove.
3. The L ED display panel of claim 2, wherein the vertical emission light-emitting chips and the tilted emission light-emitting chips are L ED chips of the same size and type.
4. The L ED display panel of claim 1, wherein the display back plate has a rectangular plate-like structure, the L ED arrays are disposed on the display back plate, and the edges of the L ED arrays are located at four sides of the display back plate;
the oblique emission type light emitting chip is arranged on at least one side edge of the display back plate.
5. The L ED display panel of claim 1, wherein the circuit layer comprises a buffer layer, a gate insulating layer and an interlayer insulating layer;
the buffer layer is disposed on the substrate, and the planarization layer is disposed on the interlayer insulating layer.
6. The L ED display panel of claim 5, wherein thin film transistors are further disposed in the circuit layer, the thin film transistors corresponding to the L ED chips one-to-one.
7. The L ED display panel of claim 6, wherein the TFT comprises an active layer, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode are respectively connected to the active layer, and the TFT is connected to the L ED chip via the drain electrode;
the grid insulating layer is used for isolating the grid electrode on the thin film transistor from the active layer;
the interlayer insulating layer is used for isolating the source electrode and the grid electrode on the thin film transistor and isolating the drain electrode and the grid electrode on the thin film transistor.
8. The L ED display panel of claim 7, wherein a power ground is disposed in the circuit layer, the first contact electrode is connected to the drain of the TFT, the second contact electrode is connected to the power ground, and the first and second contact electrodes are further connected to the first and second electrodes of the L ED chip, respectively.
9. An L ED display, wherein the L ED display is formed by splicing at least two L ED display panels as claimed in any one of claims 1-8;
in the L ED display panel, the chief rays emitted by the oblique-emission light-emitting chips on the L ED display panel of the first block and the chief rays emitted by the oblique-emission light-emitting chips on the L ED display panel of the second block are mutually staggered.
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| WO2021189777A1 (en) * | 2020-03-25 | 2021-09-30 | 重庆康佳光电技术研究院有限公司 | Led display panel and led display |
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| WO2021189777A1 (en) * | 2020-03-25 | 2021-09-30 | 重庆康佳光电技术研究院有限公司 | Led display panel and led display |
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