CN211045468U

CN211045468U - High-reliability L ED bracket, L ED and light-emitting device

Info

Publication number: CN211045468U
Application number: CN201921667102.3U
Authority: CN
Inventors: 杨丽敏; 孙平如; 王传虎
Original assignee: Huizhou Jufei Photoelectric Co ltd
Current assignee: Huizhou Jufei Photoelectric Co ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2020-07-17
Anticipated expiration: 2029-09-30

Abstract

The utility model provides a high reliability L ED support, L ED and illuminator, include the coarsening layer that forms after the coarsening is handled in the edge of contact zone, the part or all that bear the surrounding area of L0 ED chip at the functional zone is provided with the coarsening layer that forms after the coarsening is handled, L ED support and the L ED's that utilizes this support to make problem that reliable performance is poor among the prior art has been solved, also be through setting up the coarsening layer in the edge of contact zone, make the cohesion of enclosure body and base plate stronger, the region sets up the coarsening layer around bearing L ED chip at the functional zone simultaneously, make the colloid stronger with the cohesion of base plate, thereby the reliability and the durability of L ED that L ED support and utilized this L ED support to make, make L ED can be better be applicable to the application scenario of various environment, more do benefit to L ED's popularization and use.

Description

High-reliability L ED bracket, L ED and light-emitting device

Technical Field

The utility model relates to an L ED (L light Emitting Diode) field especially relates to a high reliability L ED support, L ED and illuminator.

Background

Because L ED has advantages such as abundant in color, small, environmental protection and energy saving, long life-span, consequently, its use and popularization that all fields all obtained, for example include but not limited to daily lighting, outdoor lighting, light decoration, advertising sign, car illumination or instruction, traffic indication etc. because L ED is the external environment diverse who uses in different fields, consequently put forward great requirement to L ED's reliability, wherein L ED support's firmness and the firmness of encapsulation are an important measurement index of L ED reliability.

Referring to fig. 1-1 and 1-2, the conventional L ED bracket includes a plastic enclosure 10 forming a reflective cavity, a substrate 11 enclosed by the plastic enclosure 10, wherein a portion of an area of an upper surface of the substrate 11 directly contacts the plastic enclosure 10, which is called a contact area, and another portion of the area is located at a bottom of the reflective cavity as a functional area, which can be used for carrying L ED chips and other possible electronic devices, and routing, die bonding, and as a light reflection area, etc., it can be understood that the functional area does not completely occupy the bottom of the reflective cavity, and there is a portion of other area around the functional area, which can be used for subsequent L ED packaging and bonding with a colloid, in the conventional L ED bracket, the reliability of the L ED bracket is not high due to the bonding strength of the substrate 11 and the plastic enclosure 10 and the packaging strength is not enough.

SUMMERY OF THE UTILITY MODEL

The utility model provides a high reliability L ED support, L ED and illuminator, the technical problem who mainly solves is that the reliability of solving current L ED support and L ED that utilizes this support to make is poor.

In order to solve the technical problem, the utility model provides a high reliability L ED support, be in including base plate and setting the enclosure body of base plate upper surface, base plate upper surface region includes contact zone and functional area, the contact zone with the enclosure body contacts, the functional area is used for bearing L ED chip the edge of contact zone is provided with the coarsening layer that forms after the alligatoring treatment the region is provided with the coarsening layer that forms after the alligatoring treatment around the functional area bears L ED chip.

In an embodiment of the invention, the edge of the contact area is the outside edge of the contact area, and/or the edge of the contact area is the inside edge of the contact area.

In an embodiment of the present invention, the substrate includes a first substrate, a second substrate, and an insulating isolation strip for isolating the first substrate from the second substrate.

In an embodiment of the present invention, a roughening layer formed after roughening treatment is partially or completely disposed at an edge of the first substrate contact region, and a roughening layer formed after roughening treatment is partially or completely disposed at a peripheral region of the first substrate functional region where L ED chips are supported;

and/or a roughened layer formed after roughening treatment is arranged on part or all of the edge of the second substrate contact region, and a roughened layer formed after roughening treatment is arranged on part or all of the peripheral region of the second substrate functional region bearing L ED chips.

In an embodiment of the present invention, a roughened layer formed after roughening treatment is provided at a position where the first substrate and/or the second substrate contact the insulating isolation belt.

In an embodiment of the present invention, when a part of the peripheral region of the functional region, which bears the L ED chip, is provided with a roughened layer formed after roughening treatment, the enclosure is a reflective enclosure;

when all the peripheral areas of the L ED chips carried by the functional areas are provided with coarsened layers formed after coarsening treatment, the enclosure body is a transparent enclosure body.

In an embodiment of the present invention, a plating layer is further disposed at the edge region where the substrate upper surface is located, the plating layer is in direct contact with the substrate upper surface, and the roughening layer is disposed on the plating layer.

In order to solve the above problem, the present invention further provides an L ED, including the high reliability L ED bracket and at least one L ED chip as described above, wherein the L ED chip is disposed on the substrate, and the L ED chip is electrically connected to the substrate.

In an embodiment of the invention, the surrounding area is bonded to the gel.

In order to solve the above problem, the present invention further provides a light emitting device, including the L ED as described above, the light emitting device is a lighting device, a light signal indicating device, a light supplementing device or a backlight device.

The utility model has the advantages that:

the utility model provides a high reliability L ED support, L ED and illuminator, including the base plate and set up the enclosure body at the base plate upper surface, base plate upper surface region includes contact zone and functional area, the contact zone contacts with the enclosure body, the functional area is used for bearing L ED chip, wherein, be provided with the coarsening layer that forms after the alligatoring at the edge of contact zone, the area is provided with the coarsening layer that forms after the alligatoring treatment around bearing L ED chip at the functional area, L ED support and the problem that L ED's that utilizes this support to make is poor reliable performance among the prior art has been solved, also be in the utility model discloses, through set up the coarsening layer in the edge of contact zone, increased the area of combining of enclosure body and base plate, make the cohesion of enclosure body and base plate stronger, the area sets up the coarsening layer around bearing L ED chip at the functional area simultaneously, when being used for when filling the colloid and going into the area of enclosing when encapsulating L ED, increase colloid and the area of combining with the area on every side, make the colloid stronger with the cohesion of base plate, thereby it is more durable to have promoted L ED support and utilize the ED 3625, make the various more durable use of ED environment be applicable to make and various ED use of the feasible ED L.

Drawings

FIG. 1-1 is a top view of an L ED holder;

1-2 are cross-sectional views of the L ED stent shown in FIG. 1-1;

fig. 2-1 is a top view of an L ED bracket according to an embodiment of the present invention;

FIG. 2-2 is a first top view of the L ED stent of FIG. 2-1 with a roughened layer;

FIG. 2-3 is a second top view of the L ED stent of FIG. 2-1 with a roughened layer;

FIG. 2-4 is a top view three of the L ED stent of FIG. 2-1 with a roughened layer;

2-5 are top views four of the L ED stent of FIG. 2-1 with a roughened layer;

2-6 are top views five of the L ED stent of FIG. 2-1 with a roughened layer;

2-7 are top views six of the L ED stent of FIG. 2-1 with a roughened layer;

2-8 are top plan views seven of the L ED stent of FIG. 2-1 with a roughened layer;

2-9 are top views eight of the L ED stent of FIG. 2-1 with a roughened layer;

2-10 are top views nine of the L ED stent of FIG. 2-1 with a roughened layer;

2-11 are top views ten of L ED stents shown in FIG. 2-1 with a roughened layer;

FIGS. 2-12 are top views eleven of the L ED stent of FIG. 2-1 with a roughened layer;

2-13 are top views twelve of the L ED stent of FIG. 2-1 provided with a roughened layer;

fig. 3-1 is a top view of an L ED bracket according to a second embodiment of the present invention;

FIG. 3-2 is a first schematic diagram of the coarsened layer shown in FIG. 3-1;

FIG. 3-3 is a second schematic view of the roughened layer shown in FIG. 3-1;

3-4 is a third schematic view of the coarsened layer shown in FIG. 3-1;

wherein, reference numeral 10 in fig. 1-1 to 1-2 is a wall body, 11 is a substrate;

reference numeral 20 in fig. 2-1 to 2-13 is a surrounding wall, 211 is a first substrate, 212 is a second substrate, 213 is an insulating isolation strip, diagonal lines indicate functional regions, regions other than the diagonal lines are contact regions, 23 is a region (shown as dense line regions) for carrying L ED chips in the functional regions, and other regions are peripheral regions (shown as non-dense line regions) for carrying L ED chips;

reference numeral 30 in fig. 3-1 is a wall body, 311 is a first substrate, 312 is a second substrate, 313 is an insulating isolation strip, diagonal lines indicate functional regions, regions other than the diagonal lines are contact regions, 33 is a region for carrying L ED chips in the functional regions (shown as dense line regions), and other regions are peripheral regions for carrying L ED chips (shown as non-dense line regions);

it is noted that, in order to better illustrate the protection scheme of the present application,

regions

23, 33 occupied by L ED chips are defined for subsequent use in packaging, which are not the divided regions in L ED bracket implementations.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are described in further detail below with reference to the accompanying drawings by way of specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The first embodiment is as follows:

in order to solve the problem of poor reliability of the conventional L ED support, the present embodiment provides a L ED support with high reliability, which includes a substrate and a wall body disposed on an upper surface of the substrate, an upper surface region of the substrate includes a contact region and a functional region, the contact region is in contact with the wall body, the functional region is used for carrying a L ED chip, wherein a roughened layer formed after roughening processing is disposed at an edge of the contact region, and a roughened layer formed after roughening processing is partially or completely disposed in a peripheral region of the functional region carrying the L ED chip.

For example, as shown in fig. 2-1, the substrate includes a first substrate 211, a second substrate 212, and an insulating isolation strip 213, wherein the insulating isolation strip 213 is located between the first substrate 211 and the second substrate 212 to isolate the first substrate from the second substrate, and a fence body 20 encloses the first substrate 211, the second substrate 212, and the insulating isolation strip 213, and the upper surfaces of the first substrate 211 and the second substrate 212 have a functional region (shown by the hatched region in fig. 2-1) and a contact region (shown by the region other than the hatched region in fig. 2-1) in contact with the fence body 20, wherein 23 is a region (shown by the dense line region) for carrying L ED chips, and 23 is a peripheral region (shown by the non-dense line region) for carrying L ED chips.

The first substrate and the second substrate in this embodiment are both conductive substrates, and the conductive substrate in this embodiment may be substrates made of various conductive materials, for example, various metal conductive substrates, including but not limited to a copper substrate, an aluminum substrate, an iron substrate, and a silver substrate; the conductive substrate may also be a hybrid material conductive substrate containing a conductive material, such as a conductive rubber or the like.

Optionally, in this embodiment, a reflective layer may be further disposed in the functional region of at least one of the first substrate and the second substrate to improve the light extraction efficiency of the bracket, and the reflective layer may be various light reflective layers capable of improving the light extraction efficiency, such as, but not limited to, a silver plating layer.

Optionally, in this embodiment, the back surface of at least one of the first substrate and the second substrate is exposed to the bottom of the enclosure body to serve as the electrode pad. Of course, in some examples, the back surface of at least one of the first substrate and the second substrate may not be used as the bonding pad, and the side surface thereof may be used as the bonding pad, and the specific arrangement may be flexibly determined according to the specific application requirement.

Optionally, in this embodiment, the area of the first substrate is larger than the area of the second substrate. Of course, in some examples, the area of the first substrate may also be smaller than that of the second substrate, and the specific arrangement may be flexibly set according to the specific application requirement.

Optionally, the enclosure body in this embodiment may be made of various insulating materials, for example, but not limited to, various plastics, insulating ceramics, and the like. For example, in one example, the materials that can be used for the enclosure include, but are not limited to, Poly (1, 4-cyclohexanedimethanol terephthalate) (PCT, Poly1, 4-cyclohexylene dimethyl terephthalate), Epoxy Molding Compound (EMC), Unsaturated Polyester (UP) resin, polyester resin (PET), high temperature nylon (PPA plastic), and Polycarbonate (PC).

Optionally, the material of the insulating isolation strip in this embodiment may be the same as or different from the wall body, and it may be formed together with the wall body or formed separately.

In addition, it should be understood that the forming manner of the enclosure body in the embodiment may also be flexibly selected, for example, but not limited to, forming by injection molding.

In this embodiment, a roughened layer is disposed on the substrate and at the edge of the region where the region is tightly attached to the wall body.

In one example, as shown in fig. 2-2, the edge of the contact region is the outer edge of the contact region (shown in bold in fig. 2-2), wherein all regions corresponding to the outer edge may be roughened, or a portion of the regions corresponding to the outer edge may be roughened, and at the same time, all the surrounding regions except the region 23 where the functional region is used to carry L ED chips are roughened (shown in bold in fig. 2-2).

In one example, as shown in fig. 2-3, the edge of the contact region is the outer edge of the contact region (shown in bold in fig. 2-3), wherein all corresponding regions at the outer edge may be roughened, and a corresponding portion of the outer edge may be roughened, while the portion of the peripheral region outside the region 23 where the functional region is used to carry L ED chips is roughened (shown in bold in fig. 2-3).

In one example, as shown in fig. 2-4, the edge of the contact region is the inner edge of the contact region (shown in bold in fig. 2-4), wherein all corresponding regions at the inner edge may be roughened, and a corresponding portion of the inner edge may be roughened, while all surrounding regions except the region 23 where the functional region is used to carry L ED chips are roughened (shown in bold in fig. 2-4).

In one example, as shown in fig. 2-5, the edge of the contact region is the inner edge of the contact region (shown in bold in fig. 2-5), wherein all corresponding regions at the inner edge may be roughened, and a corresponding portion of the inner edge may be roughened, while the portion of the peripheral region outside the region 23 where the functional region is used to carry L ED chips is roughened (shown in bold in fig. 2-5).

In one example, as shown in fig. 2-6, the edges of the contact region are the outer edge and the inner edge of the contact region (shown in bold in fig. 2-6), wherein all regions corresponding to the outer edge may be roughened, a part of regions corresponding to the outer edge may be roughened, all regions corresponding to the inner edge may be roughened, a part of regions corresponding to the inner edge may be roughened, and all surrounding regions except the region 23 for carrying L ED chips in the functional region are roughened (shown in bold in fig. 2-6).

In one example, as shown in fig. 2-7, the edges of the contact region are the outer edge and the inner edge of the contact region (shown in bold in fig. 2-7), wherein all regions corresponding to the outer edge may be roughened, a portion of the region corresponding to the outer edge may be roughened, all regions corresponding to the inner edge may be roughened, a portion of the region corresponding to the inner edge may be roughened, and a portion of the surrounding region outside the region 23 where the functional region is used to carry L ED chips is roughened (shown in bold in fig. 2-7).

It should be understood that moisture and the like enter from the edge of the contact area, so the bonding strength required at the edge of the contact area relative to the middle area of the contact area should be greater, when the bonding strength at the edge of the contact area is insufficient, the bonding strength at the middle area of the contact area is probably not sufficient, and when the bonding strength at the middle area of the contact area is insufficient, the bonding strength at the edge of the contact area is not affected much; it is obvious that it is not significant to set the coarsened layer on all the regions of the contact region, and the manner of setting the coarsened layer will undoubtedly increase the manufacturing process and time, so the coarsened layer can be set only at the edge of the contact region in the embodiment to increase the bonding area between the enclosure body and the substrate, i.e. to enhance the bonding force between the enclosure body and the substrate.

In one example of this implementation, please refer to fig. 2-8, the roughening layer may be provided only at the inner edge of the contact region on the first substrate (shown in bold in fig. 2-8), alternatively, the roughening layer may be provided only at the outer edge of the contact region on the first substrate, and may also be provided at both the inner edge and the outer edge of the contact region on the first substrate, and simultaneously, please refer to fig. 2-8, the roughening layer may be provided at all of the peripheral region outside the region 23 of the first substrate functional region for carrying L ED chips (shown in bold in fig. 2-8).

In one example of this implementation, please refer to fig. 2-9, the roughening layer may be provided only at the inner edge of the contact region on the first substrate (shown in bold in fig. 2-9), alternatively, the roughening layer may be provided only at the outer edge of the contact region on the first substrate, and may also be provided at both the inner edge and the outer edge of the contact region on the first substrate, and simultaneously, as shown in fig. 2-9, the roughening layer may be provided at a portion of the peripheral region outside the region 23 of the first substrate functional region for carrying L ED chips (shown in bold in fig. 2-9).

In one example of this implementation, please refer to fig. 2-10, the roughening layer may be provided only at the inner edge of the contact region on the second substrate (shown in bold in fig. 2-10), alternatively, the roughening layer may be provided only at the outer edge of the contact region on the second substrate, and may also be provided at both the inner edge and the outer edge of the contact region on the second substrate, and simultaneously, as shown in fig. 2-10, the roughening layer may be provided at all of the peripheral region outside the region 23 for carrying L ED chips in the functional region of the first substrate (shown in bold in fig. 2-10).

In one example of this implementation, please refer to fig. 2-11, the roughening layer may be provided only at the inner edge of the contact region on the second substrate (shown in bold in fig. 2-11), alternatively, the roughening layer may be provided only at the outer edge of the contact region on the second substrate, and may also be provided at both the inner edge and the outer edge of the contact region on the second substrate, and simultaneously, as shown in fig. 2-11, the roughening layer may be provided at a portion of the peripheral region outside the region 23 of the first substrate functional region for carrying L ED chips (shown in bold in fig. 2-11).

In one example of this implementation, as shown in FIGS. 2-12, a roughened layer may be provided on the first substrate at the inner edge of the contact region and at the same time at the inner edge of the contact region on the second substrate (shown in bold in FIGS. 2-12), optionally a roughened layer may be provided on the first substrate at the outer edge of the contact region and at the same time at the outer edge of the contact region on the second substrate, optionally a roughened layer may be provided on the first substrate at the inner edge and at the outer edge of the contact region and at the same time at the inner edge and at the outer edge of the contact region on the second substrate, and as shown in FIGS. 2-12, a roughened layer may be provided on all of the peripheral regions outside the region 23 where the functional regions of the first and second substrates are used to carry L ED chips (shown in bold in functional regions in FIGS. 2-12).

In one example of this implementation, as shown in FIGS. 2-13, a roughened layer may be provided on the first substrate at the inner edge of the contact region and at the same time at the inner edge of the contact region on the second substrate (shown in bold in FIGS. 2-13), optionally a roughened layer may be provided on the first substrate at the outer edge of the contact region and at the same time at the outer edge of the contact region on the second substrate, optionally a roughened layer may be provided on the first substrate at the inner edge and at the outer edge of the contact region and at the same time at the inner edge and at the outer edge of the contact region on the second substrate, and as shown in FIGS. 2-13, a roughened layer may be provided on the first substrate and at the portion of the peripheral region outside the region 23 where the functional regions of the second substrate are used to carry L ED chips (shown in bold in FIGS. 2-13).

It should be noted that fig. 2-2 to fig. 2-13 described above are only some specific examples, and in practical applications, the flexible adjustment may be made according to specific application scenarios.

It should be further noted that the roughened layer formed by roughening treatment is disposed in the peripheral region of the functional region L ED chip, and has a scattering or diffuse reflection effect on light received from the L ED chip, so that the transparent support (i.e., the transparent enclosure) or the reflective support (i.e., the reflective enclosure) may be respectively matched according to different roughening treatments, when the roughened layer formed by roughening treatment is disposed in all the peripheral region of the functional region L ED chip, such as shown in fig. 2-2, fig. 2-4, fig. 2-6, fig. 2-8, fig. 2-10, and fig. 2-12, the roughened layer formed by roughening treatment is disposed in the peripheral region of the functional region L ED chip, so that L ED light can uniformly diffuse in the gel and exit from the transparent enclosure, so as to improve light distribution uniformity of the lamp bead, and when the roughened layer formed by roughening treatment is disposed in the peripheral region of the functional region L ED chip, such as shown in fig. 2-3, fig. 2-4, fig. 2-7, fig. 2-9, fig. 2-11, and fig. 2-13, the roughened layer formed by the functional region L is adapted for preventing light from scattering in the center of the.

Optionally, in this embodiment, the coarse layer is a curved coarse layer or a linear coarse layer, or a coarse layer combining a curve and a straight line, and in practical application, the coarse layer may be flexibly adjusted according to a specific application scenario.

It should be understood that the inner edge of the contact region is at the interface with the functional region, and both are coincident regions.

The high-reliability L ED bracket provided by the embodiment comprises a substrate and an enclosing wall body arranged on the upper surface of the substrate, wherein the upper surface area of the substrate comprises a contact area and a functional area, the contact area is in contact with the enclosing wall body, and the functional area is used for bearing a L ED chip, wherein a coarsened layer formed after coarsening treatment is arranged at the edge of the contact area, and a coarsened layer formed after coarsening treatment is arranged at the peripheral area of the functional area for bearing the L ED chip, so that the problem of poor reliability of the L ED bracket and the L ED prepared by using the bracket in the prior art is solved.

Example two:

for ease of understanding, the present embodiment is illustrated with a specific L ED bracket as an example.

Please refer to fig. 3-1, which is a schematic diagram illustrating a roughened layer disposed at an edge of a region on a substrate and closely attached to a wall, wherein 30 is the wall, 311 is a first substrate, 312 is a second substrate, 313 is an insulating isolation strip, upper surfaces of the first substrate 311 and the second substrate 312 have a functional region (shown by the diagonal line region in fig. 3-1) and a contact region (shown by the other regions except the diagonal line region in fig. 3-1) contacting with the

wall

30, 33 in the functional region is a functional region (shown by the dense line region) for carrying L ED chips and achieving L ED chips and substrate electrical connection, and the other regions are peripheral regions (shown by the non-dense line region) for carrying L ED chips.

Referring to fig. 3-1, a roughened layer (shown in bold in fig. 3-1) is provided at the inner edge of the contact region on each of the first and

second substrates

311 and 312, while a roughened layer (shown in bold in fig. 3-1) is provided at the peripheral region portion of the first and

second substrates

311 and 312 outside the region 23 where the functional region is used to carry L ED chips, and additionally, a roughened layer is provided at the position where the first and

second substrates

311 and 312 contact the insulating isolation tape 313.

Alternatively, as shown in fig. 3-2, the coarsened layer may be configured as a curved coarsened layer.

Alternatively, as shown in fig. 3-3, the coarsened layer may be provided as a linear coarsened layer.

Alternatively, as shown in fig. 3-4, the roughened layer may be a combination of a linear and a curved roughened layer.

It should be noted that the above lists only a few common coarsening layer settings, and in practical applications, the settings can be flexibly adjusted according to specific application scenarios.

Meanwhile, the coarsened layer is arranged in the surrounding area of the functional area bearing L ED chips and used for increasing the bonding area of the colloid and the surrounding area when the colloid is filled into the surrounding area during packaging of L ED, so that the bonding force of the colloid and the substrate is stronger, the reliability and the durability of the L ED support and L ED prepared by the L ED support are improved, L ED can be better suitable for application scenes of various environments, and the popularization and the use of L ED are facilitated.

Example three:

the present embodiment provides an L ED, which includes the L ED bracket as shown in the above embodiments, and further includes at least one L ED chip, the L ED chip is disposed on the substrate, and the L ED chip is electrically connected to the substrate, it should be understood that the L ED chip in the present embodiment may be a flip L ED chip, or a front L ED chip, and the electrical connection between the L ED chip and the substrate is realized by, but not limited to, a conductive wire, a conductive adhesive, or other conductive material.

It should be clear that the L ED mount in each of the above embodiments is used for L ED package, and fixes the L ED chip at the bottom of the reflective cavity, that is, at the functional region, a specific implementation manner may be that after welding and fixing of the L ED chip are completed, a sealant is filled in an enclosure region formed by the enclosure body to seal L ED chip, where the sealant may be one or more combinations of a package adhesive, a luminescence conversion adhesive, and a diffusion adhesive, and a green phosphor and a red phosphor are excited by blue light, so that white light with a better effect can be obtained, the package adhesive may be a package adhesive having adhesiveness such as epoxy resin, silica gel, and silicone resin, and the package adhesive is mixed into a sealant, and injected into the enclosure body by a potting machine to package the L ED chip, because the peripheral region of the functional region bearing the L ED chip is a roughened layer, a bonding effect between the peripheral region and the sealant is better, so that an overall bonding effect between the sealant and the substrate can be improved, and a reliability of the L ED chip is greatly improved.

It should be understood that the color of L ED light emitted and presented to the user can be flexibly set according to actual needs and application scenarios, and the color of L ED light emitted and presented can be flexibly controlled by, but not limited to, the color of light emitted by L ED chip itself, whether L ED includes a luminescence conversion layer, and the type of luminescence conversion layer when L ED includes a luminescence conversion layer.

In an example of this embodiment, the L ED may further include a packaging adhesive layer or a diffusion adhesive layer disposed on the L ED chip (when the light emitting conversion adhesive layer is disposed on the L ED chip, it is disposed on the light emitting conversion adhesive layer), and the diffusion adhesive layer is formed by adding diffusion powder or silicon powder into the packaging adhesive.

It should be understood that in one example, the luminescence conversion glue layer may be a phosphor glue layer containing phosphor, a colloid containing quantum dot photo-induced material, or other luminescence conversion glue or film capable of realizing luminescence conversion, and may also include diffusing powder or silicon powder, etc. as required, and the manner of forming the encapsulation glue layer, the lens glue layer, or the diffusing glue layer on the L ED chip in this embodiment includes, but is not limited to, dispensing, molding, spraying, pasting, etc.

For example, the luminescence conversion layer may include a phosphor paste layer, a phosphor film, or a quantum dot QD film; the phosphor glue layer and the phosphor film can be made of inorganic phosphor, and can be inorganic phosphor doped with rare earth elements, wherein the inorganic phosphor includes but is not limited to at least one of silicate, aluminate, phosphate, nitride and fluoride phosphor.

For another example, the quantum dot QD film may be fabricated using quantum dot phosphors; quantum dot phosphors include, but are not limited to, at least one of BaS, AgInS2, NaCl, Fe2O3, In2O3, InAs, InN, InP, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaAs, GaN, GaS, GaSe, InGaAs, MgSe, MgS, MgTe, PbS, PbSe, PbTe, Cd (SxSe1-x), BaTiO3, PbZrO3, CsPbCl3, CsPbBr3, CsPbI 3.

In this embodiment, the light emitted by the L ED chip itself may be visible light, or ultraviolet light and infrared light invisible to the naked eye, and when the light emitted by the L ED chip itself is ultraviolet light and infrared light invisible to the naked eye, a luminescence conversion layer may be disposed on the L ED chip to convert the invisible light to visible light, so that the light emitted by the L ED is visible light for the user.

The present embodiment further provides a lighting device, which includes L ED. exemplified in the above embodiments, and the lighting device in the present embodiment may be a lighting device, an optical signal indicating device, a light supplement device, or a backlight device, and the like, and when the lighting device is a lighting device, the lighting device may be specifically a lighting device applied in various fields, such as a desk lamp, a fluorescent lamp, a ceiling lamp, a down lamp, a street lamp, a projection lamp, and the like in daily life, such as a high beam lamp, a low beam lamp, an atmosphere lamp, and the like in an automobile, such as an operation lamp, a low electromagnetic lighting lamp, and a lighting lamp of various medical instruments, such as various colored lamps, landscape lighting lamps, and advertisement lamps, and the like in the decoration field, when the lighting device is an optical signal indicating device, specifically an optical signal indicating device applied in various fields, such as a signal indicating lamp in the traffic field, various signal status indicating lamps on a communication device in the communication field, various indicating lamps on a vehicle, and the like, when the lighting device is an optical signal indicating device, such as a light supplement lamp in the camera field, such as a flash lamp, a light supplement lamp, and the backlight module, and the like of a mobile phone.

It should be understood that the above applications are only a few of the applications exemplified by the present embodiment, and that the application of L ED is not limited to the several fields exemplified above.

The foregoing is a more detailed description of embodiments of the present invention, and the specific embodiments are not to be considered in a limiting sense. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.

Claims

1. A high-reliability L ED support comprises a substrate and a wall body arranged on the upper surface of the substrate, wherein the upper surface area of the substrate comprises a contact area and a functional area, the contact area is in contact with the wall body, the functional area is used for bearing a L ED chip, and the high-reliability L ED support is characterized in that a coarsened layer formed after coarsening treatment is arranged at the edge of the contact area, and part or all of the peripheral area of the functional area bearing a L ED chip is provided with a coarsened layer formed after coarsening treatment.

2. The high reliability L ED bracket of claim 1, wherein an edge of the contact area is an outer edge of the contact area and/or an edge of the contact area is an inner edge of the contact area.

3. The high reliability L ED bracket of claim 2, wherein the substrate includes a first substrate, a second substrate, and an insulating spacer tape that separates the first substrate from the second substrate.

4. The high-reliability L ED support according to claim 3, wherein, part or all of the edge of the first substrate contact area is provided with a roughened layer formed by roughening treatment, and part or all of the peripheral area of the first substrate functional area carrying L ED chips is provided with a roughened layer formed by roughening treatment;

5. The high-reliability L ED bracket of claim 4, wherein a roughened layer formed by roughening treatment is provided at a position where the first and/or second substrate contacts the insulating isolation tape.

6. The high-reliability L ED support according to any one of claims 1-5, wherein when the portion of the functional region carrying the L ED chip in the surrounding area is provided with a roughened layer formed by roughening treatment, the enclosure is a reflective enclosure;

7. The high reliability L ED bracket of any one of claims 1-5, wherein a plating layer is further provided at an edge region of the substrate upper surface, the plating layer being in direct contact with the substrate upper surface, the roughened layer being provided on top of the plating layer.

8. An L ED, comprising the high reliability L ED bracket of any of claims 1-7 and at least one L ED chip, the L ED chip being disposed on the substrate, the L ED chip being electrically connected to the substrate.

9. L ED, according to claim 8, characterized in that the surrounding area is glued to the glue.

10. A lighting device comprising the L ED of claim 8 or 9, wherein the lighting device is a lighting device, a light signal indicating device, a light supplementing device or a backlight device.