CN211016461U - Display screen controller - Google Patents
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- CN211016461U CN211016461U CN201922374792.XU CN201922374792U CN211016461U CN 211016461 U CN211016461 U CN 211016461U CN 201922374792 U CN201922374792 U CN 201922374792U CN 211016461 U CN211016461 U CN 211016461U
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Abstract
The embodiment of the utility model discloses display screen controller, include: the main control circuit is arranged on the first circuit board; the video processing circuit is arranged on the second circuit board and connected with the main control circuit on the first circuit board; the video source input circuit is arranged on the third circuit board and is connected with the video processing circuit on the second circuit board; the video source output circuit is arranged on the fourth circuit board and is connected with the video processing circuit on the second circuit board; wherein the first circuit board, the second circuit board, the third circuit board and the fourth circuit board are different circuit boards. The utility model discloses a display screen controller has solved display screen controller human-computer interaction and has experienced not good and each module can not be replaced, and it is with high costs to upgrade the renewal, the difficult problem of later maintenance.
Description
Technical Field
The utility model relates to a display screen control technical field especially involves a display screen controller.
Background
At present, L ED display screens are widely applied to various occasions in our daily life due to the characteristics of high visibility, low power consumption and the like, and L ED display screen controllers need to develop products with different models in order to be applied to different market environments.
In the hardware architecture of current L ED display screen controller, carry out human-computer interaction through MCU, and MCU, FPGA, video input interface and video output interface are located same PCB mainboard, and human-computer interaction experiences not good and each module can not be replaced, leads to display screen controller upgrading update with high costs, and the later maintenance is difficult.
Disclosure of Invention
Therefore, the embodiment of the utility model provides a display screen controller is provided, it can solve display screen controller human-computer interaction and experience not good and each module can not be replaced, and it is with high costs to upgrade the renewal, the difficult problem of later maintenance.
Specifically, the utility model provides a display screen controller, display screen controller includes: the main control circuit is arranged on the first circuit board and is provided with an embedded main control processor and a main control connector; the video processing circuit is arranged on the second circuit board and is provided with a first connector, a second connector and a third connector, wherein the first connector is electrically connected with the main control connector of the main control circuit; the video source input circuit is arranged on the third circuit board and is provided with an input connector which is electrically connected with the second connector of the video processing circuit; the video source output circuit is arranged on the fourth circuit board and is provided with an output connector which is electrically connected with the third connector of the video processing circuit; wherein the first circuit board, the second circuit board, the third circuit board and the fourth circuit board are different circuit boards.
At present, in the hardware architecture of the existing display screen controller, an MCU, an FPGA, a video input interface and a video output interface are located on the same PCB mainboard, human-computer interaction experience is poor, modules cannot be replaced, the upgrading and updating cost of the display screen controller is high, and later maintenance is difficult. The utility model discloses divide the hardware structure of display screen controller into mutually independent main control circuit module, video processing circuit module, video source input circuit module and video source output circuit module according to different functions, each module is an solitary circuit board, and easily the replacement has reduced the product renewal cost.
In an embodiment of the present invention, the main control circuit includes: the main control processor is connected with the main control Ethernet interface; the master control connector is connected with the master control processor; wherein the master Ethernet interface, the master processor and the master connector are located on the first circuit board.
In an embodiment of the present invention, the video source input circuit includes: at least one video source input interface; at least one retimer correspondingly connected to the at least one video source input interface; the input connector is connected with the at least one retimer; wherein the at least one video source input interface, the at least one retimer, and the input connector are located on the third circuit board.
In an embodiment of the present invention, the video source output circuit includes: the first output connector is connected with the network transformer; the Ethernet physical layer transceiver is connected with the network transformer; an Ethernet interface connected to the Ethernet physical layer transceiver; wherein the network transformer, the Ethernet physical layer transceiver, the Ethernet interface, and the first output connector are located on the fourth circuit board.
In an embodiment of the present invention, the display screen controller further includes: the second video source output circuit is arranged on a fifth circuit board, and the fifth circuit board is different from the first circuit board, the second circuit board, the third circuit board and the fourth circuit board; wherein the second video source output circuit comprises: an optical fiber interface; the second output connector is connected with the optical fiber interface; the video processing circuit further comprises a fourth connector electrically connected with the second output connector; wherein the fiber optic interface and the second output connector are located on the fifth circuit board.
In an embodiment of the present invention, the video processing circuit includes: a programmable logic device; the microprocessor is connected with the programmable logic device; the first connector, the second connector, the third connector and the fourth connector are respectively connected with the programmable logic device and the microprocessor; wherein the programmable logic device, the microprocessor, the first connector, the second connector, the third connector, and the fourth connector are located on the second circuit board.
In an embodiment of the present invention, the main control connector includes a plurality of first RGMII interfaces, a plurality of first PCIE interfaces and a plurality of first GPIO interfaces, the first connector includes a plurality of second RGMII interfaces, a plurality of second PCIE interfaces and a plurality of second GPIO interfaces, the plurality of first RGMII interfaces correspond to the plurality of second RGMII interfaces and are connected, the plurality of first PCIE interfaces correspond to the plurality of second PCIE interfaces and are connected and the plurality of first GPIO interfaces correspond to the plurality of second GPIO interfaces and are connected, wherein the plurality of second RGMII interfaces, the plurality of second PCIE interfaces and a part of the plurality of second GPIO interfaces connect the programmable logic device, and another part of the plurality of second GPIO interfaces electrically connect the microprocessor.
In an embodiment of the present invention, the input connector includes: a plurality of first SerDes interfaces and a plurality of first GPIO interfaces, the second connector comprising a plurality of second SerDes interfaces and a plurality of second GPIO interfaces, the plurality of first SerDes interfaces being correspondingly connected with the plurality of second SerDes interfaces, the plurality of first GPIO interfaces being correspondingly connected with the plurality of second GPIO interfaces; wherein one part of the plurality of second SerDes interfaces and the plurality of second GPIO interfaces is electrically connected with the programmable logic device, and the other part of the plurality of second GPIO interfaces is electrically connected with the microprocessor.
In one embodiment of the present invention, the master connector, the input connector, the first output connector, the second output connector, the first connector, the second connector, the third connector and the fourth connector are high-pressure connectors.
In an embodiment of the present invention, the first output connector is a first SAS interface, the third connector is a second SAS interface, and the first SAS interface and the second SAS interface establish a connection through a communication line.
In view of the above, the above technical features of the present invention can have one or more of the following advantages: a) the hardware structure of the display screen controller is divided into a main control circuit module, a video processing circuit module, a video source input circuit module and a video source output circuit module which are independent and split according to different functions, and each module is an independent circuit board, so that the replacement is easy, and the product updating cost is reduced; b) the main control circuit comprises a main control processor, manages the man-machine interaction of the whole equipment, issues instructions and sets parameters, and the video processing circuit comprises a microprocessor serving as a chip on the coprocessor management circuit board and used for monitoring the working states of the programmable logic device and the main control processor, so that the reliable and stable running state can be ensured, and better man-machine interaction experience can be provided.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display screen controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the main control circuit shown in FIG. 1;
FIG. 3 is a schematic diagram of the input circuit of the video source of FIG. 1;
FIG. 4 is a schematic diagram of the video source output circuit of FIG. 1;
FIG. 5 is a schematic diagram of a second video source output circuit of FIG. 1;
fig. 6 is a schematic structural diagram of the video processing circuit in fig. 1.
Detailed Description
It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described with reference to the accompanying drawings in conjunction with embodiments.
In order to make those skilled in the art better understand the technical solution of the present invention, the following description will be made in conjunction with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solution in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all embodiments should belong to the protection scope of the present invention.
It should be noted that the terms "first", "second", and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the division of the embodiments in the present invention is only for convenience of description and should not be construed as a limitation, and features in various embodiments may be combined and referred to each other without contradiction.
Fig. 1 is a schematic structural diagram of a display screen controller according to an embodiment of the present invention, as shown in fig. 1, the display screen controller includes: a first circuit board 10, a second circuit board 20, a third circuit board 30, and a fourth circuit board 40.
The first circuit board 10 is provided with a main control circuit 101, the second circuit board 20 is provided with a video processing circuit 201, the third circuit board 30 is provided with a video source input circuit 301, and the fourth circuit board 40 is provided with a video source output circuit 401. The first circuit board 10, the second circuit board 20, the third circuit board 30, and the fourth circuit board 40 are different circuit boards.
The video processing circuit 201 is communicatively connected to the main control circuit 101, the video source input circuit 301, and the video source output circuit 401, respectively. The first Circuit Board 10, the second Circuit Board 20, the third Circuit Board 30, and the fourth Circuit Board 40 are, for example, PCB (Printed Circuit Board).
Further, as shown in fig. 1, the display screen controller further includes, for example, a fifth circuit board 50, the fifth circuit board 50 is provided with a second video source output circuit 501, and the second video source output circuit 501 is communicatively connected to the video processing circuit 201. The fifth circuit board 50 is a different circuit board from the first circuit board 10, the second circuit board 20, the third circuit board 30, and the fourth circuit board 40, and the fifth circuit board 50 is, for example, a PCB board.
Fig. 2 is a schematic structural diagram of the main control circuit 101 in fig. 1, and as shown in fig. 2, the main control circuit 101 includes: a master ethernet interface 1011, a master processor 1012, and a master connector 1013. The master ethernet interface 1011, the master processor 1012 and the master connector 1013 are all disposed on the first circuit board 10.
The main control processor 1012 is, for example, an ARM processor, the processor is, for example, an embedded processor, and the model of the main chip is, for example, RK3399, and is used as a core controller to manage human-computer interaction, command issuing, parameter setting, and the like of the entire device. The main ethernet interface 1011 is, for example, an RJ45 port, and is communicatively connected to the main processor 1012, for example, gigabit communication, so that data interaction is faster, and the main ethernet interface 1011 is also connected to a PC for man-machine interaction, for example, gigabit communication. The master processor 1012 is also connected to a master connector 1013, and the master connector 1013 is, for example, a high-contact plug-in, and is used to connect the video processing circuit 201.
Fig. 3 is a schematic structural diagram of the video source input circuit 301 in fig. 1, and as shown in fig. 3, the video source input circuit 301 includes: at least one video source input interface 3011, at least one retimer 3012, and an input connector 3013. Wherein, at least one video source input interface 3011, at least one retimer 3012 and input connector 3013 are disposed on the third circuit board 30.
The video source input interface 3011 is, for example, a data interface such as an HDMI interface, a DVI interface, or an SDI interface, and is configured to input video source data. The retimer 3012 is connected to the video source input interface 3011, and is used to unify data clocks of different interface protocols and ensure video source input of multi-protocol data. The retimer 3012 is also connected to an input connector 3013, and the input connector 3013 is a high-density card, for example, for connecting the video source input circuit 301 and the video processing circuit 201. Retimer 3012 is, for example, a Retimer chip.
Fig. 4 is a schematic structural diagram of the video source output circuit 401 in fig. 1, and as shown in fig. 4, the video source output circuit 401 includes: ethernet interface 4013, ethernet physical layer transceiver 4012, network transformer 4011 and first output connector 4014. Wherein, ethernet interface 4013, ethernet physical layer transceiver 4012, network transformer 4011 and first output connector 4014 are disposed on the fourth circuit board.
However, in practical applications, the space of the video source output circuit may be insufficient when the first output connector 4014 uses a high-voltage plug, so the first output connector 4014 may also be an SAS interface, SAS (serial attached SCSI), that is, serial attached SCSI, which uses serial technology to obtain higher transmission speed and improves the internal space structure of the circuit by shortening a connection line, the first output connector 4014 is connected to the network transformer 4011, the network transformer 4011 is connected to the ethernet physical layer transceiver 4012, the network transformer 4011 may be used for level signal coupling and is compatible with ethernet physical layer transceivers of different levels, the ethernet physical layer transceiver 4012 is also connected to the ethernet interface 4013 for outputting video source data, where the ethernet physical layer transceiver 4012 is, for example, a network PHY chip, such as a gigabit PHY chip, or an ethernet PHY 853 ethernet PHY chip, such as an ethernet PHY module 358284.
Fig. 5 is a schematic structural diagram of the second video source output circuit 501 in fig. 1, and as shown in fig. 5, the second video source output circuit 501 includes: a fiber optic interface 5011 and a second output connector 5012. Among them, the optical fiber interface 5011 and the second output connector 5012 are provided on the fifth circuit board 50.
The second output connector 5012 is used to connect the video processing circuit 201 and the second video source output circuit 501. The second output connector 5012 is also connected to an optical fiber interface 5011, and the optical fiber interface 5011 can be used for outputting video source data in a long distance.
Fig. 6 is a schematic structural diagram of the video processing circuit 201 in fig. 1, and as shown in fig. 6, the video processing circuit 201 includes: microprocessor 2011, programmable logic device 2012, first connector 2013, second connector 2014, third connector 2015, and fourth connector 2016. The microprocessor 2011, the programmable logic device 2012, the first connector 2013, the second connector 2014, the third connector 2015 and the fourth connector 2016 are disposed on the second circuit board 20.
The microprocessor 2011 is connected to the programmable logic device 2012, for example, by an SPI bus. The microprocessor 2011 employs, for example, a high performance MCU having a chip model of, for example, STM32H750, and is configured to manage peripheral chips on the second circuit board 20, identify other circuits for management, monitor the operating states of the programmable path device and the main control processor, and operate an HDMI soft core. The microprocessor 2011 is also connected to the master processor 1012 via the master connector 1013 of the master circuit 101, for example, via a USB interface, and the microprocessor 2011 is configured to monitor the operating status of the master processor 1012 and the programmable logic device 2012.
The programmable logic device 2012 is connected to a first connector 2013, a second connector 2014, a third connector 2015 and a fourth connector 2016, respectively. The first connector 2013 is, for example, a high-contact connector and corresponds to the master connector 1013 of the master circuit 101. The second connector 2014 is a high-contact plug, for example, and corresponds to the input connector 3013 connected to the video source input circuit 301. The third connector 2015 is, for example, a high-contact plug and corresponds to the first output connector 4014 connected to the video source output circuit 401, and when the first output connector 4014 is, for example, an SAS interface, the third connector 2015 also corresponds to an SAS interface. The fourth connector 2016 is, for example, a high-contact card, and corresponds to the second output connector 5012 connected to the second video source output circuit 501. Programmable logic device 2012 acts as a core processing unit for receiving, processing, and sending video source data, as well as data interaction with master processor 1012 and microprocessor 2011.
The Programmable logic device 2012 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic devices.
Further, the master connector 1013 includes, for example: a plurality of first RGMII interfaces, a plurality of first PCIE interfaces, and a plurality of first GPIO interfaces, the first connector 2013 includes, for example: the first plurality of RGMII interfaces are correspondingly connected with the second plurality of RGMII interfaces, the first plurality of PCIE interfaces are correspondingly connected with the second plurality of PCIE interfaces, and the first plurality of GPIO interfaces are correspondingly connected with the second plurality of GPIO interfaces. One part of the second RGMII interfaces, the second PCIE interfaces, and the second GPIO interfaces is connected to the programmable logic device 2012 through the first connector 2013, and the other part of the second GPIO interfaces is connected to the microprocessor 2011 through the first connector 2013.
The input connector 3013 includes, for example: a plurality of first SerDes interfaces and a plurality of first GPIO interfaces, and second connector 2014 includes, for example: the multiple first SerDes interfaces are correspondingly connected with the multiple second SerDes interfaces, and the multiple first GPIO interfaces are correspondingly connected with the multiple second GPIO interfaces; one part of the second SerDes interfaces and the second GPIO interfaces is electrically connected to the programmable logic device 2012, and the other part of the second GPIO interfaces is electrically connected to the microprocessor 2011.
The third connector 2015 and the fourth connector 2016 are the same as the second connector, and for example, include a plurality of second SerDes interfaces and a plurality of second GPIO interfaces, one part of the plurality of second SerDes interfaces and the plurality of second GPIO interfaces is electrically connected to the programmable logic device 2012, and another part of the plurality of second GPIO interfaces is electrically connected to the microprocessor 2011.
Output connector 4014 and second output connector 5012 are identical to input connector 3013, and include, for example: the plurality of first SerDes interfaces and the plurality of first GPIO interfaces are respectively and correspondingly connected with the second SerDes interface and the second GPIO interface of the third connector 2015 and the fourth connector 2016.
Further, the video source input interface 3011 of the video source input circuit 301 is not limited to the HDMI interface and the SDI interface, and may be other types of input interfaces, and when a user needs another type of video source input interface, the video source input interface 3011 in the video source input circuit 301 currently set on the third circuit board 30 may be replaced with a corresponding video source input interface, and the programmable logic device 2012 of the video processing circuit 201 may be changed to a program of a corresponding version. Each video source input circuit has the corresponding product code, a user can select the required video source input circuit to replace by himself, the difficulty of later maintenance of the display screen controller is reduced, and the cost is saved.
Further, the ethernet interface 4013 of the video source output circuit 401 is, for example, a 5G-rate network port, and if the network port rate of the receiving end is different from the network port rate of the ethernet interface 4013, the network port control IP core inside the programmable logic device 2012 of the video processing circuit 201 will automatically detect the network port rate of the ethernet interface 4013, and perform network port rate adjustment, so as to meet the user requirement.
As described above, the optical fiber interface 5011 of the second video output circuit 501 is, for example, a 40G-rate optical fiber interface, and if the user considers that the price of the 40G-rate optical fiber interface is too high, the 40G-rate optical fiber interface can be replaced by a corresponding optical fiber interface if the transmission requirement of the video source is met.
It should be noted that the display screen controller disclosed in this embodiment is a card-insertion device, where the first circuit board 10 and the main control circuit 101 disposed on the first circuit board 10 may be referred to as a main control sub-card, the second circuit board 20 and the video processing circuit 201 disposed on the second circuit board 20 may be referred to as a video processing sub-card, the third circuit board 30 and the video source input circuit 301 disposed on the third circuit board 30 may be referred to as a video source input sub-card, the fourth circuit board 40 and the video source output circuit 401 disposed on the fourth circuit board 40 may be referred to as a video source output sub-card, and the fifth circuit board 50 and the second video source output circuit 501 disposed on the fifth circuit board 50 may be referred to as a second video source output sub-card.
To sum up, the hardware structure of the display screen controller provided by the utility model is divided into the mutually independent main control circuit module, the video processing circuit module, the video source input circuit module and the video source output circuit module according to different functions, each module is an independent circuit board, which is easy to replace and reduces the product updating cost; the main control circuit comprises a main control processor, manages the man-machine interaction of the whole equipment, issues instructions and sets parameters, and the video processing circuit comprises a microprocessor serving as a chip on the coprocessor management circuit board and used for monitoring the working states of the programmable logic device and the main control processor, so that the reliable and stable running state can be ensured, and better man-machine interaction experience can be provided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. A display screen controller, comprising:
the main control circuit is arranged on the first circuit board and is provided with an embedded main control processor and a main control connector;
the video processing circuit is arranged on the second circuit board and is provided with a first connector, a second connector and a third connector, wherein the first connector is electrically connected with the main control connector of the main control circuit;
the video source input circuit is arranged on the third circuit board and is provided with an input connector which is electrically connected with the second connector of the video processing circuit;
the video source output circuit is arranged on the fourth circuit board and is provided with a first output connector, and the first output connector is electrically connected with the third connector of the video processing circuit;
wherein the first circuit board, the second circuit board, the third circuit board and the fourth circuit board are different circuit boards.
2. The display screen controller of claim 1, wherein the master control circuit comprises:
the main control processor is connected with the main control Ethernet interface; the main control connector is connected with the main control processor;
wherein the master Ethernet interface, the master processor and the master connector are located on the first circuit board.
3. A display screen controller as claimed in claim 2, wherein the video source input circuit comprises:
at least one video source input interface;
at least one retimer correspondingly connected to the at least one video source input interface; the input connector is connected with the at least one retimer;
wherein the at least one video source input interface, the at least one retimer, and the input connector are located on the third circuit board.
4. A display screen controller as claimed in claim 3, wherein the video source output circuit comprises:
the first output connector is connected with the network transformer;
the Ethernet physical layer transceiver is connected with the network transformer;
an Ethernet interface connected to the Ethernet physical layer transceiver;
wherein the network transformer, the Ethernet physical layer transceiver, the Ethernet interface, and the first output connector are located on the fourth circuit board.
5. The display screen controller of claim 4, further comprising:
the second video source output circuit is arranged on a fifth circuit board, and the fifth circuit board is different from the first circuit board, the second circuit board, the third circuit board and the fourth circuit board;
wherein the second video source output circuit comprises:
an optical fiber interface;
the second output connector is connected with the optical fiber interface;
the video processing circuit further comprises a fourth connector electrically connected with the second output connector;
wherein the fiber optic interface and the second output connector are located on the fifth circuit board.
6. The display screen controller of claim 5, wherein the video processing circuit comprises:
a programmable logic device;
the microprocessor is connected with the programmable logic device;
the first connector, the second connector, the third connector and the fourth connector are respectively connected with the programmable logic device and the microprocessor;
wherein the programmable logic device, the microprocessor, the first connector, the second connector, the third connector, and the fourth connector are located on the second circuit board.
7. The display screen controller of claim 6, wherein the master controller comprises a plurality of first RGMII interfaces, a plurality of first PCIE interfaces and a plurality of first GPIO interfaces, the first connector comprises a plurality of second RGMII interfaces, a plurality of second PCIE interfaces and a plurality of second GPIO interfaces, the plurality of first RGMII interfaces are correspondingly connected with the plurality of second RGMII interfaces, the plurality of first PCIE interfaces are correspondingly connected with the plurality of second PCIE interfaces and the plurality of first GPIO interfaces are correspondingly connected with the plurality of second GPIO interfaces, wherein one of the plurality of second RGMII interfaces, the plurality of second PCIE interfaces and the plurality of second GPIO interfaces is connected with the programmable logic device, and another of the plurality of second GPIO interfaces is electrically connected with the microprocessor.
8. The display screen controller of claim 6, wherein the input connector comprises: a plurality of first SerDes interfaces and a plurality of first GPIO interfaces, the second connector comprising a plurality of second SerDes interfaces and a plurality of second GPIO interfaces, the plurality of first SerDes interfaces being correspondingly connected with the plurality of second SerDes interfaces, the plurality of first GPIO interfaces being correspondingly connected with the plurality of second GPIO interfaces; wherein one part of the plurality of second SerDes interfaces and the plurality of second GPIO interfaces is electrically connected with the programmable logic device, and the other part of the plurality of second GPIO interfaces is electrically connected with the microprocessor.
9. The display screen controller of claim 6, wherein the master connector, the input connector, the first output connector, the second output connector, the first connector, the second connector, the third connector, and the fourth connector are high-profile inserts.
10. The display screen controller of claim 6, wherein the first output connector is a first SAS interface, the third connector is a second SAS interface, and the first SAS interface and the second SAS interface establish a connection via a communication line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922374792.XU CN211016461U (en) | 2019-12-25 | 2019-12-25 | Display screen controller |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922374792.XU CN211016461U (en) | 2019-12-25 | 2019-12-25 | Display screen controller |
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| CN211016461U true CN211016461U (en) | 2020-07-14 |
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| CN201922374792.XU Active CN211016461U (en) | 2019-12-25 | 2019-12-25 | Display screen controller |
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