CN210958313U - NMOS drive circuit and wafer - Google Patents

Abstract

The utility model discloses a NMOS drive circuit and wafer, including drive power supply module, buffer module, NMOS drive module, NMOS module, wherein: drive power supply module buffer module NMOS drive module with the NMOS module is connected in proper order, drive power supply module be used for do buffer module with NMOS drive module provides the power supply, buffer module is used for realizing input signal's level conversion, NMOS drive module is used for the drive the NMOS module, it is visible, through the utility model discloses an NMOS drive circuit can reduce switching loss, improves switch conversion efficiency, reduces the product volume, reduce the cost.

Description

NMOS drive circuit and wafer

Technical Field

The utility model relates to a drive circuit field especially relates to a NMOS drive circuit and wafer.

Background

With the mature and wide use of single chip microcomputer and ASIC (application specific integrated circuit) technology, there are more and more application scenarios of driving MOS, especially NMOS, by GPIO, and for example, the GPIO driving MOS is typically used in various electronic lock driving circuits, stepping motor driving circuits, PWM control driving circuits, and the like. The current common practice in the market is that GPIO plus a signal MOS or a triode inverter directly drives NMOS. However, when the current in the MOS or triode inverter is large to a certain extent, the switching speed of the NMOS will be affected, and since the switching tube of the NMOS is turned on and off for too long, the control accuracy of PWM will be seriously affected, and the switching loss will also become large.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a NMOS drive circuit and wafer through GPIO direct control NMOS module, can reduce switching loss, improves switch conversion efficiency, reduces the product volume, reduces the cost.

In a first aspect, an embodiment of the present invention provides an NMOS driving circuit, including driving power module, buffer module, NMOS driving module, NMOS module, wherein: the drive power supply module, the buffer module, the NMOS drive module and the NMOS module are sequentially connected, the drive power supply module is used for providing power supply for the buffer module and the NMOS drive module, the buffer module is used for realizing level conversion of input signals, and the NMOS drive module is used for driving the NMOS module.

In one embodiment, the driving power supply module includes a first resistor, a second resistor, a first zener diode, a second zener diode, an input enable port, and an input control port, where two ends of the first resistor are respectively connected to the input enable port and a cathode of the first zener diode, two ends of the second resistor are respectively connected to the input control port and a cathode of the second zener diode, and an anode of the first zener diode and an anode of the second zener diode are both grounded.

In one embodiment, the buffer module includes a buffer, a first pin of the buffer is connected to a cathode of the second zener diode, a second pin of the buffer is connected to a cathode of the first zener diode, a fourth pin of the buffer is connected to a first power supply, a sixth pin of the buffer is connected to a second power supply, a fifth pin of the buffer is grounded, and a third pin of the buffer is connected to the NMOS driving module.

In one embodiment, the NMOS driving module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a low-voltage reference port, a high-voltage reference port, a first comparator, a second comparator, a first MOS transistor, a second MOS transistor, and a third MOS transistor, two ends of the third resistor are respectively connected to the third pin of the buffer and the fifth pin of the first comparator, two ends of the fourth resistor are respectively connected to the low-voltage reference port and the fourth pin of the first comparator, two ends of the fifth resistor are respectively connected to the second pin of the first comparator and the gate of the first MOS transistor, the third pin of the first comparator is connected to the second power supply, the twelfth pin of the first comparator is grounded, and two ends of the sixth resistor are respectively connected to the gate of the first MOS transistor and the source of the first MOS transistor, the source of the first MOS tube is connected with the second power supply, two ends of the seventh resistor are respectively connected with the third pin of the buffer and the seventh pin of the second comparator, two ends of the eighth resistor are respectively connected with the high-voltage reference port and the sixth pin of the second comparator, two ends of the ninth resistor are respectively connected with the first pin of the second comparator and the grid electrode of the second MOS tube, the third pin of the second comparator is connected with the second power supply, the twelfth pin of the second comparator is grounded, two ends of the tenth resistor are respectively connected with the grid electrode of the second MOS tube and the second power supply, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded.

In one embodiment, the NMOS module includes an eleventh resistor, a third MOS transistor, and an output port, where two ends of the eleventh resistor are respectively connected to the drain of the second MOS transistor and the gate of the third MOS transistor, the source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the output port.

In one embodiment, when the output voltage of the third pin of the buffer is higher than the reference voltage of the high-voltage reference port, the second MOS transistor is turned on, the first MOS transistor is turned off, and the third MOS transistor is turned off.

In one embodiment, when the output voltage of the third pin of the buffer is lower than the reference voltage of the low-voltage reference port, the first MOS transistor is turned on, the second MOS transistor is turned off, and the third MOS transistor is turned on.

In one embodiment, when the third pin output voltage of the buffer is higher than the reference voltage of the low-voltage reference port and lower than the reference voltage of the high-voltage reference port, the first MOS tube and the second MOS tube are both turned off.

In one embodiment, the buffer is a dual-power reverse buffer, the first MOS transistor is a P-channel MOS transistor, and the second MOS transistor and the third MOS transistor are N-channel MOS transistors.

In a second aspect, an embodiment of the present invention provides a wafer, including the utility model provides a first aspect discloses NMOS drive circuit, the wafer includes drive power supply module, buffer module, NMOS drive module and NMOS module, the wafer is used for reducing the switching loss.

The utility model discloses in, NMOS drive circuit includes drive power supply module, buffer module, NMOS drive module, NMOS module, wherein: drive power supply module buffer module NMOS drive module with the NMOS module is connected in proper order, drive power supply module be used for do buffer module with NMOS drive module provides the power supply, buffer module is used for realizing input signal's level conversion, NMOS drive module is used for the drive the NMOS module, it is visible, through the utility model discloses an NMOS drive circuit can reduce switching loss, improves switch conversion efficiency, reduces the product volume, reduce the cost.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a circuit block diagram of an NMOS driving circuit disclosed in an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of an NMOS driving circuit according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, system, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a circuit block diagram of an NMOS driving circuit according to an embodiment of the present invention. The NMOS driving circuit 100 described in this embodiment includes a driving power module 101, a buffer module 102, an NMOS driving module 103, and an NMOS module 104, where: the driving power module 101, the buffer module 102, the NMOS driving module 103, and the NMOS module 104 are connected in sequence.

The embodiments of the present invention will be described in detail below.

Referring to fig. 2, fig. 2 is a schematic circuit structure diagram of an NMOS driving circuit disclosed in an embodiment of the present invention, including a driving power module 101, a buffer module 102, an NMOS driving module 103, and an NMOS module 104, wherein: the driving power module 101, the buffer module 102, the NMOS driving module 103, and the NMOS module 104 are sequentially connected, the driving power module 101 is configured to provide power supply for the buffer module 102 and the NMOS driving module 103, the buffer module 102 is configured to implement level conversion of an input signal, and the NMOS driving module 103 is configured to drive the NMOS module 104.

It can be seen that the utility model discloses on integrating NMOS's drive circuit and NMOS to a slice wafer, under the same processing procedure with high-power MOS, can obtain the drive logic circuit that the area is littleer, efficiency is higher, speed is faster.

In one possible example, the driving power module 101 includes a first resistor R1, a second resistor R2, a first zener diode T1, a second zener diode T2, an input enable port EN, and an input control port logic _ input, two ends of the first resistor R1 are respectively connected to the input enable port EN and a cathode of the first zener diode T1, two ends of the second resistor R2 are respectively connected to the input control port logic _ input and a cathode of the second zener diode T2, and an anode of the first zener diode T1 and an anode of the second zener diode T2 are both grounded.

The first resistor, the second resistor, the first voltage stabilizing diode and the second voltage stabilizing diode form an overcurrent protection circuit and an overvoltage protection circuit, so that when the input voltage is abnormal, the rear end circuit cannot be damaged within a certain range, when the input voltage or the input current is too large, the voltage stabilizing diode is broken down, the input voltage is pulled to a low level, the input enabling port is used for preventing the input port from abnormal operation when the input port is started or shut down, and the input port can be forced to be started or closed.

In one possible example, the Buffer module 102 includes a Buffer, a first pin of the Buffer is connected to a cathode of the second zener diode T2, a second pin of the Buffer is connected to a cathode of the first zener diode T1, a fourth pin of the Buffer is connected to the first power VCC, a sixth pin of the Buffer is connected to the second power VDD, a fifth pin of the Buffer is connected to the ground, and a third pin of the Buffer is connected to the NMOS driving module 103.

Wherein the first power supply is a front-end control power supply, the second power supply is a rear-section control power supply, the buffer is a double-power reverse buffer, is used for converting the logic levels of different input voltage values into the control level of the second power supply, can also adjust the upper edge and the lower edge of the waveform of the input voltage, enhances the anti-interference performance and drives the NMOS driving module, in this embodiment, the input logic level may be 0.9V, 1.2V, 1.5V, 1.8V, 3.3V, 3.6V, the control level of the second power supply is 12V, the buffer may be 74AUP1T34 or other type of buffer, the buffer has extremely low static power consumption and dynamic power consumption in the entire range of 1.1V to 3.6V, the fourth leg of the buffer tracks the first power supply and the sixth leg of the buffer tracks the second power supply.

In one possible example, the NMOS driving module 103 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a low-voltage reference port V_refLHigh voltage reference port V_refHA first comparator COMA, a second comparator COMB, a first MOS transistor Q1, a second MOS transistor Q2 and a third MOS transistor Q3, wherein two ends of the third resistor R3 are respectively connected to the third pin of the Buffer and the fifth pin of the first comparator COMA, and the fourth resistor R3 is connected to the fifth pin of the Buffer and the fifth pin of the first comparator COMBTwo ends of the resistor R4 are respectively connected with the low-voltage reference port V_refLAnd a fourth pin of the first comparator COMA, two ends of the fifth resistor R5 are respectively connected to the second pin of the first comparator COMA and the gate of the first MOS transistor Q1, a third pin of the first comparator COMA is connected to the second power supply VDD, a twelfth pin of the first comparator COMA is grounded, two ends of the sixth resistor R6 are respectively connected to the gate of the first MOS transistor Q1 and the source of the first MOS transistor Q1, the source of the first MOS transistor Q1 is connected to the second power supply VDD, two ends of the seventh resistor R7 are respectively connected to the third pin of the Buffer and the seventh pin of the second comparator COMB, two ends of the eighth resistor R8 are respectively connected to the high-voltage reference port V_refHAnd a sixth pin of the second comparator COMB, two ends of the ninth resistor R9 are respectively connected to the first pin of the second comparator COMB and the gate of the second MOS, a third pin of the second comparator COMB is connected to the second power supply VDD, a twelfth pin of the second comparator COMB is grounded, two ends of the tenth resistor R10 are respectively connected to the gate of the second MOS and the second power supply VDD, a drain of the second MOS Q2 is connected to the drain of the first MOS Q1, and a source of the second MOS Q2 is grounded.

Wherein the low pressure reference port V_refLIs less than the high voltage reference port V_refHThe reference voltage of, first MOS pipe is P channel MOS pipe, the second MOS pipe with the third MOS pipe is N channel MOS pipe, first comparator with the second comparator is two inside comparators of a comparator integrated circuit in fact, and this comparator integrated circuit can be LM339 or other model comparators, the utility model discloses do not limit to this.

In one possible example, the NMOS module 104 includes an eleventh resistor R11, a third MOS transistor Q3, and an output port output, two ends of the eleventh resistor R11 are respectively connected to the drain of the second MOS transistor Q2 and the gate of the third MOS transistor Q3, the source of the third MOS transistor Q3 is grounded, and the drain of the third MOS transistor Q3 is connected to the output port output.

The NMOS module is a power output control part of the whole device, and when the input control end inputs logic 0, the third pin output voltage of the buffer is higher than the high-voltage reference port V_refHWhen the reference voltage is lower than the critical voltage Vgsth, the third MOS transistor is turned off; when the input control end inputs logic 1, the output voltage of the third pin of the buffer is lower than the low-voltage reference port V_refLThe output end of the first comparator, namely the second pin, is at a low level, the first MOS transistor is turned on, the second MOS transistor is not turned on, the drain of the first comparator is pulled up to a high level (second power voltage), the gate-source capacitance Cgs of the third MOS transistor is rapidly charged by the second power supply, and when the gate voltage of the third MOS transistor is higher than the critical voltage Vgsth, the third MOS transistor is turned on; when the third pin output voltage of the buffer is higher than the low-voltage reference port V_refLIs lower than the high voltage reference port V_refHWhen the reference voltage is higher than the reference voltage, the output end of the first comparator, i.e. the second pin, is at a high level, the output end of the second comparator, i.e. the first pin, is at a low level, and the first MOS transistor and the second MOS transistor are both in a high-impedance state and are not conducted.

Wherein, still can be according to the NMOS module the voltage and the current design overcurrent protection circuit and the overvoltage crowbar, the utility model discloses do not restrict specific design method.

It can be seen that the NMOS drive module not only can drive the NMOS module, but also can reduce the resistance of the first MOS tube and the second MOS tube when the upper bridge and the lower bridge are switched on, and reduce the on-time and the off-time of the first MOS tube and the second MOS tube, thereby effectively avoiding the damage caused by the simultaneous switching on of the upper bridge and the lower bridge.

In one possible example, the present invention provides a wafer of the NMOS driving circuit based on the above embodiments, the wafer includes a driving power module, a buffer module, an NMOS driving module, and an NMOS module, and the wafer is used to reduce switching loss.

The wafer can be used in circuits such as a direct current stepping motor control circuit, a PWM control circuit (such as an LED illumination constant current drive circuit) and various electronic locks and relay drive circuits.

Therefore, the four modules are jointly designed on one wafer and can be independently made into a module IC (chip), driving is convenient, and compared with a scheme of separating devices, the driving circuit has the advantages of better stability, lower switching loss, smaller volume and lower cost in MOS packaging with the same current.

It should be noted that, for the sake of simplicity, the aforementioned embodiments of the present invention are described as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the described order of actions, because some steps can be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The embodiments of the present invention have been described in detail, and the principles and embodiments of the present invention have been explained herein using specific embodiments, and the above description of the embodiments is only used to help understand the present invention and its core ideas; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there may be changes in the specific implementation and application scope, and in summary, the content of the present specification should not be understood as the limitation of the present invention.

Claims (10)

1. The NMOS driving circuit is characterized by comprising a driving power supply module, a buffer module, an NMOS driving module and an NMOS module, wherein: the drive power supply module, the buffer module, the NMOS drive module and the NMOS module are sequentially connected, the drive power supply module is used for providing power supply for the buffer module and the NMOS drive module, the buffer module is used for realizing level conversion of input signals, and the NMOS drive module is used for driving the NMOS module.

2. The NMOS drive circuit of claim 1, wherein the drive power supply module comprises a first resistor, a second resistor, a first zener diode, a second zener diode, an input enable port, and an input control port, wherein two ends of the first resistor are respectively connected to the input enable port and a cathode of the first zener diode, two ends of the second resistor are respectively connected to the input control port and a cathode of the second zener diode, and an anode of the first zener diode and an anode of the second zener diode are both grounded.

3. The NMOS drive circuit of claim 2, wherein the buffer module comprises a buffer, a first pin of the buffer is connected to a cathode of the second zener diode, a second pin of the buffer is connected to a cathode of the first zener diode, a fourth pin of the buffer is connected to a first power supply, a sixth pin of the buffer is connected to a second power supply, a fifth pin of the buffer is grounded, and a third pin of the buffer is connected to the NMOS drive module.

4. The NMOS drive circuit of claim 3, wherein the NMOS drive module comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a low-voltage reference port, a high-voltage reference port, a first comparator, a second comparator, a first MOS transistor, a second MOS transistor and a third MOS transistor, wherein two ends of the third resistor are respectively connected with a third pin of the buffer and a fifth pin of the first comparator, two ends of the fourth resistor are respectively connected with the low-voltage reference port and a fourth pin of the first comparator, two ends of the fifth resistor are respectively connected with a second pin of the first comparator and a gate of the first MOS transistor, a third pin of the first comparator is connected with the second power supply, a twelfth pin of the first comparator is grounded, two ends of the sixth resistor are respectively connected with the grid electrode of the first MOS tube and the source electrode of the first MOS tube, the source of the first MOS tube is connected with the second power supply, two ends of the seventh resistor are respectively connected with the third pin of the buffer and the seventh pin of the second comparator, two ends of the eighth resistor are respectively connected with the high-voltage reference port and the sixth pin of the second comparator, two ends of the ninth resistor are respectively connected with the first pin of the second comparator and the grid electrode of the second MOS tube, a third pin of the second comparator is connected with the second power supply, a twelfth pin of the second comparator is grounded, two ends of the tenth resistor are respectively connected with the grid electrode of the second MOS tube and the second power supply, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded.

5. The NMOS drive circuit of claim 4, wherein the NMOS module comprises an eleventh resistor, a third MOS transistor and an output port, two ends of the eleventh resistor are respectively connected to the drain of the second MOS transistor and the gate of the third MOS transistor, the source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the output port.

6. The NMOS drive circuit of claim 4, wherein when a third pin output voltage of the buffer is higher than a reference voltage of the high voltage reference port, the second MOS transistor is turned on, the first MOS transistor is turned off, and the third MOS transistor is turned off.

7. The NMOS drive circuit of claim 6, wherein when a third pin output voltage of the buffer is lower than a reference voltage of the low-voltage reference port, the first MOS transistor is turned on, the second MOS transistor is turned off, and the third MOS transistor is turned on.

8. The NMOS drive circuit of claim 4, wherein the first MOS transistor and the second MOS transistor are both turned off when a third pin output voltage of the buffer is higher than a reference voltage of the low-voltage reference port and lower than a reference voltage of the high-voltage reference port.

9. The NMOS drive circuit of claim 7, wherein the buffer is a dual-power supply reverse buffer, the first MOS transistor is a P-channel MOS transistor, and the second MOS transistor and the third MOS transistor are N-channel MOS transistors.

10. A wafer based on the NMOS driver circuit of any one of claims 1 to 9, wherein the wafer comprises a driving power module, a buffer module, an NMOS driver module, and an NMOS module, and the wafer is used for reducing switching loss.

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