CN210895158U - E/D NMOS reference voltage source and low dropout voltage regulator - Google Patents
E/D NMOS reference voltage source and low dropout voltage regulator Download PDFInfo
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Abstract
The utility model provides a E/D NMOS reference voltage source and low dropout voltage regulator, in the E/D NMOS reference voltage source, no matter how the applied mains voltage changes, through the pre-reference source circuit based on N channel JFET can be with the output voltage of pre-reference as the fixed value, the scope of output voltage of pre-reference is wide, the technology adjustment is convenient; because the pre-reference source circuit bears withstand voltage and preliminary voltage stabilization, the input voltage of the E/D NMOS reference source circuit has small change by the power supply voltage, the wide input voltage range and the power supply rejection ratio of the E/D NMOS reference source circuit are greatly improved, and the E/D NMOS reference source circuit has the property of micro power consumption of the E/D NMOS reference; the E/D NMOS reference voltage source has a simple and reasonable circuit structure, does not need a triode, a resistor, a capacitor and the like, is additionally manufactured on the basis of a silicon gate P well E/D CMOS process, only needs to adjust the threshold voltage of the N-channel junction field effect transistor, greatly simplifies the process and reduces the cost.
Description
Technical Field
The utility model relates to a power management technical field especially relates to a AD NMOS reference voltage source and low dropout voltage regulator.
Background
In the design of a power management circuit of an analog integrated circuit, a reference voltage source determines the performance index of a low dropout power supply. Currently, there are a wide variety of reference voltage sources, including zener reference sources, bandgap reference sources with second-order compensation, and E/D NMOS reference sources with high power supply rejection ratio.
The Zener reference voltage source adopts a bipolar circuit structure and is combined with a Zener diode with process characteristics to realize the high performance of the Zener reference source; the band-gap reference source adopts a standard band-gap structure to realize high-performance band-gap reference output; the band-gap reference source with second-order compensation is designed on the basis of the band-gap reference source, so that the temperature performance of the band-gap reference is further improved; and the E/D NMOS reference voltage source with high power supply rejection ratio realizes the micro-power consumption reference voltage source with high power supply rejection ratio through a two-stage structure of serially connected enhanced and depletion NMOS tubes.
However, the above reference voltage source is difficult to satisfy the requirements of high voltage (40V), high power supply rejection ratio (60dB), and low power consumption (less than or equal to 10uA), and further the application of the above reference voltage source in a low dropout voltage regulator with high voltage, high power supply rejection ratio, and low power consumption is limited.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide an E/D NMOS reference voltage source with a wide input voltage range, which is used to solve the above-mentioned technical problems.
To achieve the above and other related objects, the present invention provides an E/D NMOS reference voltage source, comprising:
the pre-reference source circuit comprises an N-channel junction field effect transistor, wherein the grid electrode of the N-channel junction field effect transistor is grounded, the drain electrode of the N-channel junction field effect transistor is connected with power supply voltage, and the source electrode of the N-channel junction field effect transistor outputs pre-reference voltage;
and the E/D NMOS reference source circuit is connected with the pre-reference source circuit, receives the pre-reference voltage and outputs reference voltage to the outside.
Optionally, the N-channel jfet comprises a depletion mode N-channel jfet.
Optionally, the E/D NMOS reference source circuit includes:
the reference voltage starting sub-circuit is connected with the pre-reference source circuit, receives the pre-reference voltage and outputs the reference voltage outwards;
and the reference voltage regulator sub-circuit and the reference voltage starting sub-circuit regulate the reference voltage.
Optionally, the reference voltage sub-circuit comprises a plurality of NMOS transistors connected in series, and the reference voltage regulator sub-circuit comprises a plurality of NMOS transistors connected in series.
Optionally, the reference voltage starting sub-circuit comprises: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the first NMOS tube is connected with the source electrode of the N-channel junction field effect tube, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is used as a reference voltage output end; the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected together and connected with the reference voltage output end in parallel; and the substrates of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected together and connected with the reference voltage output end in parallel.
Optionally, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor include: and a depletion type NMOS tube.
Optionally, the reference voltage starting sub-circuit comprises: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the drain electrode of the fifth NMOS tube is connected with the reference voltage output end, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube, and the source electrode of the eighth NMOS tube is grounded; the grid electrodes of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected together and connected with the reference voltage output end in parallel; and the substrates of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected together and grounded.
Optionally, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor include: and an enhancement NMOS transistor.
In addition, to achieve the above and other related objects, the present invention also provides a low dropout voltage regulator including the E/D NMOS reference voltage source as described in any one of the above.
As mentioned above, the utility model discloses a AD NMOS reference voltage source has following beneficial effect:
in the pre-reference source circuit, the drain electrode of an N-channel junction field effect transistor with a grounded grid electrode bears power supply voltage, and when the N-channel junction field effect transistor is conducted, the pre-reference voltage output by the source electrode is equal to the threshold voltage and is a fixed value; when the power supply voltage changes in a wider range (high level), the N-channel junction field effect transistor is always conducted, the pre-reference voltage output by the grid electrode of the N-channel junction field effect transistor is always a constant threshold voltage, the fluctuation of the power supply of a subsequent E/D NMOS reference source circuit along with the external power supply voltage is avoided, and the working voltage range and the high power supply rejection ratio of the E/D NMOS reference source circuit are improved.
Drawings
FIG. 1 is a circuit diagram of an E/D NMOS reference voltage source according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the E/D NMOS reference voltage source of FIG. 1.
Description of the reference numerals
N1 first NMOS transistor
N2 second NMOS transistor
N3 third NMOS transistor
N4 fourth NMOS transistor
N5 fifth NMOS transistor
N6 sixth NMOS transistor
N7 seventh NMOS transistor
N8 eighth NMOS transistor
NJ N channel junction field effect transistor
N1 first equivalent NMOS transistor
N2 second equivalent NMOS transistor
VINSupply voltage
Vpre-vrefPre-reference voltage
VrefDatumVoltage of
GND ground
Detailed Description
As described in the background art, it is difficult for the reference voltage sources such as the existing zener reference source, bandgap reference source with second-order compensation, and E/D NMOS reference source with high power rejection ratio to simultaneously satisfy the requirements of high voltage, high power rejection ratio, low power consumption, etc., so that the application of the reference voltage source in the low dropout voltage regulator with high voltage, high power rejection ratio, and low power consumption is limited.
Based on this, the utility model provides a AD NMOS reference voltage source of brand-new structure, it includes reference source circuit and the AD NMOS reference source circuit in advance based on N channel junction field effect transistor, this N channel junction field effect transistor's grid ground connection, drain electrode power supply voltage, bear withstand voltage through this N channel junction field effect transistor, when power voltage changes in the broad range, the reference voltage is invariable threshold voltage in advance of its grid output, the input power of having avoided the AD NMOS reference source circuit is along with the fluctuation of external power supply voltage, the operating voltage scope and the high power supply rejection ratio of the AD NMOS reference source circuit have been improved.
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated. The structure, ratio, size and the like shown in the drawings attached to the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by people familiar with the technology, and are not used for limiting the limit conditions which can be implemented by the present invention, so that the present invention does not have the substantial significance in the technology, and any structure modification, ratio relationship change or size adjustment should still fall within the scope which can be covered by the technical content disclosed by the present invention without affecting the efficacy which can be produced by the present invention and the purpose which can be achieved by the present invention.
As shown in fig. 1, the utility model provides an E/D NMOS reference voltage source, it includes:
the pre-reference source circuit comprises an N-channel junction field effect transistor NJ, wherein the grid electrode of the N-channel junction field effect transistor NJ is grounded GND (ground), and the drain electrode of the N-channel junction field effect transistor NJ is connected with a power supply voltage VINSource electrode output pre-reference voltage Vpre-vref；
An E/D NMOS reference source circuit connected with the pre-reference source circuit for receiving the pre-reference voltage Vpre-vrefAnd externally outputs a reference voltage Vref。
Optionally, the N-channel jfet NJ comprises a depletion type N-channel jfet, i.e. a conducting channel already exists when its gate voltage is zero.
As shown in FIG. 1, the gate of the N-channel JFET NJ is connected to ground GND, and the drain is connected to a power supply voltage VINWhen the power supply voltage VINWhen the voltage is high, the N-channel junction field effect transistor NJ is conducted, and the pre-reference voltage V output by the grid electrode of the N-channel junction field effect transistor NJ ispre-vrefIs a constant threshold voltage VTHEven if the supply voltage V isINPre-reference voltage V of its grid output is changed in wide rangepre-vrefAlways at a fixed value. Wherein, the threshold voltage V in the N-channel junction field effect transistor NJ can be adjusted by the processTHThe value of (B) is usually (-4.8V to-6.8V).
In detail, the E/D NMOS reference source circuit includes:
a reference voltage sub-amplifier circuit connected to the pre-reference source circuit for receiving the pre-reference voltage Vpre-vrefAnd externally outputs a reference voltage Vref；
Reference voltage regulator sub-circuit, and reference voltage sub-circuit for regulating reference voltageVrefAnd the temperature characteristic parameters are adjusted.
The reference voltage starting sub-circuit is used as a starting circuit of the E/D NMOS reference source circuit, and the current of the E/D NMOS reference source circuit is determined; reference voltage regulator subcircuit for reference voltage VrefCarrying out pull-down regulation; the reference voltage sub-circuit comprises a plurality of NMOS tubes connected in series, and the reference voltage regulator sub-circuit comprises a plurality of NMOS tubes connected in series.
Optionally, in an embodiment of the present invention, as shown in fig. 1, the reference voltage starting sub-circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4; the drain of the first NMOS transistor N1 is connected to the source of the N-channel JFET NJ (i.e., to the pre-reference voltage V)pre-vref) The drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1, the drain of the third NMOS transistor N3 is connected to the source of the second NMOS transistor N2, the drain of the fourth NMOS transistor N4 is connected to the source of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 is used as a reference voltage output terminal for outputting a reference voltage V to the outsideref(ii) a The gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4); the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4).
The first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are depletion NMOS transistors.
Optionally, in an embodiment of the present invention, as shown in fig. 1, the reference voltage starting sub-circuit includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; the drain of the fifth NMOS transistor N5 is connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4), the drain of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5, the drain of the seventh NMOS transistor N7 is connected to the source of the sixth NMOS transistor N6, the drain of the eighth NMOS transistor N8 is connected to the source of the seventh NMOS transistor N7, and the source of the eighth NMOS transistor N8 is grounded GND; the gates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4); the substrates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected together and grounded GND.
The fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are enhancement NMOS transistors.
In detail, as shown in fig. 1 and 2, the operating principle of the E/D NMOS reference voltage source is as follows:
the pre-reference source circuit is composed of an N-channel junction field effect transistor NJ, and the drain electrode of the N-channel junction field effect transistor NJ is connected with a power supply voltage VINA gate grounded GND and a source outputting a pre-reference voltage Vpre-vrefIrrespective of the applied supply voltage VINHow to change the pre-reference voltage V output by the sourcepre-vrefTo a stable threshold voltage VTH；
Meanwhile, for the convenience of calculation, as shown in fig. 2, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are equivalent to a first equivalent NMOS transistor N1, and the threshold voltage thereof is VT1Width of channel is WN1Channel length of LN1(ii) a Similarly, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are equivalent to the second equivalent NMOS transistor N2, and the threshold voltage thereof is VT2Width of channel is WN2Channel length of LN2(ii) a When the circuit is working, the reference voltage V is outputrefSetting the current flowing through all NMOS tubes as Idd；
For the first equivalent NMOS transistor N1: due to VGS1-VT1≤VDS1The following equation (1) holds:
Idd＝kp1×(VGS1-VT1)2(1)
(1) in the formula, VGS1Represents the gate-source voltage, V, of the first equivalent NMOS transistor N1DS1The drain-source voltage of the first equivalent NMOS transistor N1, the corresponding coefficient
For the second equivalent NMOS transistor N2: due to VGS2-VT2≤VDS2The following equation (2) holds:
Idd＝kp2×(VGS2-VT2)2(2)
(2) in the formula, VGS2The gate-source voltage, V, of the second equivalent NMOS transistor N2DS2The drain-source voltage of the second equivalent NMOS transistor N2, the corresponding coefficient
According to the formula (1) and the formula (2):
kp1×(VGS1-VT1)2＝kp2×(VGS2-VT2)2(3)
as can be seen from FIG. 2, VGS1＝0，VGS2＝VrefAnd (3) can be simplified into the following steps:
kp1×VT1 2＝kp2×(Vref-VT2)2
v is to be conducted due to the second equivalent NMOS transistor N2refThe threshold voltage V must be higher than the threshold voltage V of the second equivalent NMOS transistor N2T2Therefore V isrefThe cut-off value is taken as a large value:
at the moment of electrifying the whole circuit, the NJ tube of the N-channel junction field effect tube is conducted, and the pre-reference voltage V output by the source electrode of the NJ tubepre_vrefIs equal to its threshold voltage VTHThe voltage is used as a power supply voltage of a reference voltage sub-circuit; the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 in the reference voltage starting sub-circuit are conducted to make the reference voltage VrefOutputting a high level; due to the reference voltage VrefThe voltage level is high, the fifth NMOS transistor N5, the sixth NMOS transistor N6 and the seventh NMOS transistor in the reference voltage regulator sub-circuitThe NMOS transistor N7 and the eighth NMOS transistor N8 are turned on to apply the reference voltage VrefPulled down and then gradually reaches an equilibrium value, and finally reaches a stable value, wherein the value of the stable value is related to the size and the threshold voltage of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8, and is related to the input power voltage V8INAnd threshold voltage V of N-channel junction field effect transistor NJTHIs irrelevant.
From the above analysis, it can be seen that the reference voltage V outputted by the E/D NMOS reference voltage sourcerefThe required reference voltage V can be obtained only by designing the correct parameters of the NMOS tube, which is only related to the threshold voltage of the NMOS tube and the size parameters of the NMOS tuberef。
Optionally, in an embodiment of the present invention, the basic parameter requirement is:
1) threshold voltage V of N-channel junction field effect transistor NJTH4.8V to 6.8V, source-drain breakdown voltage VDS≥40V；
2) Threshold voltages of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4: -0.8 to-1.6V, and the source-drain voltage is more than or equal to 16V;
3) threshold voltages of a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8: 0.8-1.2V, and the voltage between the source and the drain is more than or equal to 16V;
4) the gate oxide thicknesses of the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, the sixth NMOS tube N6, the seventh NMOS tube N7 and the eighth NMOS tube N8 are 35 nm-45 nm;
5) output voltage V of pre-reference source circuitpre-vref: 5.8V + -1.0V (typical value is 5.8V);
6) output voltage V of E/D NMOS reference source circuitref：1.66V±0.1V；
7) And the power supply rejection ratio of the E/D NMOS reference voltage source: not less than 75 dB;
8) the quiescent current of the E/D NMOS reference voltage source is as follows: less than or equal to 10 mu A.
It can be understood that the number of the NMOS transistors in the reference voltage sub-circuit and the reference voltage regulator sub-circuit is not necessarily the same, and the number of the corresponding NMOS transistors is not limited to four in fig. 1, and can be flexibly selected according to the design requirement of the circuit.
Furthermore, the utility model also provides a low dropout voltage regulator, it includes above-mentioned E/D NMOS reference voltage source. When the reference voltage is provided for the low-dropout voltage regulator by the E/D NMOS reference voltage source, the requirements of high voltage (wide input voltage range), high power supply rejection ratio, micro power consumption and the like can be met. The detailed structure of the low dropout voltage regulator can refer to the prior art, and is not limited herein.
In summary, in the utility model provides an among the E/D NMOS reference voltage source, no matter how the applied mains voltage changes, through the pre-reference source circuit that comprises grid ground connection, the N channel junction field effect transistor that the drain electrode connects mains voltage can be with the threshold voltage of stabilizing as N channel junction field effect transistor of pre-reference output voltage, pre-reference output voltage's wide range, technology adjustment are convenient; because the withstand voltage and the primary voltage stabilization of the pre-reference source circuit are adopted, the input voltage of the E/D NMOS reference source circuit has small change by the power supply voltage, the wide input voltage range and the power supply rejection ratio of the E/D NMOS reference source circuit are greatly improved, and the E/D NMOS reference micro-power consumption property is realized; the reference voltage starting sub-circuit is used as a starting circuit of the E/D NMOS reference source circuit, the current of the E/D NMOS reference source circuit can be determined, the output voltage performance of the E/DNMOS reference source circuit can be adjusted through the reference voltage adjusting sub-circuit, and the value and the temperature characteristic parameters of the E/D NMOS reference source circuit can be adjusted conveniently; the E/DNMOS reference voltage source is simple and reasonable in circuit structure, a triode, a resistor, a capacitor and the like are not needed, the manufacturing process of the E/DNMOS reference voltage source is only based on a silicon gate P well E/D CMOS process, the N-channel junction field effect transistor is additionally manufactured, only the threshold voltage of the N-channel junction field effect transistor needs to be adjusted in the process, the process is greatly simplified, and the cost is reduced.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. An E/D NMOS reference voltage source, comprising:
the pre-reference source circuit comprises an N-channel junction field effect transistor, wherein the grid electrode of the N-channel junction field effect transistor is grounded, the drain electrode of the N-channel junction field effect transistor is connected with power supply voltage, and the source electrode of the N-channel junction field effect transistor outputs pre-reference voltage;
and the E/D NMOS reference source circuit is connected with the pre-reference source circuit, receives the pre-reference voltage and outputs reference voltage to the outside.
2. The E/D NMOS reference voltage source of claim 1, wherein the N-channel JFET comprises a depletion mode N-channel JFET.
3. The E/D NMOS reference voltage source of claim 1 or 2, wherein the E/D NMOS reference source circuit comprises:
the reference voltage starting sub-circuit is connected with the pre-reference source circuit, receives the pre-reference voltage and outputs the reference voltage outwards;
and the reference voltage regulator sub-circuit and the reference voltage starting sub-circuit regulate the reference voltage.
4. The E/D NMOS reference voltage source of claim 3, wherein the reference voltage sub-circuit comprises a plurality of NMOS transistors connected in series, and the reference voltage regulator sub-circuit comprises a plurality of NMOS transistors connected in series.
5. The E/D NMOS reference voltage source of claim 4, wherein the reference voltage promoter circuit comprises: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the first NMOS tube is connected with the source electrode of the N-channel junction field effect tube, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is used as a reference voltage output end; the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected together and connected with the reference voltage output end in parallel; and the substrates of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected together and connected with the reference voltage output end in parallel.
6. The E/D NMOS reference voltage source of claim 5, wherein the first, second, third and fourth NMOS transistors comprise: and a depletion type NMOS tube.
7. The E/D NMOS reference voltage source of claim 6, wherein the reference voltage promoter circuit comprises: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the drain electrode of the fifth NMOS tube is connected with the reference voltage output end, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube, and the source electrode of the eighth NMOS tube is grounded; the grid electrodes of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected together and connected with the reference voltage output end in parallel; and the substrates of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected together and grounded.
8. The E/D NMOS reference voltage source of claim 7, wherein the fifth, sixth, seventh and eighth NMOS transistors comprise: and an enhancement NMOS transistor.
9. A low dropout voltage regulator comprising the E/D NMOS reference voltage source of any one of claims 1-8.
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| CN113031691A (en) * | 2021-03-15 | 2021-06-25 | 江苏硅国微电子有限公司 | Wide-input wide-output depletion tube reference voltage source |
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