CN210864615U - Power supply circuit of tablet computer - Google Patents
Power supply circuit of tablet computer Download PDFInfo
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- CN210864615U CN210864615U CN201922445358.6U CN201922445358U CN210864615U CN 210864615 U CN210864615 U CN 210864615U CN 201922445358 U CN201922445358 U CN 201922445358U CN 210864615 U CN210864615 U CN 210864615U
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Abstract
The utility model relates to a computer motherboard power technical field discloses a power supply circuit of panel computer that level output state conversion is timely, possesses: the controller is configured at the signal output end of the inverter, and the signal input end of the controller is coupled with the signal output end of the inverter and used for receiving the level signal output by the inverter; the base electrode of the first triode is connected with the signal output end of the controller; the base electrode of the second triode is coupled with the signal output end of the inverter; the base electrode of the third triode is coupled with the collector electrode of the second triode, and the first signal input end of the dual-channel MOS tube is connected with the collector electrode of the third triode; the second signal input end of the double-channel MOS tube is coupled to the collector electrode of the first triode; when the screen is switched from sleep to work, the phase inverter outputs high level, and the high level is used for driving the dual-channel MOS tube to be conducted so as to lighten the screen of the tablet computer.
Description
Technical Field
The utility model relates to a computer motherboard power technical field, more specifically say, relate to a power supply circuit of panel computer.
Background
Switching power supply circuits are relatively common power supply circuits in electronic products. In the past, when a switching power supply provides a working power supply for a tablet personal computer, the switching power supply is easily influenced by the fluctuation voltage of a power grid, so that the output voltage of the switching power supply is unstable.
Therefore, a switching power supply circuit with stable output voltage and small influence of fluctuation voltage is provided in the prior art, and the problem of unstable output voltage caused by power grid fluctuation is effectively solved. However, when the sleep state of the tablet computer is changed to normal operation, the switching between the output levels of the switching power supply circuit in the prior art is delayed, so that the user experience is poor.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, when operating condition changes to the above-mentioned panel computer of prior art, the delayed defect of conversion between the level provides the timely panel computer's of level output state conversion power supply circuit.
The utility model provides a technical scheme that its technical problem adopted is: a power supply circuit for a tablet computer is configured to include:
a controller configured at a signal output end of the inverter, a signal input end of the controller being coupled to the signal output end of the inverter for receiving the level signal output by the inverter;
the base electrode of the first triode is connected with the signal output end of the controller;
a base of the second triode is coupled to the signal output end of the inverter;
a third transistor having a base coupled to a collector of the second transistor,
a first signal input end of the double-channel MOS tube is connected with a collector electrode of the third triode;
the second signal input end of the double-channel MOS tube is coupled to the collector electrode of the first triode;
when the screen is switched from sleep to work, the phase inverter outputs a high level, and the high level is used for driving the two-channel MOS tube to be conducted so as to lighten the screen of the tablet computer.
In some embodiments, the transistor further comprises a first resistor and a second resistor, one end of the first resistor is connected to the signal output terminal of the controller, the other end of the first resistor is coupled to the base of the first transistor,
one end of the second resistor is connected with the collector of the first triode;
the other end of the second resistor is coupled to an auxiliary power supply end of the controller.
In some embodiments, the transistor further comprises a fourth resistor and a fifth resistor, one end of the fourth resistor is connected to the signal output terminal of the inverter, the other end of the fourth resistor is coupled to the base of the second transistor,
one end of the fifth resistor is respectively connected with the collector of the second triode and the base of the third triode;
the other end of the fifth resistor is coupled to an auxiliary power supply terminal of the controller.
In some embodiments, the controller further comprises a second controller, wherein a signal input end of the second controller is connected with a high level;
the signal output end of the second controller is coupled to the signal input end of the south bridge chip and provides a working power supply for the south bridge chip.
In some embodiments, the device further comprises a first capacitor, a second capacitor and a third capacitor,
the first capacitor, the second capacitor and the third capacitor are connected in parallel,
one end of the first capacitor, one end of the second capacitor and one end of the third capacitor are respectively connected with the signal input end of the second controller.
In some embodiments, further comprises a seventh resistor and an eighth resistor,
the seventh resistor and the eighth resistor are connected in series,
one end of the seventh resistor is connected with the signal output end of the second controller,
one end of the eighth resistor and the other end of the seventh resistor are respectively connected with the adjusting end of the second controller.
In the power circuit of the tablet computer of the present invention, the power circuit includes a controller disposed at the signal output end of the phase inverter, and the signal input end of the controller is coupled to the signal output end of the phase inverter and is configured to receive the level signal output by the phase inverter; the first signal input end of the double-channel MOS tube is connected with the collector electrode of the third triode; the second signal input end of the double-channel MOS tube is coupled to the collector electrode of the first triode; when the screen is switched from sleep to work, the phase inverter outputs high level, and the high level is used for driving the dual-channel MOS tube to be conducted so as to lighten the screen of the tablet computer. Compared with the prior art, the level signal (high level or low level) input by the phase inverter enables the level signal to be timely converted when the screen of the tablet computer is converted into normal work in the sleep state, and the experience of a user can be effectively improved.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a partial driving circuit diagram of an embodiment of a power circuit of a tablet computer;
fig. 2 is a partial power circuit diagram of another embodiment of the power circuit of the tablet computer according to the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a partial driving circuit diagram of an embodiment of a power circuit of a tablet computer; fig. 2 is a partial power circuit diagram of another embodiment of the power circuit of the tablet computer according to the present invention. As shown in fig. 1 and fig. 2, in the first embodiment of the power circuit of the tablet computer of the present invention, the power circuit of the tablet computer only includes the phase inverter a1, the controller U1, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the dual-channel MOS transistor (VT1, VT 2).
The inverter a1 is a basic unit of a logic circuit, and when an input terminal thereof is at a high level (logic 1), an output terminal thereof is at a low level (logic 0); when its input terminal is low, the output terminal is high, that is, the level states of the input terminal and the output terminal are always inverted.
The controller U1 is used for receiving the level signal inputted from the inverter a1, and has the functions of logic operation and controlling the output signal (current signal or voltage signal).
The controller U1 has a NOT gate signal input terminal (corresponding to ATXPWROK #), a south bridge chip signal terminal (corresponding to SLP _ S4#), a signal output terminal (corresponding to OUT) and an auxiliary power supply terminal (corresponding to PWR).
The triode has the function of a switch.
The dual-channel MOS tubes (VT1, VT2) have the functions of signal conversion and circuit on-off control.
Specifically, the controller U1 is disposed at the signal output terminal (corresponding to terminal F) of the inverter a 1.
One signal input terminal (corresponding to terminal a) of the controller U1 is coupled to the signal output terminal of the inverter a1, and the other signal input terminal (corresponding to terminal B) of the controller U1 is connected to the signal output terminal (SLP-S4#) of the south bridge chip IC, and is configured to receive the level signals (i.e., high level or low level) output by the inverter a1 and the south bridge chip IC and output the level signals to the first transistor Q1.
The base of the first transistor Q1 is connected to the signal output terminal OUT of the controller U1, which is used for receiving the level signal output by the controller U1.
The base of the second transistor Q2 is coupled to the signal output terminal (corresponding to the ATXPWROK terminal) of the inverter a1, and is configured to receive the level signal output by the inverter a 1.
The base of the third transistor Q3 is coupled to the collector of the second transistor Q2, and the collector of the third transistor Q3 is connected to the 12V terminal.
The first signal input ends (corresponding to 2 pins) of the dual-channel MOS tubes (VT1 and VT2) are connected with the collector of the third triode Q3.
The second signal input terminals (corresponding to 4 pins) of the dual-channel MOS transistors (VT1, VT2) are coupled to the collector of the first transistor Q1.
The emitters of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are connected to a common terminal, respectively.
When the screen of the tablet computer is switched from sleep to work, the inverter A1 outputs high level to drive the dual-channel MOS tube (VT1, VT2) to conduct the high level so as to lighten the screen of the tablet computer, and the tablet computer is switched to work in time.
Specifically, the ATXPWROK # signal in the circuit is ATXPWROK converted by the NOT gate circuit (i.e., inverter A1) to a level opposite to that of ATXPWROK.
The working principle is as follows: when the tablet personal computer is in a sleep state, ATXPWROK is at a low level, no +12V voltage is input into the collector of the third triode Q3, the first signal input end (corresponding to 2 pins) of the input dual-channel MOS transistor (VT1, VT2) is at a low level, and an N-type channel in the dual-channel MOS transistor (VT1, VT2) is cut off.
At this moment, ATXPWROK # is the high level, and SLP _ S4# that south bridge chip IC sent is the high level simultaneously, and controller U1 exports the high level signal, and control first triode Q1 switches on, exports the low level, and the P type passageway on the second signal input part (corresponding 4 feet) of dual-channel MOS pipe (VT1, VT2) switches on. At this time, pin 5 and pin 6 of the dual channel MOS transistor (VT2) output the 5V-USB converted from 5 VSB.
I.e. the screen can be lit up by means of a mouse or keyboard.
When the dual-channel MOS transistor works normally, the ATXPWROK is at a high level, the second triode Q2 is switched on, the third triode Q3 is switched off, and the +12V is added to the first signal input end (corresponding to 2 pins) of the dual-channel MOS transistor (VT1 and VT2) through the sixth resistor R6, namely, the control pin of the N-type channel of the dual-channel MOS transistor is at the high level, and the channel is switched on.
At this time, the VCC voltage is output from pin 7 and pin 8 of the dual-channel MOS transistor (VT2) as 5V-USB voltage through the N-type MOS transistor. Meanwhile, if ATXPWROK is at a high level and ATXPWROK # is at a low level, the controller U1 outputs a low level, the first triode Q1 is turned off, and a high-level control signal is output to the second signal input end (corresponding to 4 pins) of the dual-channel MOS transistor (VT1, VT2), that is, the P-type channel of the dual-channel MOS transistor is turned off. At this time, there is no current output to pins 5 and 6 of the dual channel MOS transistor (VT2), i.e., 5VSB is not supplied with voltage of 5V-USB.
In some embodiments, a first resistor R1 and a second resistor R2 may be disposed in the circuit to improve the stability of the circuit. The first resistor R1 and the second resistor R2 have a current limiting function.
Specifically, one end of the first resistor R1 is connected to a signal output end of the controller U1, the other end of the first resistor R1 is coupled to a base of the first transistor Q1, and a level signal output by the controller U1 is input to the first transistor Q1 through the first resistor R1 to control the first transistor Q1 to be turned on or off.
One end of the second resistor R2 is connected to the collector of the first transistor Q1, and the other end of the second resistor R2 is coupled to an auxiliary power source terminal (corresponding to the 5VSB terminal) of the controller U1.
That is, when the controller U1 outputs a high level, the first transistor Q1 is turned on, and at this time, the voltage output from the auxiliary power source terminal (corresponding to the 5VSB terminal) of the controller U1 can be input to the second signal input terminal (corresponding to the 4 pins) of the dual-channel MOS transistor (VT1, VT2) through the second resistor R2.
In some embodiments, a fourth resistor R4 and a fifth resistor R5 may be provided in the circuit to improve the stability of the circuit. Specifically, one end of the fourth resistor R4 is connected to the signal output terminal (corresponding to terminal F) of the inverter a1, and the other end of the fourth resistor R4 is coupled to the base of the second transistor Q2.
That is, the level signal inverted and outputted by the inverter a1 is inputted to the second transistor Q2 through the fourth resistor R4 to control the second transistor Q2 to be turned on or off.
Further, one end of the fifth resistor R5 is connected to the collector of the second transistor Q2 and the base of the third transistor Q3, respectively, and the other end of the fifth resistor R5 is coupled to an auxiliary power source terminal of the controller U1.
In some embodiments, in order to ensure the stability of the output voltage of the power circuit, a second controller U2 may be disposed in the circuit, wherein the second controller U2 provides a stable operating voltage for the south bridge chip IC and the north bridge chip.
Specifically, the signal input terminal (corresponding to the Vin terminal) of the second controller U2 is connected to the high level (i.e., VCC terminal), and the signal output terminal (corresponding to the Vout terminal) of the second controller U2 and the signal input terminal of the south bridge chip IC provide the working power supply of 1.5V for the south bridge chip IC.
In some embodiments, the capacitor further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3, wherein the first capacitor C1, the second capacitor C2, and the third capacitor C3 have a filtering function.
Specifically, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in parallel, and one end of the first capacitor C1, one end of the second capacitor C2 and one end of the third capacitor C3 are respectively connected to a signal input end of the second controller U2.
After the input voltage is filtered by the capacitor, the impurities of the power supply can be effectively reduced, and the quality of the output power supply is further improved.
In some embodiments, the electronic device further includes a seventh resistor R7 and an eighth resistor R8, the seventh resistor R7 and the eighth resistor R8 are connected in series, one end of the seventh resistor R7 is connected to the signal output terminal of the second controller U2, and the other end of the seventh resistor R7 and one end of the eighth resistor R8 are respectively connected to the adjustment terminal (i.e., the ADJ terminal) of the second controller U2.
Through the circuit, the input VCC power supply is regulated and converted into 1.5V voltage so as to meet the standard working voltage of other parts (extended AGP bus and I/O chip) of the internal circuit of the mainboard.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (6)
1. A power supply circuit of a tablet computer is characterized by comprising:
a controller configured at a signal output end of the inverter, a signal input end of the controller being coupled to the signal output end of the inverter for receiving the level signal output by the inverter;
the base electrode of the first triode is connected with the signal output end of the controller;
a base of the second triode is coupled to the signal output end of the inverter;
a third transistor having a base coupled to a collector of the second transistor,
a first signal input end of the double-channel MOS tube is connected with a collector electrode of the third triode;
the second signal input end of the double-channel MOS tube is coupled to the collector electrode of the first triode;
when the screen is switched from sleep to work, the phase inverter outputs a high level, and the high level is used for driving the two-channel MOS tube to be conducted so as to lighten the screen of the tablet computer.
2. The power circuit of a tablet computer according to claim 1,
the circuit also comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the signal output end of the controller, the other end of the first resistor is coupled with the base electrode of the first triode,
one end of the second resistor is connected with the collector of the first triode;
the other end of the second resistor is coupled to an auxiliary power supply end of the controller.
3. The power circuit of a tablet computer according to claim 2,
the inverter further comprises a fourth resistor and a fifth resistor, wherein one end of the fourth resistor is connected with the signal output end of the inverter, the other end of the fourth resistor is coupled to the base electrode of the second triode,
one end of the fifth resistor is respectively connected with the collector of the second triode and the base of the third triode;
the other end of the fifth resistor is coupled to an auxiliary power supply terminal of the controller.
4. The power circuit of a tablet computer according to claim 1,
the signal input end of the second controller is connected with a high level;
the signal output end of the second controller is coupled to the signal input end of the south bridge chip and provides a working power supply for the south bridge chip.
5. The power circuit of a tablet computer according to claim 4,
also includes a first capacitor, a second capacitor and a third capacitor,
the first capacitor, the second capacitor and the third capacitor are connected in parallel,
one end of the first capacitor, one end of the second capacitor and one end of the third capacitor are respectively connected with the signal input end of the second controller.
6. The power circuit of a tablet computer according to claim 5,
also comprises a seventh resistor and an eighth resistor,
the seventh resistor and the eighth resistor are connected in series,
one end of the seventh resistor is connected with the signal output end of the second controller,
one end of the eighth resistor and the other end of the seventh resistor are respectively connected with the adjusting end of the second controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922445358.6U CN210864615U (en) | 2019-12-26 | 2019-12-26 | Power supply circuit of tablet computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922445358.6U CN210864615U (en) | 2019-12-26 | 2019-12-26 | Power supply circuit of tablet computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210864615U true CN210864615U (en) | 2020-06-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922445358.6U Active CN210864615U (en) | 2019-12-26 | 2019-12-26 | Power supply circuit of tablet computer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210864615U (en) |
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2019
- 2019-12-26 CN CN201922445358.6U patent/CN210864615U/en active Active
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