CN210835772U

CN210835772U - High-precision oscillator circuit

Info

Publication number: CN210835772U
Application number: CN201921974667.6U
Authority: CN
Inventors: 孙志亮; 霍俊杰; 朱永成
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-06-23
Anticipated expiration: 2029-11-18

Abstract

The utility model provides a high-precision oscillator circuit, which comprises a temperature compensation circuit and a clock generation circuit; the temperature compensation circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first band gap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; the clock generation circuit comprises a first comparator, a second comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate; the utility model introduces the first comparator and the second comparator into the high-precision oscillator circuit, thus reducing the change of the output frequency caused by the temperature change; overall, simple structure, easily integrated, output voltage is stable.

Description

High-precision oscillator circuit

Technical Field

The utility model relates to an integrated circuit technical field in the SIM card technique especially relates to high accuracy oscillator circuit.

Background

The utility model relates to an integrated circuit technical field in the SIM technique, wherein the stability of oscillator output clock is more and more important to the stability of system work, and its performance direct relation is to the SIM card and can normally work.

With the application of the existing high-capacity and high-security SIM card, the requirements of the system on the speed and the stability of the clock are higher and higher, the oscillator is generally divided into a quartz crystal oscillator, an LC oscillator, an RC oscillator and the like, and the RC oscillator is widely applied to the field of integrated circuits due to the advantages of simple structure, easiness in oscillation, small area, low power consumption, easiness in integration and the like, but the output frequency of the RC oscillator is easily affected by temperature and process deviation, and the accuracy is poor. Therefore, the design and research of the high-precision and low-cost RC oscillator circuit have very important significance.

Referring to fig. 1, a conventional RC oscillator circuit structure is shown, and the operation principle is as follows: in the circuit structure of the RC oscillator, the RC oscillator is a ring oscillator, assuming that a node N3 is subjected to a small interference, a positive transition is generated, and after passing through a delay T of a first inverter INV1 and a second capacitor C2, the RC oscillator is amplified into a larger negative transition signal N1, and after passing through a delay T of a second inverter INV2 and a third capacitor C3, the RC oscillator continues to be amplified into a larger positive transition signal N2, and after passing through a delay T of a third inverter INV3 and a first capacitor C1, the RC oscillator continues to be amplified into a larger negative transition signal N3, and after passing through 3T, the N3 signal becomes a positive transition again, forming a positive feedback and a positive feedback, generating a self-excited oscillation, and the period being 6T.

The RC oscillator circuit described above, however, has some disadvantages: firstly, the capacitor in the circuit and the devices in the inverter are easily affected by process deviation and temperature, so that the frequency of an output clock is unstable; furthermore, IREF is typically generated from a bandgap reference voltage and is easily affected by temperature and process variations, causing output clock frequency instability.

SUMMERY OF THE UTILITY MODEL

To the not enough of existence among the above-mentioned prior art, the utility model aims at providing a high accuracy oscillator circuit, including temperature compensation circuit and clock generation circuit, have easily integrated, output voltage is stable characteristics.

In order to achieve the technical purpose, the utility model discloses the technical scheme who adopts is:

a high precision oscillator circuit, the oscillator circuit comprising a temperature compensation circuit and a clock generation circuit; the temperature compensation circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first band gap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; one end of a second resistor is connected with one end of a first resistor, the other end of the first resistor and the drain end of a fifth PMOS transistor are connected with the negative input end of a first amplifier, the grid end of the fifth PMOS transistor and the grid end of a third PMOS transistor are connected with the grid end of a fourth PMOS transistor, the source end and the substrate of the fifth PMOS transistor, the source end and the substrate of the third PMOS transistor, the source end and the substrate of the fourth PMOS transistor, the substrate of the first PMOS transistor, the substrate of a second NMOS transistor and the power supply end of the first amplifier are connected with a power supply end VDD, the positive input end of the first amplifier is connected with a band-gap reference voltage source VREF, the drain end of the third PMOS transistor is connected with the source end of the first PMOS transistor, the drain end of the fourth PMOS transistor is connected with the source end of a second NMOS transistor, the grid end of the first PMOS transistor is connected with the grid end of the first NMOS transistor, the drain terminal of the first PMOS transistor and one end of the first capacitor are connected with the drain terminal of the first NMOS transistor and are used as first output ends, the drain terminal of the second PMOS transistor and one end of the second capacitor are connected with the drain terminal of the second NMOS transistor and are used as second output ends, the other end of the second resistor, the other end of the first capacitor, the other end of the second capacitor, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the second NMOS transistor, and the ground terminal of the first amplifier is connected with a ground terminal VSS;

the clock generation circuit comprises a first comparator, a second comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate; the positive input end of the first comparator and the positive input end of the second comparator are connected with a band-gap reference voltage VREF, the negative input end of the first comparator is connected with the second output end of the temperature compensation circuit, the negative input end of the second comparator is connected with the first output end of the temperature compensation circuit, the output end of the first comparator is connected with the input end of the first reverser, the output end of the second comparator is connected with the input end of the second reverser, the output end of the first reverser is connected with one input end of the first AND-gate, the output end of the second reverser is connected with one input end of the second AND-gate, the other input end of the first AND-gate and the output end of the second AND-gate are connected with one input end of the third AND-gate, the other input end of the second AND-gate and the output end of the first AND-gate are connected with one input end of the fourth AND-gate, the other input end of the third AND, The output end of a fourth AND-gate is connected with the input end of a fourth inverter, the other input end of the fourth AND-gate, the output end of the third AND-gate and the input end of a third inverter are connected, the output end of the third inverter is used as the first input end, the output end of the fourth inverter is used as the second input end, the power supply end of the first comparator, the power supply end of the second comparator, the power supply end of the first inverter, the power supply end of the second inverter, the power supply end of the fourth inverter, the power supply end of the first AND-gate, the power supply end of the second AND-gate, the power supply end of the fourth AND-gate and the power supply end are connected, the ground end of the first comparator, the ground end of the second comparator, the ground end of the first inverter, the ground end of the second inverter, the ground end of the third inverter, the ground end of the fourth inverter, the ground end of the first AND-gate, the ground end of the second inverter, the ground end of the, And the ground end of the second AND gate, the ground end of the third AND gate and the ground end of the fourth AND gate are connected with a ground terminal VSS.

The utility model discloses owing to adopted foretell structure, compare with current technical scheme, have following advantage:

first, IN the high-precision oscillator circuit of the present invention, a first resistor and a second resistor are introduced, the first resistor has a positive temperature characteristic, and the second resistor has a negative temperature characteristic, so that the current flowing through the fifth PMOS transistor connected to the first resistor has a certain temperature coefficient, and at the same time, the current flowing through the third PMOS transistor also has the same temperature coefficient, thereby compensating for the change of the first IN1 and the second IN2 at the output end due to the temperature change;

secondly, in the high-precision oscillator circuit of the utility model, a first comparator and a second comparator are introduced, so as to reduce the change of the output frequency caused by the temperature change;

moreover, in the high-precision oscillator circuit of the present invention, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, AND a fourth AND gate 4 are introduced, so that the duty ratio of the output clock is about 50%;

finally, the utility model discloses a high accuracy oscillator circuit, generally, simple structure, easily integration, output voltage is stable.

The present invention will be further described with reference to the accompanying drawings and the following detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a conventional RC oscillator circuit configuration;

fig. 2 shows a high-precision oscillator circuit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 2, a high-precision oscillator circuit according to an embodiment of the present invention is shown. The high-precision oscillator circuit of this embodiment includes a temperature compensation circuit 101 and a clock generation circuit 102.

In the high-precision oscillator circuit, the temperature compensation circuit 101 includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first amplifier AMP1, a first bandgap reference voltage source VREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM 5; one end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 and the drain of the fifth PMOS transistor PM5 are connected to the negative input terminal of the first amplifier AMP1, the gate of the fifth PMOS transistor PM5 and the gate of the third PMOS transistor PM3 are connected to the gate of the fourth PMOS transistor PM4, the source and the substrate of the fifth PMOS transistor PM5, the source and the substrate of the third PMOS transistor PM3, the source and the substrate of the fourth PMOS transistor PM4, the substrate of the first PMOS transistor PM1, the substrate of the second NMOS transistor NM2, the source of the first amplifier AMP1 is connected to the power supply terminal VDD, the positive input terminal of the first amplifier AMP1 is connected to the bandgap reference voltage source VREF, the drain of the third PMOS transistor PM3 is connected to the drain of the first PMOS transistor PM1, the drain of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2, the drain of the first PMOS transistor PM1 is connected to the NMOS transistor PM1, and serves as a first input terminal VOUT1, a gate terminal of the second PMOS transistor PM2 is connected to a gate terminal of the second NMOS transistor NM2 and serves as a second input terminal VOUT2, a drain terminal of the first PMOS transistor PM1 and one terminal of the first capacitor C1 are connected to a drain terminal of the first NMOS transistor NM1 and serve as a first output terminal IN1, a drain terminal of the second PMOS transistor PM2 and one terminal of the second capacitor C2 are connected to a drain terminal of the second NMOS transistor NM2 and serve as a second output terminal IN2, the other terminal of the second resistor R2, the other terminal of the first capacitor C1, the other terminal of the second capacitor C2, the source terminal and substrate of the first NMOS transistor NM1, the source terminal and substrate of the second NMOS transistor NM2, and the ground terminal of the first amplifier AMP1 is connected to the ground terminal VSS.

In the high-precision oscillator circuit, the clock generation circuit 102 includes a first comparator COM1, a second comparator COM2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, AND a fourth AND gate AND 4; a positive input terminal of the first comparator COM1, a positive input terminal of the second comparator COM2 are connected to the bandgap reference voltage VREF, a negative input terminal of the first comparator COM1 is connected to a second output terminal IN2 of the temperature compensation circuit, a negative input terminal of the second comparator COM2 is connected to a first output terminal IN1 of the temperature compensation circuit, an output terminal of the first comparator COM1 is connected to an input terminal of a first inverter INV1, an output terminal of the second comparator COM2 is connected to an input terminal of a second inverter INV2, an output terminal of the first inverter INV1 is connected to an input terminal of a first AND gate AND1, an output terminal of the second inverter INV2 is connected to an input terminal of a second AND gate AND2, another input terminal of the first AND gate AND1, an output terminal of the second AND gate AND2 is connected to an input terminal of a third AND gate AND3, another input terminal of the second AND gate 2, an output terminal of the first AND gate 1 is connected to a first AND gate 4 of a fourth AND gate. The other input terminal of the third AND-gate AND3, the output terminal of the fourth AND-gate AND4 AND the input terminal of the fourth inverter INV4 are connected, the other input terminal of the fourth AND-gate AND4, the output terminal of the third AND-gate AND3 AND the input terminal of the third inverter INV3 are connected, the output terminal of the third inverter INV3 is used as the first input terminal VOUT1, the output terminal of the fourth inverter INV4 is used as the second input terminal VOUT2, the power terminal of the first comparator COM1, the power terminal of the second comparator COM2, the power terminal of the first inverter INV1, the power terminal of the second inverter INV2, the power terminal of the third inverter INV3, the power terminal of the fourth inverter INV4, the power terminal of the first AND-gate AND1, the power terminal of the second AND-gate 2, the power terminal of the third AND-gate AND3, the power terminal of the fourth AND-gate 4 AND VDD, the ground terminal of the first comparator COM2, the ground terminal of the second comparator COM1, the first inverter COM-gate AND 639, the ground terminal of the second inverter INV 9 AND-gate AND 686, The ground end of the second inverter INV2, the ground end of the third inverter INV3, the ground end of the fourth inverter INV4, the ground end of the first AND gate AND1, the ground end of the second AND gate AND2, the ground end of the third AND gate AND3, AND the ground end of the fourth AND gate AND4 are connected to the ground end VSS.

Referring to fig. 2, when the high-precision oscillator circuit operates, the bandgap reference voltage VREF IN the temperature compensation circuit is a temperature-independent reference voltage, the first resistor R1 has a positive temperature characteristic, the second resistor R2 has a negative temperature characteristic, so that the current flowing through the fifth PMOS transistor PM5 has a certain temperature coefficient, and meanwhile, the current flowing through the third PMOS transistor PM3 and the current flowing through the fifth PMOS transistor PM5 have the same temperature coefficient, so as to compensate for the change of the rising edge of the first output terminal IN1 and the second output terminal IN2 due to the temperature change, and the falling edge is relatively fast due to the strong pull-down of the first NMOS transistor NM1 and the second NMOS transistor NM2, so that the temperature change of the falling edge is relatively small.

The first output terminal IN1 and the second output terminal IN2 IN the temperature compensation circuit generate the rising edge of the high-precision oscillator circuit through the comparison of the first comparator COM1 and the second comparator COM2 with the bandgap reference voltage VREF IN the temperature compensation circuit, and the rising edge voltage of the first output terminal IN1 and the second output terminal IN2 IN the temperature compensation circuit is slightly influenced by temperature, so the rising edge of the output clock of the high-precision oscillator circuit is slightly influenced by temperature; the falling edges of the first output terminal IN1 and the second output terminal IN2 IN the temperature compensation circuit are relatively fast and are less affected by temperature, so that the falling edge of the output clock of the high-precision oscillator circuit is also less affected by temperature.

Because the duty ratio of the clock generated by the first comparator COM1 AND the second comparator COM2 can be less than or greater than 50%, which is not beneficial to the system use, the clock generated by the first comparator COM1 AND the second comparator COM2 is shaped into a clock with a duty ratio of about 50% by forming a two-stage RS flip-flop with the first AND gate AND1, the second AND gate AND2, the third AND gate AND3 AND the fourth AND gate AND4 in the clock generation circuit, so as to be beneficial to the system use.

As can be seen from the above, the embodiment of the present invention effectively improves the stability of the output clock of the oscillator circuit through the phase compensation circuit 101 and the clock generation circuit 102.

The basic idea of the present invention is described in the above embodiments only by way of illustration, and the constituent circuits related to the present invention are not drawn in accordance with the number, shape, arrangement of devices, and connection manner of the constituent circuits in actual implementation. The actual implementation of the method can be changed freely according to the type, number, connection mode, device arrangement mode and device parameters of each circuit.

The above-mentioned embodiments are only preferred embodiments of the present invention, and the extension of the technical solution of the present invention is not limited. Any modification, equivalent change, obvious change and the like of the known technology made by the technical proposal of the invention by the technical personnel in the field shall fall within the protection scope of the invention.

Claims

1. A high precision oscillator circuit, wherein the oscillator circuit comprises a temperature compensation circuit and a clock generation circuit; wherein,

the temperature compensation circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first band gap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; one end of a second resistor is connected with one end of a first resistor, the other end of the first resistor and the drain end of a fifth PMOS transistor are connected with the negative input end of a first amplifier, the grid end of the fifth PMOS transistor and the grid end of a third PMOS transistor are connected with the grid end of a fourth PMOS transistor, the source end and the substrate of the fifth PMOS transistor, the source end and the substrate of the third PMOS transistor, the source end and the substrate of the fourth PMOS transistor, the substrate of the first PMOS transistor, the substrate of a second NMOS transistor and the power supply end of the first amplifier are connected with a power supply end VDD, the positive input end of the first amplifier is connected with a band-gap reference voltage source VREF, the drain end of the third PMOS transistor is connected with the source end of the first PMOS transistor, the drain end of the fourth PMOS transistor is connected with the source end of a second NMOS transistor, the grid end of the first PMOS transistor is connected with the grid end of the first NMOS transistor, the drain terminal of the first PMOS transistor and one end of the first capacitor are connected with the drain terminal of the first NMOS transistor and are used as first output ends, the drain terminal of the second PMOS transistor and one end of the second capacitor are connected with the drain terminal of the second NMOS transistor and are used as second output ends, the other end of the second resistor, the other end of the first capacitor, the other end of the second capacitor, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the second NMOS transistor, and the ground terminal of the first amplifier is connected with a ground terminal VSS;