CN210835692U

CN210835692U - High-reliability remote data transmission system based on LVDS

Info

Publication number: CN210835692U
Application number: CN202020012023.5U
Authority: CN
Inventors: 李晓庆
Original assignee: Guangzhou Youmi Network Technology Co ltd
Current assignee: Guangzhou Youmi Network Technology Co ltd
Priority date: 2020-01-04
Filing date: 2020-01-04
Publication date: 2020-06-23
Anticipated expiration: 2030-01-04

Abstract

The utility model discloses a remote data transmission system of high reliability based on LVDS contains data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, and wherein, the data acquisition encoder for gather high-speed analog signal, ground test platform for receive the instruction that the host computer was issued and forward the data acquisition encoder and receive the data of data acquisition encoder passback. The utility model discloses the high-speed analog signal of data acquisition encoder collection, the data that ground test board received the instruction that the host computer was issued and was forwarded the data acquisition encoder and received the data acquisition encoder passback, adopt 4 sections 60m, totally 240 m's balanced twisted pair wire connects data acquisition encoder and ground test board, the data acquisition encoder sends LVDS data with 500 Mb/s's code rate to ground test board, data are handled fast to the high efficiency more, data transmission's reliability is improved.

Description

High-reliability remote data transmission system based on LVDS

Technical Field

The utility model relates to a data transmission technical field, more specifically say, the utility model relates to a remote data transmission system of high reliability based on LVDS.

Background

In a certain remote test task, a data acquisition encoder is required to acquire multi-path high-speed analog quantity signals and return the signals to a ground test bench in real time for data detection and processing. Based on the fact that the environment of a cable network used in the task is severe and the surrounding electromagnetic interference is large, for traditional parallel line transmission, although the transmission rate can meet the task requirement, the data quality is seriously reduced under the conditions of high transmission rate and severe environment due to the fact that more interface data lines are needed; the PECL rate, while also meeting the task requirements, is not compatible with standard logic at its interface level; and the data transmission rates of the RS422 and the RS485 can obviously not meet the task requirement, so that the LVDS technology is selected as the solution of the design.

SUMMERY OF THE UTILITY MODEL

In order to overcome prior art's above-mentioned defect, the utility model discloses the problem that the reliability is low in high-speed remote transmission in-process to data provides a high reliability remote data transmission system based on LVDS, and high efficiency is handled data fast, improves data transmission's reliability.

In order to achieve the above object, the utility model provides a following technical scheme:

the utility model provides a high reliability remote data transmission system based on LVDS, contains data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, wherein, the data acquisition encoder for gather high-speed analog signal, ground test platform is used for receiving the instruction of host computer issuing and forwarding to the data acquisition encoder and receive the data of data acquisition encoder passback.

As a further preferred scheme of the remote data transmission system of high reliability based on LVDS, the data acquisition encoder contains high-speed data acquisition module, first FPGA module, driver module, LVDS encoder, 485 receiver, the input of first FPGA module is connected to the output of fast data acquisition module, the input of driver module is connected to the output of first FPGA module, the input of LVDS encoder is connected to the output of driver module, the input of first FPGA module is connected to the output of 485 receiver.

As the utility model relates to a remote data transmission system's of high reliability further preferred scheme based on LVDS, ground test platform contains balanced device, LVDS decoder, second FPGA module, PCI9051 module, 485 and sends the ware, the input of LVDS encoder is connected to the output balanced device's of LVDS encoder input, the output of balanced device, second FPGA module input is connected to the output of LVDS encoder, the second FPGA module passes through PCI9051 modular connection host computer, the input that 485 sent the ware is connected to the output of second FPGA module, the input of 485 receiver is connected to the output that 485 sent the ware.

As a further preferred aspect of the high reliability remote data transmission system based on LVDS, the chip model of VDS encoder is GM 8223.

As a further preferable aspect of the present invention, the high-reliability remote data transmission system based on LVDS, the chip model of the LVDS decoder is GM 8224.

As a further preferred aspect of the high reliability remote data transmission system based on LVDS, the chip model of the equalizer is LMH 0044.

The utility model discloses a technological effect and advantage:

1. the utility model discloses the data acquisition encoder gathers high-speed analog quantity signal, and the ground test board receives the instruction that the host computer was issued and forwards to the data acquisition encoder and receive the data of data acquisition encoder passback, adopts 4 sections 60m, totally 240 m's balanced twisted pair wire connects data acquisition encoder and ground test board, and the data acquisition encoder sends LVDS data to the ground test board with 500 Mb/s of code rate, handles data more high-efficiently fast, improves data transmission's reliability;

2. the utility model discloses to the problem that data is low in high-speed remote transmission in-process reliability, adopted the signal conditioning technique on hardware circuit, carry out the equilibrium and aggravate the processing in advance (going) to the LVDS signal, added a novel 8B 10B codec's optimization mode, greatly strengthened the reliability of transmission link, LVDS data can realize no error code transmission with 500 Mb/s transmission rate on 240 m's balanced twisted pair wire.

Drawings

FIG. 1 is a schematic diagram of the overall structure of the present invention;

FIG. 2 is a schematic diagram of the data acquisition encoder of the present invention;

fig. 3 is a schematic structural diagram of the ground test bench of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The utility model provides a remote data transmission system of high reliability based on LVDS, as shown in FIG. 1, contain data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, and wherein, the data acquisition encoder for gather high-speed analog quantity signal, ground test platform for receive the instruction that the host computer was issued and forward to the data acquisition encoder and receive the data of data acquisition encoder passback. The utility model discloses a 4 sections 60m, total 240 m's balanced twisted pair wire connects data acquisition encoder and ground test board, and the data acquisition encoder sends LVDS data with 500 Mb/s' code rate to ground test board, verifies the feasibility and the reliability of this scheme through the correctness of the data of testboard readback.

Aiming at the problem of low reliability of data in the process of high-speed long-distance transmission, a signal conditioning technology is adopted on a hardware circuit to carry out equalization and pre (de) emphasis processing on LVDS signals, a novel optimization mode of 8B/10B coding and decoding is added, the reliability of a transmission link is greatly enhanced, and the LVDS data can be transmitted without error on a balanced twisted pair wire of 240m at the transmission rate of 500 Mb/s.

As shown in fig. 2, the data acquisition encoder includes a high-speed data acquisition module, a first FPGA module, a driver module, an LVDS encoder, and a 485 receiver, wherein an output end of the high-speed data acquisition module is connected to an input end of the first FPGA module, an output end of the first FPGA module is connected to an input end of the driver module, an output end of the driver module is connected to an input end of the LVDS encoder, and an output end of the 485 receiver is connected to an input end of the first FPGA module.

As shown in fig. 3, the ground test platform includes an equalizer, an LVDS decoder, a second FPGA module, a PCI9051 module, and a 485 transmitter, wherein an output end of the LVDS encoder is connected to an input end of the equalizer, an output end of the equalizer is connected to an input end of the LVDS encoder, an output end of the LVDS encoder is connected to an input end of the second FPGA module, the second FPGA module is connected to an upper computer through the PCI9051 module, an output end of the second FPGA module is connected to an input end of the 485 transmitter, and an output end of the 485 transmitter is connected to an input end of the.

In order to actively respond to the demand of imported electronic components localization, support the development of "chinese core" engineering, avoid appearing imported electronic components simultaneously because shut down, forbidden shelves problem and the safety problem that inserts wooden horse etc. to the chip, the utility model discloses use the LVDS serializer and deserializer of import in having given up traditional design, through the LVDS interface product of the internal chip firm of contrast, selected and accorded with the utility model discloses the required LVDS encoder GM8223 and LVDS decoder GM8224 that become all the core that shakes.

Due to the skin effect and the dielectric loss, the high-speed LVDS signals are attenuated in cable transmission, and the signal attenuation caused by the high-speed LVDS signals is respectively proportional to the square root of the transmission frequency and the transmission rate, and especially in the process of high-speed long-distance transmission, the attenuation in cable transmission is the main reason for signal instability. In order to ensure the transmission quality of data, the design adopts a signal conditioning technology aiming at a transmission rate of 500 Mb/s and a long distance of 240m, and the design requirement is met by equalizing and pre (de) emphasizing the signal. This section employs a serial digital cable driver LMH0002 and an adaptive cable equalizer LMH0044 by the company TI, usa.

The GM8223 encoder receives a 10-bit parallel TTL data signal and a path of TTL clock signal from the FPGA, converts the TTL data signal into 1 pair of LVDS serial data signals and outputs the LVDS serial data signals to a serial digital cable driver LMH0002, and the serial transmission rate of the GM8223 is 100 Mb/s-660 Mb/s.

The data transmission rate of the LMH0002 driver can reach 1.485 Gb/s, and the differential voltage output by the GM8223 can be increased, so that the transmission distance of data on a transmission line is effectively increased. The signal is output by the output end of the LMH0002 and then transmitted to the receiving end of the LMH0044 through the LVDS balanced twisted pair.

LVDS signals are transmitted to an LMH0044 equalizer through a cable and a connector, the LMH0044 has the characteristics of low power consumption and extremely low jitter of 208 mW, and the LVDS differential signals comprise a multistage adaptive filter inside, after being input from an input end, the LVDS differential signals are firstly filtered through the multistage adaptive filter, then enter a self-bias recovery circuit to completely recover the signals and then are sent to an output driving module to generate an Automatic Equalization Control (AEC) signal, the AEC signal is used for setting the gain and the bandwidth of the adaptive filter in a feedback mode, then a carrier detection module inside generates a carrier detection signal and sends the carrier detection signal to the output driving module, and finally the output driving module outputs the signal through an output pin after being synthesized and sends the signal to a GM8224 decoder for decoding.

The GM8224 decoder utilizes a data and clock recovery technology, and can decode a high-speed LVDS signal which is input in series into 10-bit parallel data and a 1-path clock signal, wherein the serial transmission rate of the high-speed LVDS is between 100 Mb/s and 660 Mb/s.

The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;

secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are referred to, and other structures can refer to the common design, and under the condition of no conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

and finally: the above description is only for the preferred embodiment of the present invention and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-reliability long-distance data transmission system based on LVDS is characterized in that: contain data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, and wherein, the data acquisition encoder for gather high-speed analog signal, ground test platform for receive the instruction that the host computer was issued and forward the data of data acquisition encoder passback to and receive the data of data acquisition encoder passback.

2. A high reliability long distance data transmission system based on LVDS according to claim 1, characterized in that: the data acquisition encoder comprises a high-speed data acquisition module, a first FPGA module, a driver module, an LVDS encoder and a 485 receiver, wherein the output end of the high-speed data acquisition module is connected with the input end of the first FPGA module, the output end of the first FPGA module is connected with the input end of the driver module, the output end of the driver module is connected with the input end of the LVDS encoder, and the output end of the 485 receiver is connected with the input end of the first FPGA module.

3. A high reliability long distance data transmission system based on LVDS according to claim 1, characterized in that: the ground test bench comprises an equalizer, an LVDS decoder, a second FPGA module, a PCI9051 module and a 485 transmitter, wherein the output end of the LVDS encoder is connected with the input end of the equalizer, the output end of the equalizer is connected with the input end of the LVDS encoder, the output end of the LVDS encoder is connected with the input end of the second FPGA module, the second FPGA module is connected with an upper computer through the PCI9051 module, the output end of the second FPGA module is connected with the input end of the 485 transmitter, and the output end of the 485 transmitter is connected with the input end of the 485 receiver.

4. A high reliability long distance data transmission system based on LVDS according to claim 2, characterized in that: the chip model of the VDS encoder is GM 8223.

5. A high reliability long distance data transmission system based on LVDS according to claim 3, characterized in that: the chip model of the LVDS decoder is GM 8224.

6. A high reliability long distance data transmission system based on LVDS according to claim 3, characterized in that: the chip model of the equalizer is LMH 0044.