CN211787486U - Remote data information transmission system based on adjustable amplitude encoder - Google Patents
Remote data information transmission system based on adjustable amplitude encoder Download PDFInfo
- Publication number
- CN211787486U CN211787486U CN202020012022.0U CN202020012022U CN211787486U CN 211787486 U CN211787486 U CN 211787486U CN 202020012022 U CN202020012022 U CN 202020012022U CN 211787486 U CN211787486 U CN 211787486U
- Authority
- CN
- China
- Prior art keywords
- diode
- encoder
- capacitor
- module
- data acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The utility model discloses a remote data information transmission system based on adjustable range encoder contains data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, the data acquisition encoder contains high-speed data acquisition module, first FPGA module, driver module, LVDS encoder, 485 receiver, ground test platform contains adjustable range equalizer, LVDS decoder, second FPGA module, PCI9051 module, 485 and sends the ware, the utility model discloses high-efficient data processing fast improves data transmission's reliability. The utility model discloses an adjustable amplitude equalizer can adjust the slope of the amplitude-frequency response curve of the radio frequency signal in the frequency conversion system through controlling the voltage; the PIN diode is used for replacing a resistor in the equalizer network, so that different amplitude-frequency response curves can be equalized; the gain of the amplitude-frequency response curve can be adjusted between positive and negative slopes.
Description
Technical Field
The utility model relates to a data transmission technical field, more specifically say, the utility model relates to a remote data information transmission system based on adjustable range encoder.
Background
In a certain remote test task, a data acquisition encoder is required to acquire multi-path high-speed analog quantity signals and return the signals to a ground test bench in real time for data detection and processing. Based on the fact that the environment of a cable network used in the task is severe and the surrounding electromagnetic interference is large, for traditional parallel line transmission, although the transmission rate can meet the task requirement, the data quality is seriously reduced under the conditions of high transmission rate and severe environment due to the fact that more interface data lines are needed; the PECL rate, while also meeting the task requirements, is not compatible with standard logic at its interface level; and the data transmission rates of the RS422 and the RS485 can obviously not meet the task requirement, so that the LVDS technology is selected as the solution of the design.
SUMMERY OF THE UTILITY MODEL
In order to overcome prior art's above-mentioned defect, the utility model discloses the problem that reliability is low in high-speed remote transmission in-process to data provides a remote data information transmission system based on adjustable range encoder, and high efficiency is handled data fast, improves data transmission's reliability.
In order to achieve the above object, the utility model provides a following technical scheme:
a remote data information transmission system based on an adjustable amplitude encoder comprises a data acquisition encoder, a ground test board and an upper computer, wherein the data acquisition encoder is connected with the upper computer through the ground test board and used for acquiring high-speed analog quantity signals;
the data acquisition encoder comprises a high-speed data acquisition module, a first FPGA module, a driver module, an LVDS encoder and a 485 receiver, wherein the output end of the high-speed data acquisition module is connected with the input end of the first FPGA module, the output end of the first FPGA module is connected with the input end of the driver module, the output end of the driver module is connected with the input end of the LVDS encoder, and the output end of the 485 receiver is connected with the input end of the first FPGA module;
the ground test bench comprises an adjustable amplitude equalizer, an LVDS decoder, a second FPGA module, a PCI9051 module and a 485 transmitter, wherein the output end of the LVDS encoder is connected with the input end of the adjustable amplitude equalizer, the output end of the adjustable amplitude equalizer is connected with the input end of the LVDS encoder, the output end of the LVDS encoder is connected with the input end of the second FPGA module, the second FPGA module is connected with an upper computer through the PCI9051 module, the output end of the second FPGA module is connected with the input end of the 485 transmitter, and the output end of the 485 transmitter is connected with the input end of the 485 receiver;
the adjustable amplitude equalizer comprises an adjustable amplitude equalization circuit; the adjustable amplitude equalization circuit is used
Changing the internal resistance value of the PIN diode under different voltages by changing the control voltage, and adjusting the slope of the amplitude-frequency response curve of the radio frequency signal; the first input port is connected with the adjustable amplitude equalization circuit through a third capacitor, and the adjustable amplitude equalization circuit is connected with the second output port through a sixth capacitor.
As a further preferred aspect of the present invention, the adjustable amplitude equalization circuit comprises a diode power supply port, a first adjustable voltage port, a second adjustable voltage port, a first inductor, a second inductor, a third inductor, a fourth inductor, a first diode, a second diode, a third diode, a fifth capacitor, a ninth capacitor, and a tenth capacitor; the common anode node of the first diode and the second diode is connected with the first input port through a third capacitor; the diode power supply port is connected with a common anode node of the first diode and the second diode through a first inductor and used for providing 5V control voltage for the first diode, the second diode and the third diode; the cathode of the second diode is grounded through a ninth capacitor; the first regulating voltage port is connected with the cathode of the first diode and the common node of the fifth capacitor through a second inductor;
the cathode of the second diode is connected with the anode of the third diode through a fourth inductor; the anode of the third diode is grounded through a tenth capacitor; the second regulating voltage port is connected with a common node between a fifth capacitor and the cathode of the third diode through a third inductor; and a common node among the third inductor, the fifth capacitor and the cathode of the third diode is directly connected with the second output port through the sixth capacitor.
As a further preferred aspect of the remote data information transmission system based on the adjustable amplitude encoder, the chip model of VDS encoder is GM 8223.
As a further preferred aspect of the present invention, a remote data information transmission system based on an adjustable amplitude encoder, wherein the chip model of the LVDS decoder is GM 8224.
The utility model discloses a technological effect and advantage:
1. the utility model discloses the data acquisition encoder gathers high-speed analog quantity signal, and the ground test board receives the instruction that the host computer was issued and forwards to the data acquisition encoder and receive the data of data acquisition encoder passback, adopts 4 sections 60 m, totally 240 m's balanced twisted pair wire connects data acquisition encoder and ground test board, and the data acquisition encoder sends LVDS data to the ground test board with 500 Mb/s of code rate, handles data more high-efficiently fast, improves data transmission's reliability;
2. the utility model discloses to the problem that data reliability is low in high-speed remote transmission in-process, adopted the signal conditioning technique on hardware circuit, carry out the equilibrium and add the weight processing in advance (going) to the LVDS signal, added a novel 8B/10B codec's optimization mode, greatly strengthened the reliability of transmission link, LVDS data can realize no error code transmission on the balanced twisted pair wire of 240m with the transmission rate of 500 Mb/s;
3. the utility model discloses an adjustable amplitude equalizer can adjust the slope of the amplitude-frequency response curve of the radio frequency signal in the frequency conversion system through controlling the voltage; the PIN diode is used for replacing a resistor in the equalizer network, so that different amplitude-frequency response curves can be equalized; the gain of the amplitude-frequency response curve can be adjusted between positive and negative slopes.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the present invention;
FIG. 2 is a schematic diagram of the data acquisition encoder of the present invention;
FIG. 3 is a schematic structural diagram of the ground test bench of the present invention;
fig. 4 is a circuit diagram of the adjustable amplitude equalizer of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides a remote data information transmission system based on adjustable range encoder, as shown in FIG. 1, contain data acquisition encoder, ground test platform and host computer, the data acquisition encoder passes through ground test platform and connects the host computer, and wherein, the data acquisition encoder for gather high-speed analog signal, ground test platform for receive the instruction that the host computer was issued and forward the data of data acquisition encoder and receipt data acquisition encoder passback. The utility model discloses a 4 sections 60 m, total 240 m's balanced twisted pair wire connects data acquisition encoder and ground test board, and the data acquisition encoder sends LVDS data with 500 Mb/s' code rate to ground test board, verifies the feasibility and the reliability of this scheme through the correctness of the data of testboard readback.
As shown in fig. 2, the data acquisition encoder includes a high-speed data acquisition module, a first FPGA module, a driver module, an LVDS encoder, and a 485 receiver, wherein an output end of the high-speed data acquisition module is connected to an input end of the first FPGA module, an output end of the first FPGA module is connected to an input end of the driver module, an output end of the driver module is connected to an input end of the LVDS encoder, and an output end of the 485 receiver is connected to an input end of the first FPGA module.
As shown in fig. 3, the ground test platform includes an adjustable amplitude equalizer, an LVDS decoder, a second FPGA module, a PCI9051 module, and a 485 transmitter, wherein an output end of the LVDS encoder is connected to an input end of the adjustable amplitude equalizer, an output end of the adjustable amplitude equalizer is connected to an input end of the LVDS encoder, an output end of the LVDS encoder is connected to an input end of the second FPGA module, the second FPGA module is connected to an upper computer through the PCI9051 module, an output end of the second FPGA module is connected to an input end of the 485 transmitter, and an output end of the 485 transmitter is connected to an input end of the.
Aiming at the problem of low reliability of data in the process of high-speed long-distance transmission, a signal conditioning technology is adopted on a hardware circuit to carry out equalization and pre (de) emphasis processing on LVDS signals, a novel optimization mode of 8B/10B coding and decoding is added, the reliability of a transmission link is greatly enhanced, and the LVDS data can be transmitted without error on a balanced twisted pair wire of 240m at the transmission rate of 500 Mb/s.
As shown in fig. 4, the adjustable amplitude equalizer includes an adjustable amplitude equalization circuit; said adjustable amplitude
The equalizing circuit is used for changing the internal resistance value of the PIN diode under different voltages by changing the control voltage and adjusting the slope of the amplitude-frequency response curve of the radio frequency signal; the first input port P1 is connected to the adjustable amplitude equalization circuit through a third capacitor C3, and the adjustable amplitude equalization circuit is connected to a second output port P2 through a sixth capacitor C6;
the adjustable amplitude equalization circuit comprises a diode power supply port P3, a first adjusting voltage port P4, a second adjusting voltage port P5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first diode D1, a second diode D2, a third diode D3, a fifth capacitor C5, a ninth capacitor C9 and a tenth capacitor C10; a common anode node of the first diode D1 and the second diode D2 is connected with the first input port P1 through a third capacitor C3; the diode power supply port P3 is connected with a common anode node of a first diode D1 and a second diode D2 through a first inductor L1, and the diode power supply port P3 is used for providing 5V control voltage for a first diode D1, a second diode D2 and a third diode D3; the cathode of the second diode D2 is grounded through a ninth capacitor C9; the first regulated voltage port P4 is connected to the common node of the cathode of the first diode D1 and the fifth capacitor C5 through the second inductor L2;
the cathode of the second diode D2 and the anode of the third diode D3 are connected through a fourth inductor L4; the anode of the third diode D3 is grounded through a tenth capacitor C10; the second regulated voltage port P5 is connected to the common node between the fifth capacitor C5 and the cathode of the third diode D3 through a third inductor L3; a common node between the third inductor L3, the fifth capacitor C5 and the cathode of the third diode D3 is directly connected to the second output port P2 through the sixth capacitor C6.
In order to actively respond to the demand of imported electronic components localization, support the development of "chinese core" engineering, avoid appearing imported electronic components simultaneously because shut down, forbidden shelves problem and the safety problem that inserts wooden horse etc. to the chip, the utility model discloses use the LVDS serializer and deserializer of import in having given up traditional design, through the LVDS interface product of the internal chip firm of contrast, selected and accorded with the utility model discloses the required LVDS encoder GM8223 and LVDS decoder GM8224 that become all the core that shakes.
Due to the skin effect and the dielectric loss, the high-speed LVDS signals are attenuated in cable transmission, and the signal attenuation caused by the high-speed LVDS signals is respectively proportional to the square root of the transmission frequency and the transmission rate, and especially in the process of high-speed long-distance transmission, the attenuation in cable transmission is the main reason for signal instability. In order to ensure the transmission quality of data, the design adopts a signal conditioning technology aiming at a transmission rate of 500 Mb/s and a long distance of 240m, and the design requirement is met by equalizing and pre (de) emphasizing the signal.
The GM8223 encoder receives a 10-bit parallel TTL data signal and a path of TTL clock signal from the FPGA, converts the TTL data signal into 1 pair of LVDS serial data signals and outputs the LVDS serial data signals to a serial digital cable driver LMH0002, and the serial transmission rate of the GM8223 is 100 Mb/s-660 Mb/s.
The data transmission rate of the LMH0002 driver can reach 1.485 Gb/s, and the differential voltage output by the GM8223 can be increased, so that the transmission distance of data on a transmission line is effectively increased. The signal is output by the output end of the LMH0002 and then transmitted to the receiving end of the LMH0044 through the LVDS balanced twisted pair.
LVDS signals are transmitted to an LMH0044 adjustable amplitude equalizer through a cable and a connector, the LMH0044 has the characteristics of low power consumption and extremely low jitter of 208 mW, and the LVDS differential signals internally comprise a multistage adaptive filter, after being input from an input end, the LVDS differential signals are firstly filtered through the multistage adaptive filter, then enter an automatic bias recovery circuit to completely recover the signals and then are sent to an output driving module to generate an Automatic Equalization Control (AEC) signal, the AEC signal is used for setting the gain and the bandwidth of the adaptive filter in a feedback mode, then an internal carrier detection module generates a carrier detection signal and sends the carrier detection signal to the output driving module, and finally the output driving module outputs the signal through an output pin after being synthesized and sends the signal to a GM8224 decoder for decoding.
The GM8224 decoder utilizes a data and clock recovery technology, and can decode a high-speed LVDS signal which is input in series into 10-bit parallel data and a 1-path clock signal, wherein the serial transmission rate of the high-speed LVDS is between 100 Mb/s and 660 Mb/s.
The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;
secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are referred to, and other structures can refer to the common design, and under the condition of no conflict, the same embodiment and different embodiments of the present invention can be combined with each other;
and finally: the above description is only for the preferred embodiment of the present invention and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. A remote data information transmission system based on an adjustable amplitude encoder is characterized in that: the system comprises a data acquisition encoder, a ground test board and an upper computer, wherein the data acquisition encoder is connected with the upper computer through the ground test board, the data acquisition encoder is used for acquiring high-speed analog quantity signals, and the ground test board is used for receiving instructions sent by the upper computer, forwarding the instructions to the data acquisition encoder and receiving data returned by the data acquisition encoder;
the data acquisition encoder comprises a high-speed data acquisition module, a first FPGA module, a driver module, an LVDS encoder and a 485 receiver, wherein the output end of the high-speed data acquisition module is connected with the input end of the first FPGA module, the output end of the first FPGA module is connected with the input end of the driver module, the output end of the driver module is connected with the input end of the LVDS encoder, and the output end of the 485 receiver is connected with the input end of the first FPGA module;
the ground test bench comprises an adjustable amplitude equalizer, an LVDS decoder, a second FPGA module, a PCI9051 module and a 485 transmitter, wherein the output end of the LVDS encoder is connected with the input end of the adjustable amplitude equalizer, the output end of the adjustable amplitude equalizer is connected with the input end of the LVDS encoder, the output end of the LVDS encoder is connected with the input end of the second FPGA module, the second FPGA module is connected with an upper computer through the PCI9051 module, the output end of the second FPGA module is connected with the input end of the 485 transmitter, and the output end of the 485 transmitter is connected with the input end of the 485 receiver;
the adjustable amplitude equalizer comprises an adjustable amplitude equalization circuit; the adjustable amplitude equalization circuit is used for changing the internal resistance value of the PIN diode under different voltages by changing the control voltage and adjusting the slope of the amplitude-frequency response curve of the radio frequency signal;
the adjustable amplitude equalization circuit comprises a first input port (P1), a second output port (P2), a diode power supply port (P3), a first adjusting voltage port (P4), a second adjusting voltage port (P5), a first inductor (L1), a second inductor (L2), a third inductor (L3), a fourth inductor (L4), a first diode (D1), a second diode (D2), a third diode (D3), a fifth capacitor (C5), a ninth capacitor (C9) and a tenth capacitor (C10); the common anode node of the first diode (D1) and the second diode (D2) is connected with the first input port (P1) through a third capacitor (C3); the diode power supply port (P3) is connected with a common anode node of a first diode (D1) and a second diode (D2) through a first inductor (L1), and the diode power supply port (P3) is used for providing a 5V control voltage for the first diode (D1), the second diode (D2) and the third diode (D3); the cathode of the second diode (D2) is grounded through a ninth capacitor (C9); the first regulating voltage port (P4) is connected with a common node of a cathode of the first diode (D1) and a fifth capacitor (C5) through a second inductor (L2);
the cathode of the second diode (D2) and the anode of the third diode (D3) are connected through a fourth inductor (L4); the anode of the third diode (D3) is connected to ground through a tenth capacitor (C10); the second regulated voltage port (P5) is connected to a common node between the fifth capacitor (C5) and the cathode of a third diode (D3) through a third inductor (L3); a common node among the third inductor (L3), the fifth capacitor (C5) and the cathode of the third diode (D3) is directly connected with the second output port (P2) through the sixth capacitor (C6);
the first input port (P1) is connected to the adjustable amplitude equalizing circuit via a third capacitor (C3), and the adjustable amplitude equalizing circuit is connected to the second output port (P2) via a sixth capacitor (C6).
2. A system for transmitting data over a distance based on an adjustable amplitude encoder as claimed in claim 1, wherein: the chip model of the VDS encoder is GM 8223.
3. A system for transmitting data over a distance based on an adjustable amplitude encoder as claimed in claim 1, wherein: the chip model of the LVDS decoder is GM 8224.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020012022.0U CN211787486U (en) | 2020-01-04 | 2020-01-04 | Remote data information transmission system based on adjustable amplitude encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020012022.0U CN211787486U (en) | 2020-01-04 | 2020-01-04 | Remote data information transmission system based on adjustable amplitude encoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211787486U true CN211787486U (en) | 2020-10-27 |
Family
ID=72888187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020012022.0U Expired - Fee Related CN211787486U (en) | 2020-01-04 | 2020-01-04 | Remote data information transmission system based on adjustable amplitude encoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211787486U (en) |
-
2020
- 2020-01-04 CN CN202020012022.0U patent/CN211787486U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8175172B2 (en) | High speed digital galvanic isolator with integrated low-voltage differential signal interface | |
| US20110103267A1 (en) | Asymmetric full duplex communication including device power communication | |
| CN101232477A (en) | Method and device for compensating baseline dissociation as well as Ethernet circuit device | |
| CN112399387B (en) | Link training method for multi-rate bidirectional transmission system | |
| US20130073749A1 (en) | Backchannel communication between host and interface module | |
| CN111314252B (en) | Self-adaptive equalization method and system for high-speed serial port transceiver | |
| CN104639899A (en) | High-definition SDI (Serial Digital Interface) digital video signal optical fiber transparent transmission device | |
| CN108183696A (en) | A kind of low-voltage high speed may be programmed equalizing circuit | |
| DE102018005553B4 (en) | High-speed solutions for coupling links with support for continuous-time reverse channel communication | |
| CN104253695A (en) | Direct-connected medium converter | |
| CN116915278A (en) | SERDES circuit and electronic device | |
| CN211787486U (en) | Remote data information transmission system based on adjustable amplitude encoder | |
| DE102018005554B4 (en) | High-speed interconnect link solutions with support for continuous-time, in-band return channel communications and proprietary features | |
| CN117441294A (en) | Network for reducing crosstalk using asymmetric uplink and downlink baud rates | |
| CN210835692U (en) | High-reliability remote data transmission system based on LVDS | |
| US10944601B2 (en) | Reception circuit, receiver, and reception control method | |
| CN102065039A (en) | High-speed interface circuit adaptive equalization method and circuit therefor | |
| CN116974971A (en) | Bidirectional transmitting and receiving SERDES circuit and electronic equipment | |
| CN111436012B (en) | Signal processing system, switch, and optical module | |
| CN1334663A (en) | Long-distance transmission method for signals of Ethernet | |
| US11451417B1 (en) | Power-efficient nonlinear equalizers and methods | |
| CN102684945A (en) | Test access port (TAP) equipment | |
| CN104052642B (en) | A kind of communication system and communication means | |
| CN113965262A (en) | Network cable | |
| CN106209236A (en) | High-speed communication generates transmission and obtains supervisory control signals system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20201027 Termination date: 20210104 |